CN104967794B - Power supply noise cancellation circuit suitable for CMOS image sensor - Google Patents
Power supply noise cancellation circuit suitable for CMOS image sensor Download PDFInfo
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Abstract
The invention provides a power noise cancellation circuit suitable for a CMOS image sensor, comprising: the first noise path outputs a first output noise signal through the source follower transistor, and the first noise path is an all-pass network with the same capacitance proportion gain and consistent phase; the power supply noise is output to a second output noise signal through the proportion adjusting module, the second noise path is an all-pass network with the same capacitance proportion gain and consistent phase, and the first output noise signal and the second output noise signal cancel noise mutually. The power supply noise of the source following transistor is counteracted through the two noise paths, so that the purposes of resisting power supply interference, reducing image noise and improving image quality are achieved.
Description
Technical Field
The present invention relates to the field of analog circuit design of CMOS image sensors, and more particularly, to a power noise cancellation circuit suitable for CMOS image sensors.
Background
An image sensor, an important component of a digital camera, is an apparatus for converting an optical image into an electrical signal, and is widely used in digital cameras, mobile terminals, portable electronic devices, and other electronic optical apparatuses. Image sensors can be classified into two main types, CCD (Charge Coupled Device ) and CMOS (Complementary Metal oxide Semiconductor, complementary metal oxide semiconductor) image sensors, according to the elements.
In addition to large-scale application to digital cameras, CCD image sensors are widely used in video cameras, scanners, industrial fields, and the like. The CMOS image sensor has the advantages of high integration, low power consumption, programmable local pixel reading, high speed, low cost and the like, and can be applied to the fields of digital cameras, PC cameras, mobile communication products and the like.
With the continued rapid development of image sensors, further miniaturization and integration thereof is promoted. Both CCD image sensors and CMOS image sensors employ a photoelectric conversion region, typically a photodiode (Photodiode or Photodetector), to collect incident light and convert it into photo-charges that can be image-processed. In the existing CMOS image sensor, a pixel array formed by a plurality of pixel units receives incident light and collects photons. The pixel unit usually adopts a 3T, 4T or 5T structure, taking 4T as an example, and comprises a transfer Transistor (Transfer Transistor, TX), a Reset Transistor (RST), a Source follower Transistor (Source-Follower Transistor, SF) and a row gate tube (Row Selector Transistor, RSEL), wherein the basic working principle is as follows: the photoelectric conversion is used for forming photo-generated carriers, generating analog signals, and reading the analog signals of each column by gating and row-column reading the rows of the pixel array, so that the subsequent signal processing processes such as operation gain amplification, analog-digital conversion and the like are performed.
In actual operation, noise of a power supply of a source follower transistor SF of a pixel (pixel) is amplified through a signal path and then reflected on output data after analog-to-digital (AD) conversion, so that an image signal-to-noise ratio is affected. It is common practice to make a pixel circuit LDO (Low Dropout Regulator) alone to reduce the effect of external power supply noise on image quality. If the output of the LDO is affected, noise is also reflected on the image. One solution, in the case of LDO noise suppression performance limitations, is to introduce another path of supply noise in the signal path to cancel out the incoming portion from the pixel. The conventional approach is to make an LDO for the pixel power supply to isolate noise on the external power supply. When the chip interference is large, the method has limited stabilizing speed, and noise can still be reflected on the image in the stabilizing process.
Disclosure of Invention
In view of the understanding of the technical problems in the background art, it would be beneficial to improve the overall performance of a circuit if a circuit design could be provided that effectively eliminates the power supply noise of the image sensor source follower transistor.
The present invention provides a power supply noise cancellation circuit suitable for a CMOS image sensor, the circuit comprising:
the first noise path outputs a first output noise signal through the source follower transistor, and the first noise path is an all-pass network with the same capacitance proportion gain and consistent phase;
the power supply noise is output to a second output noise signal through the proportion adjusting module, the second noise path is an all-pass network with the same capacitance proportion gain and consistent phase, and the first output noise signal and the second output noise signal cancel noise mutually.
In an embodiment, in the second noise path, the power noise is connected to a node of the ramp voltage signal through the proportion adjustment module and then connected to the comparator, and the output second output noise signal has the same amplitude and the same phase as the first output noise signal.
In one embodiment, the phase uniformity is a phase error within 30 degrees.
In an embodiment, the proportion adjusting module is a resistance adjusting module, a first end of the resistance adjusting module is connected with a power supply of the source follower transistor, and the power supply is connected with a second end of the resistor group through selection control; one end of the bias resistor is connected with the second end, and the other end of the bias resistor is connected with the ground; the current source is connected to the second end.
In an embodiment, the size of the selection control resistor group is adjusted to adjust the ratio of the equivalent resistance of the resistor group to the bias resistance, thereby adjusting the second output noise signal.
In an embodiment, the selectively controlled resistor group is a resistor connected in parallel, and each branch is respectively provided with a switch.
In one embodiment, the first noise path comprises: the first capacitor is connected with the source following transistor, couples power noise to the floating diffusion region, and outputs the power noise to the first sub-output end through the source following transistor, one end of the first sub-output end is connected with the bias module, and the other end of the first sub-output end is connected with the comparator.
In one embodiment, the gain of the first output noise signal is calculated according to the ratio of the first capacitance to the second capacitance; and calculating the gain of the second output noise signal through the ratio of the equivalent resistance of the resistor group to the bias resistance, wherein the gain of the first output noise signal is the same as the gain of the second output noise signal.
The second noise path is introduced, and the power supply noise of the source following transistor is counteracted through the two noise paths, so that the purposes of resisting power supply interference, reducing image noise and improving image quality are achieved.
Drawings
FIG. 1 is a schematic circuit diagram of a first noise path involved in a first embodiment of the present invention;
fig. 2 is a circuit schematic of a second noise path involved in the first embodiment of the present invention.
Detailed Description
The invention provides a power noise cancellation circuit suitable for a CMOS image sensor, comprising: the first noise path outputs a first output noise signal through the source follower transistor, and the first noise path is an all-pass network with the same capacitance proportion gain and consistent phase; the power supply noise is output to a second output noise signal through the proportion adjusting module, the second noise path is an all-pass network with the same capacitance proportion gain and consistent phase, and the first output noise signal and the second output noise signal cancel noise mutually.
The following describes the present invention in detail with reference to examples.
Referring to fig. 1 and 2, fig. 1 is a schematic circuit diagram of a first noise path according to a first embodiment of the present invention. Fig. 2 is a circuit schematic of a second noise path according to the first embodiment of the present invention. In fig. 1, a first terminal 1001 of a source follower transistor 100 of the pixel unit of the image sensor is connected to a power signal VPIX, a second terminal 1002 of the source follower transistor 100 is connected to a floating diffusion FD, and a third terminal 1003 of the source follower transistor 100 is connected to a bias module 200 and a first sub output terminal pda; wherein the first noise path further comprises: the first capacitor 110Cpar and the second capacitor 120Cfd connected to the source follower transistor 100, the first capacitor 110 couples the power supply noise of the power supply signal to the floating diffusion FD and outputs to the first sub-output terminal pda through the source follower transistor 100. The first noise path further includes: bias module 200, comparator 600. The bias module 200 includes: the first terminal 2011 of the first transistor 201 is connected to the third terminal 1003 of the source follower transistor 100, the second terminal 1002 of the first transistor 201 is connected to the first terminal 2021 of the second transistor 202, the second terminal of the second transistor 202 is grounded, and the third terminal of the second transistor 202 is connected to the bias capacitor 210. The comparator includes: a ninth transistor 601, a tenth transistor 602, an eleventh transistor 603, a twelfth transistor 604, a thirteenth transistor 605, and a fourteenth transistor 606. The first end 6001 of the comparator is connected to the first sub-output end pxda, the second end 6002 of the comparator is connected to the output end pxdo, and the third end 6003 of the comparator is connected to the ramp signal Vramp. Wherein, the output end pxdo is the same as the phase of the ramp signal Vramp. The gain of the first output noise signal is calculated in the first noise path by the ratio of the first capacitance 110 to the second capacitance 120. The source follower transistor 100, the first transistor 201, the second transistor 202, the eleventh transistor 603, the twelfth transistor 604, the thirteenth transistor 605, and the fourteenth transistor 606 are NMOS transistors; the ninth transistor 601 and the tenth transistor 602 are PMOS transistors.
Referring to fig. 2, in the second noise path, it includes: the proportional adjustment module 400', the node of the proportional adjustment module 400' connected to the ramp signal Vramp is connected to the comparator 600, in this embodiment, the proportional adjustment module 400 'is a resistance adjustment module, and the first end 401' of the resistance adjustment module is connected to the power supply signal VPIX of the source follower transistor 100; the resistance adjustment module includes: the power supply signal is connected to the second terminal 402 'through the selection control resistor group 420' and the bias resistor 430', one end of the bias resistor 430' is connected to the second terminal 402 'and connected to the current source 440', and the other end is grounded. The selection control resistor group 420 'is composed of a plurality of resistors connected in parallel, each branch is provided with a switch suitable for controlling the conduction of each resistor passage, the resistance value of each branch is set according to the proportion of 2 times, the size of the equivalent resistor of the selection control resistor group is adjusted, the ratio of the equivalent resistor to the bias resistor 430' is adjusted, and the second output noise signal is adjusted. Wherein the ratio of the resistor group equivalent resistance to the bias resistance 430' is between 10:1 and 20:1. In this embodiment, the second output noise signal has the same amplitude and the same phase as the first output noise signal.
Please refer to fig. 1 and fig. 2 simultaneously; the gain of the first output noise signal is calculated through the ratio of the first capacitor 110 to the second capacitor 120, the first noise path is an all-pass network with the same capacitance proportion gain and consistent phase, and the high-frequency capacitance proportion gain and the low-frequency capacitance proportion gain of the source follower transistor 100 in the first noise path are the same and consistent in phase; the gain of the second output noise signal is calculated through the ratio of the equivalent capacitance of the resistor group to the bias resistor 430', the second noise path is an all-pass network with the same capacitance proportion gain and consistent phase, and the high-frequency capacitance proportion gain and the low-frequency capacitance proportion gain of the proportion adjustment module 400' in the second noise path are the same and consistent in phase; phase coincidence is a phase error within 30 degrees. The gain of the first output noise signal is the same as the gain of the second output noise signal, and the phases are the same to cancel each other.
In the first noise path, the gain at the first sub-output end pxda is:
in the second noise path, the noise on the power supply is introduced to the ramp signal Vramp through the equivalent capacitance of the resistor group and the voltage division of the bias resistor 430', and then quantized to the digital domain through the comparator 600 to the output end pxdo for being reflected on the image.
The gain to the ramp signal vramp is:
because vramp is opposite in phase to the gain at pda to pdo; so to eliminate the noise on the power supply, the gain amplitude and the phase of the power supply are the same as those of the vramp and the pda
The equivalent capacitance of the resistor group can be controlled by selecting the resistor group so that
In this way, the noise on the power supply reaches the positive and negative input ends of the comparator 600 through the two paths respectively, the amplitude values are the same, the signs are the same, and the noise is counteracted at the comparator 600, so that the purpose of suppressing the noise of the power supply of the pixel unit is achieved.
While the invention has been illustrated and described in detail in the drawings and foregoing description, the same is to be considered as illustrative and exemplary and not restrictive in character. The present invention is not limited to the above embodiments.
Other variations to the disclosed embodiments can be understood and effected by those skilled in the art by studying the specification, the disclosure, and the appended claims. In the practice of the invention, a single component may perform the functions of several of the features recited in the claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. Any reference signs in the claims shall not be construed as limiting the scope.
Claims (7)
1. A power supply noise cancellation circuit suitable for use in a CMOS image sensor, the circuit comprising:
the first end of a source following transistor of the pixel unit of the image sensor is connected with a power supply signal, the second end of the source following transistor is connected with a floating diffusion area, and the third end of the source following transistor is connected with a bias module and a first sub output end;
the power supply noise is connected with the comparator through the first sub-output end of the source follower transistor, and the first noise path is an all-pass network with the same capacitance proportion gain and consistent phase;
the power supply noise is connected to the comparator through a node which outputs a second output noise signal to the slope voltage signal through the proportion adjusting module, and the second noise path is an all-pass network with the same capacitance proportion gain and consistent phase;
the power supply noise on the source follower transistor respectively outputs the first output noise signal and the second output noise signal to the positive and negative input ends of the comparator through two noise paths, and the amplitude and the phase of the power supply noise are the same, so that the power supply noise and the second output noise are mutually offset at the comparator.
2. The power supply noise cancellation circuit for a CMOS image sensor according to claim 1, wherein the so-called phase coincidence is a phase error within 30 degrees.
3. The power supply noise cancellation circuit for a CMOS image sensor according to claim 2, wherein the ratio adjustment module is a resistance adjustment module, a first end of the resistance adjustment module is connected to a power supply of a source follower transistor, and the power supply is connected to a second end through a selection control resistor; one end of the bias resistor is connected with the second end, and the other end of the bias resistor is connected with the ground; the current source is connected to the second end.
4. The power noise cancellation circuit of claim 3, wherein the size of the selection control resistor group is adjusted to adjust the ratio of the equivalent resistance of the resistor group to the bias resistance to adjust the second output noise signal.
5. The power noise cancellation circuit for a CMOS image sensor according to claim 4, wherein the selection control resistor group is a resistor connected in parallel, and each branch is provided with a switch.
6. The power supply noise cancellation circuit for a CMOS image sensor of claim 3, wherein the first noise path comprises: the first capacitor is connected with the source following transistor, couples power noise to the floating diffusion region, and outputs the power noise to the first sub-output end through the source following transistor, one end of the first sub-output end is connected with the bias module, and the other end of the first sub-output end is connected with the comparator.
7. The power noise cancellation circuit for a CMOS image sensor according to claim 6, wherein the gain of the first output noise signal is calculated from a ratio of the first capacitance to the second capacitance; and calculating the gain of the second output noise signal through the ratio of the equivalent resistance of the resistor group to the bias resistance, wherein the gain of the first output noise signal is the same as the gain of the second output noise signal.
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| CN113365005B (en) * | 2020-03-06 | 2023-06-09 | 格科微电子（上海）有限公司 | Implementation method of image sensor column processing module blocking capacitor |
| CN113473046B (en) * | 2020-03-31 | 2023-11-24 | 比亚迪半导体股份有限公司 | Ramp signal generator and image sensor |
| CN113890552B (en) * | 2021-11-12 | 2023-03-24 | 四川创安微电子有限公司 | Image sensor pixel power supply noise cancellation device and cancellation method |
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