CN204887209U - Power noise cancellation circuit suitable for CMOS image sensor - Google Patents
Power noise cancellation circuit suitable for CMOS image sensor Download PDFInfo
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- CN204887209U CN204887209U CN201520550336.5U CN201520550336U CN204887209U CN 204887209 U CN204887209 U CN 204887209U CN 201520550336 U CN201520550336 U CN 201520550336U CN 204887209 U CN204887209 U CN 204887209U
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Abstract
The utility model provides a power noise cancellation circuit suitable for CMOS image sensor, include: first noise channel, the first output noise signal of transistor output is followed through the source to the power supply noise, it is the same that first noise channel is electric capacity proportional gain, the allpass network of phase coincidence, second noise channel, power supply noise pass through ratio adjustment module output second output noise signal, it is the same that the second noise channel is electric capacity proportional gain, the allpass network of phase coincidence, first output noise signal and second output noise signal cancel each other out noise. Power supply noise through following the source in the transistor is offset through two noise channels, plays anti power supply interference, reduces the picture noise, improves image quality's purpose.
Description
Technical field
The utility model relates to cmos image sensor Analog Circuit Design field, particularly a kind of power supply noise bucking circuit being applicable to cmos image sensor.
Background technology
Imageing sensor is the important component part of digital camera, and be a kind of equipment optical imagery being converted to electrical signal, it is widely used in digital camera, mobile terminal, portable electron device and other electro-optical devices.Imageing sensor is according to the difference of element, CCD(ChargeCoupledDevice can be divided into, charge coupled cell) and CMOS(ComplementaryMetaloxideSemiconductor, CMOS (Complementary Metal Oxide Semiconductor) element) the large class of imageing sensor two.
Ccd image sensor, except large-scale application is except digital camera, is also widely used in video camera, scanner and industrial circle etc.And cmos image sensor reads immediately because its Highgrade integration, low-power consumption and local pixel are able to programme, speed is fast, low cost and other advantages, be applicable to the fields such as digital camera, PC video camera, mobile communication product.
Along with the development continuously and healthily of imageing sensor, facilitate that it is further miniaturized and integrated.Ccd image sensor and cmos image sensor are all adopt photoelectric conversion regions, generally adopt photodiode (PhotodiodeorPhotodetector) to collect incident light, and are converted into the optical charge that can carry out image procossing.In existing cmos image sensor, the pel array of several pixel cells composition receives incident light, collects photon.Pixel cell often adopts 3T, the structure of 4T or 5T, for 4T, by transfering transistor (TransferTransistor, TX), reset transistor (ResetTransistor, RST), transistor (Source-FollowerTransistor is followed in source, SF), row gate tube (RowSelectorTransistor, RSEL), basic operation principle is: form photo-generated carrier by opto-electronic conversion, produce analog signal, by going forward side by side to the row gating of pel array, ranks read, read the analog signal often arranged, carry out follow-up computing gain to amplify, the signal processings such as analog-to-digital conversion.
In real work the source of pixel (pixel) follow the noise of transistor SF pipe power supply can by electric capacity couple to the floating diffusion region FD of pixel cell, then be exaggerated by signal path, embody after analog-to-digital conversion (AD) conversion and export in data, affect signal noise ratio (snr) of image.Common practices is for pixel circuit does separately a LDO (LowDropoutRegulator), to reduce the impact of externally fed power supply noise on picture quality.If the output of LDO is affected, noise is same or can embody on image.When LDO noise suppressed limited capacity, a kind of solution is, introduces an other road power supply noise in signal path, is used for offsetting the part imported into from pixel.Traditional approach is for pixel power supply is a LDO, in order to the noise on isolating exterior power supply.This method is when chip interference is larger, and its stabilized speed is limited, and in the process that it is stable, noise still can embody on image.
Utility model content
In view of the understanding to the technical problem in background technology, if a kind of effective removal of images sensor source can be provided to follow the circuit design of the power supply noise of transistor, be useful to the lifting of circuit integrity performance.
The utility model provides a kind of power supply noise bucking circuit being applicable to cmos image sensor, and described circuit comprises:
First noise channel, power supply noise is followed transistor by source and is exported the first output noise signal, and described first noise channel is that capacitance ratio gain is identical, the all-pass network that phase place is consistent;
Second noise channel, power supply noise passing ratio adjustment module exports the second output noise signal, described second noise channel is that capacitance ratio gain is identical, the all-pass network that phase place is consistent, and described first output noise signal and the second output noise signal are cancelled out each other noise.
In one embodiment, in described second noise channel, the node that described power supply noise passing ratio adjustment module is connected to ramp voltage signal is connected to comparator again, and the second output noise signal of output is identical with the first output noise signal amplitude, and phase place is identical.
In one embodiment, so-called phase place is unanimously that phase error is within 30 degree.
In one embodiment, described proportion adjustment module is resistance adjustment module, and the power supply of transistor is followed in the first termination source of described resistance adjustment module, and described power supply connects the second end through selecting controlling resistance group; Second end described in one termination of biasing resistor, other end ground connection; Current source connects the second end.
In one embodiment, the size of the selection controlling resistance group described in adjustment, with the ratio of the equivalent resistance of regulating resistance group and described biasing resistor, and then regulates the second output noise signal.
In one embodiment, described selection controlling resistance group is resistance in parallel, and each branch road is respectively arranged with switch.
In one embodiment, first noise channel comprises: the first electric capacity and second electric capacity of transistor are followed in the source of being connected to, power supply noise is coupled to floating diffusion region by described first electric capacity, and follow transistor by described source and export the first sub-output to, one end of first sub-output connects biasing module, and the other end connects comparator.
In one embodiment, the gain of the first output noise signal is calculated according to the ratio meter of the first electric capacity and the second electric capacity; Calculated the gain of the second output noise signal by the ratio meter of resistor group equivalent resistance and described biasing resistor, the gain of described first output noise signal is identical with the gain of the second output noise signal.
The utility model introduces the second noise channel, is offset, play anti-power supply disturbance by the power supply noise of source being followed transistor by two noise channels, reduces picture noise, improves the object of picture quality.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of the first noise channel related in the utility model first embodiment;
Fig. 2 is the circuit diagram of the second noise channel related in the utility model first embodiment.
Embodiment
The utility model provides a kind of power supply noise bucking circuit being applicable to cmos image sensor, circuit comprises: the first noise channel, power supply noise is followed transistor by source and is exported the first output noise signal, described first noise channel is that capacitance ratio gain is identical, the all-pass network that phase place is consistent; Second noise channel, power supply noise passing ratio adjustment module exports the second output noise signal, described second noise channel is that capacitance ratio gain is identical, the all-pass network that phase place is consistent, and described first output noise signal and the second output noise signal are cancelled out each other noise.
Below in conjunction with embodiment, particular content of the present utility model is described in detail.
Please refer to Fig. 1, Fig. 2, Fig. 1 is the circuit diagram of the first noise channel related in the utility model first embodiment.Fig. 2 is the circuit diagram of the second noise channel related in the utility model first embodiment.In Fig. 1, the first end 1001 that transistor 100 is followed in the source of image sensor pixel cells meets power supply signal VPIX, the second end 1002 that transistor 100 is followed in source meets floating diffusion region FD, and the 3rd end 1003 that transistor 100 is followed in source meets biasing module 200 and the first sub-output end p xda; Wherein the first noise channel also comprises: the first electric capacity 110Cpar and the second electric capacity 120Cfd of transistor 100 are followed in the source of being connected to, the power supply noise of power supply signal is coupled to floating diffusion region FD by the first electric capacity 110, and follows transistor 100 by source and export the first sub-output end p xda to and connect.First noise channel also includes: biasing module 200, comparator 600.Biasing module 200 comprises: the first transistor 201, transistor seconds 202, the first end 2011 of the first transistor 201 connects the 3rd end 1003 that transistor 100 is followed in source, second end 1002 of the first transistor 201 connects the first end 2021 of transistor seconds 202, second end ground connection of transistor seconds 202, the 3rd termination partially installing capacitor 210 of transistor seconds 202.Comparator comprises: the 9th transistor 601, the tenth transistor the 602, the 11 transistor 603, the tenth two-transistor the 604, the 13 transistor the 605, the 14 transistor 606.Wherein, comparator first end 6001 meets the first sub-output end p xda, and comparator second end 6002 meets output end p xdo, and comparator the 3rd end 6003 meets ramp signal Vramp.Wherein, output end p xdo is identical with ramp signal Vramp phase place.Calculated the gain of the first output noise signal by the ratio meter of the first electric capacity 110 and the second electric capacity 120 in the first noise channel.Wherein, transistor 100 is followed in source, the first transistor 201, transistor seconds 202, the 11 transistor 603, the tenth two-transistor 604, the 13 transistor 605, the 14 transistor 606 be nmos pass transistor; 9th transistor 601, the tenth transistor 602 are PMOS transistor.
Refer to Fig. 2, in the second noise channel, comprise: proportion adjustment module 400 ', the node that proportion adjustment module 400 ' is connected to ramp signal Vramp is connected to comparator 600 again, in the present embodiment, proportion adjustment module 400 ' is resistance adjustment module, and the first end 401 ' of described resistance adjustment module meets the power supply signal VPIX that transistor 100 is followed in source; Resistance adjustment module comprises: select controlling resistance group 420 ' and biasing resistor 430 ', and described power supply signal connects the second end 402 ' through selecting controlling resistance group 420 '; One termination second end 402 ' of biasing resistor 430 ' is also connected to current source 440 ', other end ground connection.Controlling resistance group 420 ' is selected to be made up of the resistance of some parallel connections, each branch road is respectively arranged with the conducting that switch is suitable for controlling each resistive path, the resistance value of each branch road is according to the ratio setting of 2 times, regulate the size of the equivalent resistance selecting controlling resistance group, and then regulate the ratio of equivalent resistance and biasing resistor 430 ', and then regulate the second output noise signal.Wherein, between the ratio 10:1 to 20:1 of resistor group equivalent resistance and biasing resistor 430 '.In the present embodiment, the second output noise signal is identical with the amplitude of the first output noise signal, and phase place is identical.
Please also refer to Fig. 1, Fig. 2; The gain of the first output noise signal is calculated by the ratio meter of the first electric capacity 110 and the second electric capacity 120, first noise channel is that capacitance ratio gain is identical, the all-pass network that phase place is consistent, in first noise channel, to follow the high frequency capacitance proportional gain of transistor 100 identical with low frequency capacitive proportional gain in source, and phase place is consistent; The gain of the second output noise signal is calculated by the ratio meter of resistor group equivalent capacity and biasing resistor 430 ', second noise channel is that capacitance ratio gain is identical, the all-pass network that phase place is consistent, in second noise channel, the high frequency capacitance proportional gain of proportion adjustment module 400 ' is identical with low frequency capacitive proportional gain, and phase place is consistent; So-called phase place is unanimously that phase error is within 30 degree.The gain of the first output noise signal is identical with the gain of the second output noise signal, and phase place is identical to cancel out each other.
In the first noise channel, the first sub-output end p xda place gain is:
In the second noise channel, the noise on power supply is incorporated into ramp signal Vramp place by resistor group equivalent capacity and biasing resistor 430 ' dividing potential drop, then is quantized numeric field by comparator 600 to output end p xdo place and embodies on image.
It to ramp signal vramp place's gain is:
Because vramp and pxda is contrary to the phase place of pxdo place gain; So will eliminate the noise on power supply, as long as its gain range to vramp and pxda place is identical, phase place is identical
Resistor group equivalent capacity size can be passed through to select controlling resistance group, to make
Like this, the noise on power supply arrives the positive-negative input end of comparator 600 respectively by two paths, and its amplitude size is the same, and symbol is identical, and at comparator 600, place cancels out each other, and plays the object suppressing pixel cell power supply noise.
Although illustrate in detail in accompanying drawing and aforesaid description and describe the utility model, it is illustrative and exemplary for should thinking that this is illustrated and describes, instead of restrictive; The utility model is not limited to above-mentioned execution mode.
The those skilled in the art of those the art can pass through research specification, disclosed content and accompanying drawing and appending claims, understand and implement other changes to the execution mode disclosed.In practical application of the present utility model, the function of the multiple technical characteristics quoted during a part possibility enforcement of rights requires.In the claims, word " comprises " element and step of not getting rid of other, and wording " one " does not get rid of plural number.Any Reference numeral in claim should not be construed as the restriction to scope.
Claims (8)
1. be applicable to a power supply noise bucking circuit for cmos image sensor, described circuit comprises:
First noise channel, power supply noise is followed transistor by source and is exported the first output noise signal, and described first noise channel is that capacitance ratio gain is identical, the all-pass network that phase place is consistent;
Second noise channel, power supply noise passing ratio adjustment module exports the second output noise signal, described second noise channel is that capacitance ratio gain is identical, the all-pass network that phase place is consistent, and described first output noise signal and the second output noise signal are cancelled out each other noise.
2. the power supply noise bucking circuit being applicable to cmos image sensor according to claim 1, it is characterized in that, in described second noise channel, the node that described power supply noise passing ratio adjustment module is connected to ramp voltage signal is connected to comparator again, the the second output noise signal exported is identical with the first output noise signal amplitude, and phase place is identical.
3. the power supply noise bucking circuit being applicable to cmos image sensor according to claim 2, is characterized in that, so-called phase place is unanimously that phase error is within 30 degree.
4. the power supply noise bucking circuit being applicable to cmos image sensor according to claim 3, it is characterized in that, described proportion adjustment module is resistance adjustment module, the power supply of transistor is followed in first termination source of described resistance adjustment module, and described power supply connects the second end through selecting controlling resistance group; Second end described in one termination of biasing resistor, other end ground connection; Current source connects the second end.
5. the power supply noise bucking circuit being applicable to cmos image sensor according to claim 4, it is characterized in that, the size of the selection controlling resistance group described in adjustment, with the ratio of the equivalent resistance of regulating resistance group and described biasing resistor, and then regulates the second output noise signal.
6. the power supply noise bucking circuit being applicable to cmos image sensor according to claim 5, is characterized in that, described selection controlling resistance group is resistance in parallel, and each branch road is respectively arranged with switch.
7. the power supply noise bucking circuit being applicable to cmos image sensor according to claim 4, it is characterized in that, first noise channel comprises: the first electric capacity and second electric capacity of transistor are followed in the source of being connected to, power supply noise is coupled to floating diffusion region by described first electric capacity, and follow transistor by described source and export the first sub-output to, one end of first sub-output connects biasing module, and the other end connects comparator.
8. the power supply noise bucking circuit being applicable to cmos image sensor according to claim 7, is characterized in that, calculates the gain of the first output noise signal according to the ratio meter of the first electric capacity and the second electric capacity; Calculated the gain of the second output noise signal by the ratio meter of resistor group equivalent resistance and described biasing resistor, the gain of described first output noise signal is identical with the gain of the second output noise signal.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104967794A (en) * | 2015-07-28 | 2015-10-07 | 格科微电子（上海）有限公司 | Power supply noise canceling circuit suitable for CMOS image sensor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104967794A (en) * | 2015-07-28 | 2015-10-07 | 格科微电子（上海）有限公司 | Power supply noise canceling circuit suitable for CMOS image sensor |
| CN104967794B (en) * | 2015-07-28 | 2023-09-19 | 格科微电子（上海）有限公司 | Power supply noise cancellation circuit suitable for CMOS image sensor |
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