CN212677264U - Power supply noise suppression circuit and image sensor - Google Patents
Power supply noise suppression circuit and image sensor Download PDFInfo
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- CN212677264U CN212677264U CN202022130799.XU CN202022130799U CN212677264U CN 212677264 U CN212677264 U CN 212677264U CN 202022130799 U CN202022130799 U CN 202022130799U CN 212677264 U CN212677264 U CN 212677264U
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Abstract
The utility model relates to a power noise suppression circuit and image sensor, including pixel circuit, comparison signal generation circuit and comparator, the image signal of the first power noise signal of pixel circuit output superpose the noise power to the first input of comparator, comparison signal generation circuit output superpose the comparison signal of the second power noise signal of noise power to the second input of comparator, the second power noise signal is the same with first power noise signal amplitude to offset the power noise of pixel circuit; the comparison signal generating circuit comprises a capacitance adjusting module, a buffer transistor and a bias transistor, wherein the capacitance adjusting module comprises a variable capacitor and a bias capacitor, and the grid electrode of the bias transistor is connected with a bias voltage node and is connected with the first end of the bias capacitor. The utility model discloses a power noise in order to restrain the pixel circuit is introduced to the noise to the comparator, can effectual anti power noise interference, reduce image noise and improve the quality of image.
Description
Technical Field
The utility model relates to an image sensor electronic circuit field especially relates to a power noise suppression circuit and image sensor.
Background
The image sensor is commonly used in various electronic devices, such as video surveillance systems, smart phones, digital cameras, and various electronic products such as intelligent AI, face recognition, etc., for capturing and recognizing image information of a person or a scene. As an important component of digital cameras, it provides for the conversion of optical images into electrical signals. Image sensors can be classified into CMOS (Complementary metal oxide Semiconductor) and CCD (Charge Coupled Device) and image sensors according to their elements.
The CMOS image sensor has the advantages of high integration, low power consumption, programmable and immediate reading of local pixels, high speed, low cost and the like, and can be applied to the fields of digital cameras, PC (personal computer) video cameras, mobile communication products and the like. The CCD image sensor is widely used in scanners and industries, in addition to large-scale digital cameras. Both CMOS image sensors and CCD image sensors employ photoelectric conversion regions, generally photodiodes (photodiodes or photodiodes) to collect incident light and convert it into photocharges that enable image processing. In an existing CMOS image sensor, a pixel array is composed of a plurality of pixel units, and the pixel units usually adopt a 3T, 4T or 5T structure, taking 4T as an example, and are composed of a transfer transistor, a reset transistor, a source follower transistor and a row strobe transistor. The pixel unit performs photoelectric conversion through a photodiode to form a photon-generated carrier, generates an analog signal, and performs subsequent signal processing processes such as operational gain amplification, analog-to-digital conversion and the like by gating and reading rows of the pixel array and reading the analog signal of each column.
In actual operation of the CMOS image sensor, noise sources include pixel power line noise and noise coupled from a pixel control signal line related to a power supply, while noise of a power supply of a source follower transistor (SF tube) of a pixel circuit is coupled to a floating diffusion node (FD) of a pixel unit through a capacitor, and then signal amplification is performed through the source follower transistor, and the signal is reflected on output data after conversion by a digital-to-analog conversion module, which affects a signal-to-noise ratio of an image. The existing processing method is to separately provide a LDO (Low Dropout Regulator) for the pixel circuit to reduce the influence of the noise of the external power supply on the image quality. If the output of the LDO is influenced, the power supply noise can still be reflected on the image, so when the LDO is used for solving the power supply noise, when the chip interference is large, the stabilizing speed of the method is limited, the power supply noise can still be reflected on the image in the stabilizing process, the LDO also occupies a large layout area, consumes power and limits other modules to use a power supply, and the performance of the image sensor chip can be possibly reduced.
SUMMERY OF THE UTILITY MODEL
In view of this, the utility model provides a power noise suppression circuit and image sensor can effectually restrain image sensor's power noise interference, reduce image noise and improve the quality of image.
In order to achieve the above object, a first aspect of the embodiments of the present invention provides a power noise suppression circuit, which is characterized in that the circuit includes a pixel circuit, a comparison signal generation circuit, and a comparator;
the pixel circuit outputs an image signal superimposed with a first power supply noise signal of a noise power supply to a first input terminal of the comparator, the comparison signal generation circuit outputs a comparison signal superimposed with a second power supply noise signal of the noise power supply to a second input terminal of the comparator, and the second power supply noise signal has the same amplitude as the first power supply noise signal so as to cancel power supply noise in the pixel circuit;
the comparison signal generation circuit comprises a capacitance adjusting module, a buffer transistor and a bias transistor, wherein the capacitance adjusting module comprises a variable capacitor and a bias capacitor;
a first end of the variable capacitor is connected with the noise power supply, a second end of the variable capacitor is connected with a first end of the bias capacitor, and a second end of the bias capacitor is grounded;
the buffer transistor and the bias transistor are connected in series between the noise power supply and the ground, the grid electrode of the buffer transistor receives a ramp voltage reference signal, and the grid electrode of the bias transistor is connected to a bias voltage node and connected with a first end of the bias capacitor;
wherein the second power supply noise signal is made to have the same amplitude as the first power supply noise signal by adjusting the value of the variable capacitor to cancel the power supply noise in the pixel circuit.
As one embodiment, the buffer transistor is a first NMOS transistor, and the bias transistor is a second NMOS transistor; the drain electrode of the first NMOS tube is connected with the noise power supply, the grid electrode of the first NMOS tube is connected to a voltage reference signal node, the voltage reference signal is a ramp voltage reference signal, and the source electrode of the first NMOS tube is connected with the second input end of the comparator; the drain electrode of the second NMOS tube is connected with the second input end of the comparator, the grid electrode of the second NMOS tube is connected with the bias voltage node and is connected with the first end of the bias capacitor, and the source electrode of the second NMOS tube is grounded.
In one embodiment, the buffer transistor is a first PMOS transistor, and the bias transistor is a second PMOS transistor; the source electrode of the second PMOS tube is connected with the noise power supply, the grid electrode of the second PMOS tube is connected to a bias voltage node and is connected with the first end of the bias capacitor, and the drain electrode of the second PMOS tube is connected with the second input end of the comparator; the source electrode of the first PMOS tube is connected with the second input end of the comparator, the grid electrode of the first PMOS tube is connected to the voltage reference signal node, the voltage reference signal is a ramp voltage reference signal, and the drain electrode of the first PMOS tube is grounded. Ramp voltage reference signal as an embodiment of the present invention, the bias voltage node is connected to a current mirror circuit to provide a bias voltage.
In one embodiment, the variable capacitor comprises a variable sized capacitor.
In one embodiment, the variable capacitor includes a plurality of constant capacitors connected in parallel, and each branch is provided with a switch to control conduction of each constant capacitor.
In one embodiment, the first input terminal of the comparator is an inverting input terminal, and the second input terminal of the comparator is a non-inverting input terminal.
In one embodiment, the bias capacitor is a variable capacitor.
As one of the embodiments, the pixel circuit includes a first capacitor connected between a drain and a gate of a source follower transistor and a second capacitor connected between the gate of the source follower transistor and a ground, the first capacitor being a total coupling capacitance between a pixel power supply line, a pixel control signal line related to a power supply, and a floating diffusion node, the second capacitor being all parasitic capacitance on the floating diffusion node minus the first capacitor.
As one embodiment, the image signal on which the first power supply noise signal is superimposed is:
the comparison signal on which the second power supply noise signal is superimposed is:
wherein v isnoiseIs a noisy supply voltage, CpIs a first capacitor, CfdIs a second capacitance, CbiasIs the total capacitance of the bias voltage node, MbufIs a buffer transistor that is used to buffer the transistor,Mbiasis a bias transistor, W and L are the width and length of the MOS transistor, gmbsfIs a small signal body transconductance, gm, characterizing a source follower transistorsf、gmbuf、gmbiasTransconductance of a source follower transistor, a buffer transistor and a bias transistor, respectively, by adjusting CcMake the difference value
Minimized for noise suppression.
In order to achieve the above object, a second aspect of the embodiments of the present invention provides an image sensor, which includes, as one of the embodiments, the power supply noise suppression circuit described in any one of the above embodiments.
To sum up, the utility model discloses a set up pixel circuit, comparison signal generation circuit and comparator, wherein, the image signal of the first power noise signal of pixel circuit output superpose the noise power to the first input of comparator, comparison signal generation circuit output superpose the comparison signal of the second power noise signal of noise power to the second input of comparator, the second power noise signal is the same with first power noise signal amplitude, in order to offset the power noise in the pixel circuit; the comparison signal generating circuit comprises a capacitance adjusting module, a buffer transistor and a bias transistor, wherein the capacitance adjusting module comprises a variable capacitor and a bias capacitor; the first end of the variable capacitor is connected with the noise power supply, the second end of the variable capacitor is connected with the first end of the bias capacitor, and the second end of the bias capacitor is grounded; ramp voltage reference signal the buffer transistor and the bias transistor are connected in series between the noise power supply and ground, the gate of the buffer transistor receives a ramp voltage reference signal, and the gate of the bias transistor is connected to a bias voltage node and to a first end of the bias capacitor; wherein the second power supply noise signal is made to have the same amplitude as the first power supply noise signal by adjusting the value of the variable capacitor to cancel the power supply noise in the pixel circuit. Therefore, the utility model discloses a noise in the comparator introduction comparison signal production circuit makes power noise appear as the common mode noise of comparator to restrain the power noise among the pixel circuit, can effectual anti power noise interference, reduce image noise and improve the quality of image.
Drawings
Fig. 1 shows a block diagram of a power supply noise suppression circuit according to an embodiment of the present invention.
Fig. 2 shows a schematic diagram of a specific structure of a power noise suppression circuit according to an embodiment of the present invention.
Fig. 3 is a schematic diagram illustrating a specific structure of a power noise suppression circuit according to another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be described in detail and completely with reference to the accompanying drawings, and obviously, the described embodiments are some embodiments of the present invention, not all embodiments, and are only used for explaining the present invention, and are not used for limiting the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention. Reference throughout this patent specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention.
First, the present invention is conceived to solve the line noise of the image sensor, which is caused by the noise of the pixel power line in the pixel unit and the noise coupled from the pixel control signal line related to the power supply, by transmitting the power supply noise coupled in the pixel unit to one input terminal of the comparator or the amplifier through the source follower (the source follower transistor and the current source), and simultaneously introducing the power supply noise having the same amplitude to the other input terminal of the comparator or the amplifier, so that the power supply noise of the pixel unit becomes the common mode noise of the comparator, thereby suppressing the power supply noise of the pixel unit, making the output of the comparator less affected by the power supply noise, and achieving the purpose of reducing the image noise and improving the quality of the image.
Specifically, referring to fig. 1, fig. 1 is a block diagram illustrating a power noise suppression circuit according to an embodiment of the present invention. As shown in fig. 1, the power supply noise suppressing circuit includes a pixel circuit 11, a comparison signal generating circuit 12, and a comparator 13, the pixel circuit 11 outputs an image signal superimposed with a first power supply noise signal of a noise power supply vnoise to a first input terminal of the comparator 13, the comparison signal generating circuit 12 outputs a comparison signal superimposed with a second power supply noise signal of the noise power supply vnoise to a second input terminal of the comparator 13, and the second power supply noise signal has the same amplitude as the first power supply noise signal to cancel power supply noise in the pixel circuit. The comparison signal generating circuit 12 includes a capacitance adjusting module, a buffer transistor, and a bias transistor, where the buffer transistor and the bias transistor are connected in series between the noise power supply vnoise and ground, a gate of the buffer transistor receives a voltage reference signal, and the capacitance adjusting module adjusts a capacitance to make the amplitude of the second power supply noise signal be the same as that of the first power supply noise signal, so as to cancel the power supply noise in the pixel circuit.
Referring to fig. 2 in combination, fig. 2 is a schematic diagram illustrating a specific structure of a power noise suppression circuit according to an embodiment of the present invention. As shown in fig. 2, the pixel circuit 11 includes a first capacitor Cp connected between the drain and gate of the source follower transistor Msf and a second capacitor Cfd connected between the gate of the source follower transistor Msf and ground, the first capacitor Cp being a total coupling capacitance between the pixel power supply line, the pixel control signal line related to the power supply, and the floating diffusion node, and the second capacitor Cfd being all parasitic capacitances on the floating diffusion node minus the first capacitor Cp.
The comparison signal generation circuit 12 in the power supply noise suppression circuit includes a capacitance adjustment module, a first NMOS transistor Mbuf (buffer transistor), and a second NMOS transistor Mbias (bias transistor), the capacitance adjustment module including a variable capacitor Cc and a bias capacitor Cbias; the first end of the variable capacitor Cc is connected with a noise power supply vnoise, the second end of the variable capacitor Cc is connected with the first end of the bias capacitor Cbias, and the second end of the bias capacitor Cbias is grounded; the drain electrode of the first NMOS tube Mbuf is connected to the noise power supply vnoise, the gate electrode of the first NMOS tube Mbuf is connected to the ramp voltage reference signal node vref, and the source electrode of the first NMOS tube Mbuf is connected to the second input end of the comparator 13; the drain of the second NMOS transistor Mbias is connected to the second input of the comparator 13, the gate of the second NMOS transistor Mbias is connected to the bias voltage node vbias and to the first terminal of the bias capacitor Cbias, and the source of the second NMOS transistor Mbias is grounded.
Specifically, the pixel circuit may have a 3T, 4T, 5T or other structure, and in any structure, the power supply voltage in the pixel circuit may generate power supply noise, which affects the signal-to-noise ratio of the image. A common pixel circuit of 4T structure includes a photodiode, a transfer transistor, a reset transistor, a source follower transistor, a current source, and a row select transistor, the photodiode is connected to a source of the transfer transistor, drains of the reset transistor and the source follower transistor are commonly connected to a noise power source, a drain of the transfer transistor, a source of the reset transistor, and a gate of the source follower transistor are connected to a floating diffusion node, a source of the source follower transistor is connected to a drain of the row select transistor, and a source of the row select transistor is grounded through a current source. As shown in fig. 2, the pixel unit includes a first capacitor Cp connected between a noise power supply vnoise and a floating diffusion node FD (the voltage of FD is represented as vfd in fig. 2), and a second capacitor Cfd connected between the floating diffusion node FD (the voltage of FD is represented as vfd in fig. 2) and ground, the first capacitor Cp being a total coupling capacitance between a pixel power supply line, a pixel control signal line related to the power supply, and the floating diffusion node FD, and the second capacitor Cfd being a total parasitic capacitance on the floating diffusion node FD minus the first capacitor Cp.
During operation of the image sensor, the first capacitor Cp couples the power noise of the noise power supply vnoise to the floating diffusion node FD and outputs the power noise to the first input terminal of the comparator 13 through the source follower transistor Msf, i.e., the source of the source follower transistor Msf is connected to the node visg, and the first input terminal of the comparator 13 is connected to the node vsig. The first power supply noise signal of the noise power supply vnoise in the pixel circuit 11 is superimposed on the image signal input to the first input terminal of the comparator 13. Then, the second power noise signal of the noise power supply vnoise in the comparison signal generation circuit 12 is superimposed on the comparison signal input to the second input terminal of the comparator 13 to cancel the noises each other, thereby eliminating the power noise of the noise power supply vnoise in the pixel circuit 11. In the comparison signal generating circuit 12, the bias voltage node vbias provides a bias voltage to the second NMOS transistor Mbias to generate a bias current, which can also be understood as providing an operating voltage to the second NMOS transistor Mbias, and the first NMOS transistor Mbuf is used to suppress the influence of the reverse noise at the comparator end on the ramp voltage reference signal vref and provide a gain.
Specifically, in the present embodiment, the image signal on which the first power supply noise signal is superimposed is:
the comparison signal on which the second power supply noise signal is superimposed is:
wherein v isnoiseIs a noisy supply voltage, CpIs a first capacitor, CfdIs a second capacitance, CbiasIs the total capacitance of the bias voltage node, MbufIs a buffer transistor, MbiasIs a bias transistor, W and L are the width and length of the MOS transistor, gmbsfIs a small signal body transconductance characterizing a source follower transistor, which is related to the voltage difference between a body terminal and a source terminal, when the body terminal and the source terminal are connected together, gmbsfEqual to 0, at which time the capacitance adjustment, gm, can be made more efficientsf、gmbuf、gmbiasTransconductance of a source follower transistor, a buffer transistor and a bias transistor, respectively, by adjusting CcMake the difference value
Minimization for noise suppressionAnd (5) preparing.
It is worth mentioning that in case it is optimal that the second power supply noise signal has an amplitude equal to the amplitude of the first power supply noise signal, the difference in amplitude between the two noise signals can be minimized by adjusting the variable capacitor Cc.
In one embodiment, the first input terminal of the comparator 13 is an inverting input terminal, and the second input terminal of the comparator 13 is a non-inverting input terminal.
In one embodiment, the bias voltage node vbias is connected to a current mirror circuit to provide a bias voltage.
In one embodiment, the variable capacitor Cc comprises a variable sized capacitance.
Specifically, the variable capacitor Cc includes a variable-sized capacitance, and the image sensor may control the magnitude of the second noise signal by adjusting the size of the variable capacitance.
In one embodiment, the variable capacitor Cc comprises a plurality of constant capacitors connected in parallel, and each branch is provided with a switch to control the conduction of each constant capacitor.
Specifically, the variable capacitor Cc may be implemented by a plurality of constant capacitances connected in parallel and a plurality of corresponding switches, and the magnitude of the second noise signal is controlled by changing the capacitance value by controlling on/off of each switch to adjust the size of the variable capacitance.
In one embodiment, the bias capacitance Cbias is a variable capacitor.
To sum up, the embodiment of the present invention provides a power noise suppression circuit, which is provided with a pixel circuit, a comparison signal generation circuit and a comparator, wherein the pixel circuit outputs an image signal of a first power noise signal superimposed with a noise power source to a first input terminal of the comparator, the comparison signal generation circuit outputs a comparison signal of a second power noise signal superimposed with the noise power source to a second input terminal of the comparator, and the second power noise signal has the same amplitude as the first power noise signal to offset the power noise in the pixel circuit; the comparison signal generating circuit comprises a capacitance adjusting module, a first NMOS (N-channel metal oxide semiconductor) tube and a second NMOS tube, wherein the capacitance adjusting module comprises a variable capacitor and a bias capacitor; the first end of the variable capacitor is connected with the noise power supply, the second end of the variable capacitor is connected with the first end of the bias capacitor, and the second end of the bias capacitor is grounded; the drain electrode of the first NMOS tube is connected with a noise power supply, the grid electrode of the first NMOS tube is connected to a ramp voltage reference signal node, and the source electrode of the first NMOS tube is connected with the second input end of the comparator; the drain electrode of the second NMOS tube is connected with the second input end of the comparator, the grid electrode of the second NMOS tube is connected with the bias voltage node and is connected with the first end of the bias capacitor, and the source electrode of the second NMOS tube is grounded. The utility model discloses a noise among the comparator introduction comparison signal generating circuit makes power noise appear as the common mode noise of comparator to restrain the power noise among the pixel circuit, can effectual anti power noise interference, reduce image noise and improve the quality of image.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating a specific structure of a power noise suppression circuit according to another embodiment of the present invention. As shown in fig. 3, the power supply noise suppressing circuit includes a pixel circuit 11, a comparison signal generating circuit 12, and a comparator 13, the pixel circuit 11 outputs an image signal superimposed with a first power supply noise signal of a noise power supply vnoise to a first input terminal of the comparator 13, the comparison signal generating circuit 12 outputs a comparison signal superimposed with a second power supply noise signal of the noise power supply vnoise to a second input terminal of the comparator 13, the second power supply noise signal having the same amplitude as the first power supply noise signal to cancel power supply noise in the pixel circuit; the comparison signal generating circuit 12 includes a capacitance adjusting module, a first PMOS transistor Mbias, and a second PMOS transistor Mbuf, where the capacitance adjusting module includes a variable capacitor Cc and a bias capacitor Cbias; the first end of the variable capacitor Cc is connected with a noise power supply vnoise, the second end of the variable capacitor Cc is connected with the first end of the bias capacitor Cbias, and the second end of the bias capacitor Cbias is grounded; the source electrode of the first PMOS pipe Mbias is connected with a noise power supply vnoise, the grid electrode of the first PMOS pipe Mbias is connected with a bias voltage node vbias and is connected with the first end of a bias capacitor Cbias, and the drain electrode of the first PMOS pipe Mbias is connected with the second input end of the comparator 13; the source of the second PMOS transistor Mbuf is connected to the second input terminal of the comparator 13, the gate of the second PMOS transistor Mbuf is connected to the ramp voltage reference signal node vref, and the drain of the second PMOS transistor Mbuf is grounded.
Specifically, in the present embodiment,
the image signal on which the first power supply noise signal is superimposed is:
the comparison signal on which the second power supply noise signal is superimposed is:
wherein v isnoiseIs a noisy supply voltage, CpIs a first capacitor, CfdIs a second capacitance, CbiasIs the total capacitance of the bias voltage node, MbufIs a buffer transistor, MbiasIs a bias transistor, W and L are the width and length of the MOS transistor, gmbsfIs a small signal body transconductance characterizing a source follower transistor, which is related to the voltage difference between a body terminal and a source terminal, when the body terminal and the source terminal are connected together, gmbsfEqual to 0, at which time the capacitance adjustment, gm, can be made more efficientsf、gmbuf、gmbiasTransconductance of a source follower transistor, a buffer transistor and a bias transistor, respectively, by adjusting CcMake the difference value
Minimized for noise suppression.
It is worth mentioning that in case it is optimal that the second power supply noise signal has an amplitude equal to the amplitude of the first power supply noise signal, the difference in amplitude between the two noise signals can be minimized by adjusting the variable capacitor.
In one embodiment, the first input terminal of the comparator 13 is an inverting input terminal, and the second input terminal of the comparator 13 is a non-inverting input terminal.
In one embodiment, the bias voltage node vbias is connected to a current mirror circuit to provide a bias voltage.
In one embodiment, the variable capacitor Cc comprises a variable sized capacitance.
Specifically, the variable capacitor Cc includes a variable-sized capacitance, and the image sensor may control the magnitude of the second noise signal by adjusting the size of the variable capacitance.
In one embodiment, the variable capacitor Cc comprises a plurality of constant capacitors connected in parallel, and each branch is provided with a switch to control the conduction of each constant capacitor.
Specifically, the variable capacitor Cc may be implemented by a plurality of constant capacitances connected in parallel and a plurality of corresponding switches, and the magnitude of the second noise signal is controlled by changing the capacitance value by controlling on/off of each switch to adjust the size of the variable capacitance.
In one embodiment, the bias capacitance Cbias is a variable capacitor.
To sum up, the embodiment of the present invention provides a power noise suppression circuit, which is provided with a pixel circuit, a comparison signal generation circuit and a comparator, wherein the pixel circuit outputs an image signal of a first power noise signal superimposed with a noise power source to a first input terminal of the comparator, the comparison signal generation circuit outputs a comparison signal of a second power noise signal superimposed with the noise power source to a second input terminal of the comparator, and the second power noise signal has the same amplitude as the first power noise signal to offset the power noise in the pixel circuit; the comparison signal generation circuit comprises a capacitance adjusting module, a first PMOS (P-channel metal oxide semiconductor) tube and a second PMOS tube, wherein the capacitance adjusting module comprises a variable capacitor and a bias capacitor; a first end of the variable capacitor is connected with the noise power supply, a second end of the variable capacitor is connected with a first end of the bias capacitor, and a second end of the bias capacitor is grounded; the source electrode of the first PMOS tube is connected with the noise power supply, the grid electrode of the first PMOS tube is connected to a bias voltage node and is connected with the first end of the bias capacitor, and the drain of the first PMOS tube is connected with the second input end of the comparator; the source electrode of the second PMOS tube is connected with the second input end of the comparator, the grid electrode of the second PMOS tube is connected to the ramp voltage reference signal node, and the drain electrode of the second PMOS tube is grounded. The utility model discloses a noise among the comparator introduction comparison signal generating circuit makes power noise appear as the common mode noise of comparator to restrain the power noise among the pixel circuit, can effectual anti power noise interference, reduce image noise and improve the quality of image.
The preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the details of the above embodiments, and the technical concept of the present invention can be within the scope of the present invention, and can be modified to various simple variants, and these simple variants all belong to the protection scope of the present invention. The various features described in the foregoing detailed description may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the present invention does not separately describe various possible combinations.
Claims (11)
1. A power supply noise suppression circuit is characterized by comprising a pixel circuit, a comparison signal generation circuit and a comparator;
the pixel circuit outputs an image signal superimposed with a first power supply noise signal of a noise power supply to a first input terminal of the comparator, the comparison signal generation circuit outputs a comparison signal superimposed with a second power supply noise signal of the noise power supply to a second input terminal of the comparator, and the second power supply noise signal has the same amplitude as the first power supply noise signal so as to cancel power supply noise in the pixel circuit;
the comparison signal generation circuit comprises a capacitance adjusting module, a buffer transistor and a bias transistor, wherein the capacitance adjusting module comprises a variable capacitor and a bias capacitor;
a first end of the variable capacitor is connected with the noise power supply, a second end of the variable capacitor is connected with a first end of the bias capacitor, and a second end of the bias capacitor is grounded;
the buffer transistor and the bias transistor are connected in series between the noise power supply and the ground, the grid electrode of the buffer transistor receives a voltage reference signal, and the grid electrode of the bias transistor is connected to a bias voltage node and connected with a first end of the bias capacitor;
wherein the second power supply noise signal is made to have the same amplitude as the first power supply noise signal by adjusting the value of the variable capacitor to cancel the power supply noise in the pixel circuit.
2. The power supply noise suppression circuit according to claim 1, wherein the buffer transistor is a first NMOS transistor, and the bias transistor is a second NMOS transistor; the drain electrode of the first NMOS tube is connected with the noise power supply, the grid electrode of the first NMOS tube is connected to a voltage reference signal node, the voltage reference signal is a ramp voltage reference signal, and the source electrode of the first NMOS tube is connected with the second input end of the comparator; the drain electrode of the second NMOS tube is connected with the second input end of the comparator, the grid electrode of the second NMOS tube is connected with the bias voltage node and is connected with the first end of the bias capacitor, and the source electrode of the second NMOS tube is grounded.
3. The power supply noise suppression circuit according to claim 1, wherein the bias transistor is a first PMOS transistor, and the buffer transistor is a second PMOS transistor; the source electrode of the first PMOS tube is connected with the noise power supply, the grid electrode of the first PMOS tube is connected to a bias voltage node and is connected with the first end of the bias capacitor, and the drain electrode of the first PMOS tube is connected with the second input end of the comparator; the source electrode of the second PMOS tube is connected with the second input end of the comparator, the grid electrode of the second PMOS tube is connected to the voltage reference signal node, the voltage reference signal is a ramp voltage reference signal, and the drain electrode of the second PMOS tube is grounded.
4. The power supply noise suppression circuit of claim 1, wherein the bias voltage node is coupled to a current mirror circuit to provide a bias voltage.
5. The power supply noise suppression circuit of claim 1, wherein the variable capacitor comprises a variable sized capacitor.
6. The power supply noise suppression circuit according to claim 1, wherein the variable capacitor comprises a plurality of constant capacitances connected in parallel, and each branch is provided with a switch to control conduction of each constant capacitance.
7. The power supply noise suppression circuit according to claim 1, wherein the first input terminal of the comparator is an inverting input terminal, and the second input terminal of the comparator is a non-inverting input terminal.
8. The power supply noise suppression circuit according to claim 1, wherein the bias capacitance is a variable capacitor.
9. The power supply noise suppression circuit of claim 1, wherein the pixel circuit comprises a first capacitance connected between a drain and a gate of a source follower transistor and a second capacitance connected between the gate of the source follower transistor and ground, the first capacitance being a total coupling capacitance between a pixel power supply line, a power supply related pixel control signal line, and a floating diffusion node, the second capacitance being all parasitic capacitance on the floating diffusion node minus the first capacitance.
10. The power supply noise suppressing circuit according to claim 9, wherein the image signal on which the first power supply noise signal is superimposed is:
the comparison signal on which the second power supply noise signal is superimposed is:
wherein v isnoiseIs a noisy supply voltage, CpIs a first capacitor, CfdIs a second capacitance, CbiasIs the total capacitance of the bias voltage node, MbufIs a buffer transistor, MbiasIs a bias transistor, W and L are the width and length of the MOS transistor, gmbsfIs a small signal body transconductance, gm, characterizing a source follower transistorsf、gmbuf、gmbiasTransconductance of a source follower transistor, a buffer transistor and a bias transistor, respectively, by adjusting CcMake the difference value
Minimized for noise suppression.
11. An image sensor comprising the power supply noise suppressing circuit according to any one of claims 1 to 10.
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