JPH11143568A - Clock controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To respective independently control the supply operation of a clock signal in a clock generation circuit which are arranged distributedly in plural units that constitute an electronic equipment. SOLUTION: This clock controller is provided on an electronic device that consists of plural units 103 which respectively have at least one clock generating means 101 and at least one signal processing means 102 that operates in accordance with the supply of a clock signal that is obtained by the means 101. In such cases, it is provided with a stopping means 111 which stops the supply operation of the clock signal by a corresponding clock generating means 101 in accordance with a stop instruction and a stop instructing means 112 which generates a stop instruction to a corresponding stopping means 111 sends it in accordance with a selection instruction to the effect that it selectively stops the supply operation of a clock signal by at least one of the clock generating means 101 that are respectively arranged in plural units 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a clock control device for controlling the operation of a clock generation circuit mounted on a motherboard, an interface board, or the like for preventing electromagnetic noise in a personal computer or the like. In recent years, the influence of electromagnetic noise radiated from a personal computer or the like on other electronic devices has become a serious problem, and accordingly, various standards (for example, VCCI) regarding electromagnetic noise have been established. . On the other hand, the speed and functionality of personal computers have increased remarkably. In addition to the standard boards and units, a wide variety of boards and units have been installed as options. Since the clock generation circuits provided in each of the above generate clock signals of various frequencies, countermeasures against electromagnetic noise of a personal computer have become a very complicated problem. In particular, when a plurality of clock generation circuits are provided on each board or unit mounted on a personal computer and a clock signal of a frequency corresponding to the specified operation mode is generated, it is difficult to identify the source of noise. is there. Therefore, there is a need for a technique for controlling the operation of a plurality of clock generation circuits to reliably determine the noise source.

[0002]

2. Description of the Related Art The applicant of the present invention has already applied for a clock control system disclosed in Japanese Patent Application Laid-Open No. 1-286008 as a technique for controlling the operation of a clock generation circuit having a plurality of oscillation elements. In this technique, when a motherboard or an interface board is provided with a plurality of clock generation circuits that generate clock signals of different frequencies, a switching signal selectively activates one of these clock generation circuits to operate. , Stop the operation of the other clock generation circuits.

For example, as shown in FIG. 6, two clock generation circuits 410a and 410 provided in a display device are provided.
10b includes stop circuits 411a and 411b, respectively, and is configured such that mutually exclusive logic switching signals are input to these stop circuits 411a and 411b in accordance with the selected screen display mode. As the stop circuits 411a and 411b, for example, in the corresponding clock generation circuits 410a and 410b, a configuration in which the driving power supply to the oscillation circuit is cut off to completely stop the generation of the clock signal can be considered.

When the clock generation circuit 410a is enabled by a switching signal corresponding to the designated screen display mode, the clock signal Sa generated by the clock generation circuit 410a causes the NAND gate 412 and the frequency dividing circuit 413 to operate. Processor 414, screen control circuit 415 and parallel / serial (P / S) converter 4
16 and is used for controlling an access operation to the screen memory 417.

In this case, the stop circuit 411b stops the clock signal Sb by the clock generation circuit 410b in response to the switching signal inverted by the inverter 418, so that this clock signal which becomes unnecessary in the currently selected screen display mode is used. Sb is not emitted as electromagnetic noise. As described above, by applying the technique of Japanese Patent Application Laid-Open No. 1-286008, an unnecessary clock signal may cause the ground line, the power supply line, and other adjacent signal lines to be viewed as a single device or board alone. It can be prevented from radiating or conducting as electromagnetic wave noise through.

On the other hand, in the case of the personal computer as a whole, it may not be enough to satisfy the standards for each unit or board. For example, when the clock signal of the display device or its harmonics and the clock signal of the optional board are close in frequency, the clock signal selected by each unit or board is replaced by the clock signal of the other unit or board. It may interfere with the operation.

For this reason, conventionally, the housing of a personal computer has been dismantled, and the output pins and power supply pins of the oscillating elements of the clock generation circuit of the board or unit of interest have been removed from the board by heating with a soldering iron. Stop the clock signal by a mechanical method such as cutting the pattern with a cutter, and then
The personal computer was assembled again and the power was turned on to check for the occurrence of electromagnetic interference.

[0008]

As described above, the technique disclosed in Japanese Patent Application Laid-Open No. 1-286008 is a technique for selectively generating a required clock signal in each unit or board. However, any one of a large number of clock generation circuits provided on various units and boards constituting the above cannot be selectively operated.

Further, since the switching signal is generated in accordance with the setting of the operation mode by software or the like, the clock of the CPU controlling the entire personal computer cannot be stopped. On the other hand, if the clock signal is cut off by hardware, any clock signal, including the CPU clock, can be stopped, but each time, the housing is disassembled and the integrated circuit pins are removed from the board. It is necessary to perform complicated operations such as removing and assembling, and a great deal of time and labor is required to identify the source of the electromagnetic wave interference.

[0010] The present invention provides a clock control device capable of independently controlling the operation of supplying a clock signal to a clock generation circuit distributed in a plurality of units constituting an electronic device such as a personal computer. The purpose is to provide.

[0011]

FIG. 1 is a block diagram showing the principle of the present invention.

The invention according to claim 1 has at least one
In a clock control device provided in an electronic apparatus including a plurality of units 103 each including one clock generation unit 101 and at least one signal processing unit 102 that operates in accordance with the supply of a clock signal obtained by the clock generation unit 101 A stopping means 111 for stopping a clock signal supply operation by a corresponding clock generating means 101 in response to a stop instruction;
3 in response to a selection instruction to selectively stop the clock signal supply operation by at least one of the clock generation units 101 arranged in each of the three units.
Instructing unit 11 to create and send a stop instruction to
2 is provided.

According to the first aspect of the present invention, in response to a stop instruction from the stop instruction means 112, each stop means 111 stops the supply of the clock signal to the signal processing means 102 by the corresponding clock generation means 101. It is possible to stop at least one clock generating means 101 distributed in the unit 103 by an arbitrary combination.

According to a second aspect of the present invention, in the clock control device of the first aspect, the stopping means 111 has a power switch 113 for cutting off the supply of the driving power to the corresponding clock generating means 101. It is characterized by. Since the power supply to the clock generation unit 101 is controlled by the power switch 113 provided in the stop unit 111, the stop unit 111 can be easily mounted on an actual printed circuit board. Further, it is possible to reliably stop the generation of the clock signal itself and evaluate the contribution of the generation of the clock signal itself in the electromagnetic noise measurement work.

According to a third aspect of the present invention, in the clock control device according to the first aspect, the stopping means 111 includes a transmission switch 114 for cutting a wiring for transmitting the clock signal generated by the corresponding clock generating means 101. It is characterized by having a configuration.

According to a third aspect of the present invention, the transmission switch 114 provided in the stop means 111 cuts the wiring pattern for transmitting the clock signal, so that the wiring for transmitting the clock signal in the electromagnetic noise measurement work. It is possible to evaluate the contribution of the pattern. According to a fourth aspect of the present invention, in the clock control device according to the third aspect,
The stopping means 111 corresponding to the clock generating means 101 for supplying a clock signal to the plurality of signal processing means 102 includes a plurality of transmission switches 114 for cutting the wiring for transmitting the clock signal to the plurality of signal processing means 102. The stop instructing means 112 is characterized in that information indicating that at least one of the plurality of wirings is cut is transmitted as a stop instruction to the stopping means 111.

According to a fourth aspect of the present invention, a plurality of signal processing means 1 are provided.
By providing the transmission switches 114 corresponding to the respective wiring patterns for supplying the clock signals to 02, the contribution of these wiring patterns can be individually evaluated in the electromagnetic noise measurement work. According to a fifth aspect of the present invention, in the clock control device according to the first aspect, the stop instruction means 11 is provided in response to the input of the reset signal.
2 is provided with a release unit 115 for instructing that all clock generation units 101 supply clock signals.

According to a fifth aspect of the present invention, in response to a reset signal when the electronic device is reset by hardware by the operation of the release means 115, all of the signals including the clock of the central processing unit for controlling the entire electronic device are controlled. The supply of the clock signal is resumed, and the electronic device can be operated in a normal state.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 2 shows an embodiment of an electronic apparatus to which the clock control device according to claim 1 is applied. In FIG. 2, m units 201 ₁ constituting an electronic device such as a personal computer are shown.
~ 201m Have at least one clock generation circuit 211, and in the entire personal computer system,
n clock generation circuits 211 _{1 to} 211 _n are provided.

These n clock generation circuits 211 ₁
The ～211 _n, as a unique identifier in the electronic device system, for example, a number (1 to n) is given, but also, the clock generation circuit 211 ₁ ~211 _n is
A stop circuit 2 corresponding to the stop means 111 described in claim 1.
12 _{1 to} 212 _n are provided.
Further, in the clock control unit 220 shown in FIG. 2, the stop signal generation unit 222 includes the stop instruction unit 1 described in claim 1.
12 in response to an instruction from the stop control unit 221 and the n clock generation circuits 211 ₁ described above.
To 211 _n as a stop instruction for each stop signal S1
To Sn, and the corresponding stop circuits 212 ₁ to 2 ₁
It has a configuration which controls the operation of the 12 _n.

The stop control unit 221 generates, for example, n-bit stop instruction information including bits corresponding to the _n clock generation circuits 211 _{1 to} 211 n described above, and generates the clock generation circuit 211 _i with the number _i. May be instructed to stop the clock generation operation by the corresponding clock generation circuit 211 by setting the bit corresponding to.

Further, as shown in FIG. 3, the stop signal generation unit 222 includes a register 224 comprising n latches 223.
And the outputs Q1 to Qn of the latches 223 _{1 to} 223 _n are supplied as they are to the corresponding stop circuits 212 _{1 to} 212 _n as stop signals S1 to Sn. In this case, by specifying the address of the above-mentioned register 224 and writing the above-mentioned stop instruction information, it is possible to transmit an instruction to the stop signal generation unit 222. The function of the stop control unit 221 may be realized by performing a process of creating and writing stop instruction information by a part.

For example, the write signal of the control bus and the determination result by the address determination unit 225 are input to the clock terminals of the latches 223 _{1 to} 223 _n via the AND gate 226, and the stop instruction information output to the data bus is input. At the falling edge of this clock signal.
It may be held in the ₁ to 223 _n. In response to this, the output stop signal S1~Sn from these latches 223 ₁ to 223 _n, is supplied to a corresponding stop circuit 212 ₁ -212 _n, respectively.

Here, the clock generation circuit 211 generally outputs a signal of a predetermined frequency generated by the oscillation element 213 via the clock driver 214, and a signal processing unit (not shown) corresponding to the signal processing means 102 It is configured to be supplied to. Therefore, for example, power is supplied to the oscillation element 213 via the stop circuit 212 ₁ having the switch 215 that is turned on / off in response to the stop signal as in the clock generation circuit 211 ₁ shown in FIG. With this configuration, the clock signal can be completely stopped according to the corresponding stop signal.

The switch 215 is equivalent to the power switch 113 described in claim 2, and is constituted by using an FET 216 and a diode 217 as shown in FIG. The switching operation may be controlled by inputting a signal. In addition,
In this embodiment, the power switch is turned off when the stop signals (S1 to Sn) are at logic "1", that is, at the high voltage state, and vice versa at logic "0".

On the other hand, the clock generation circuit 21 shown in FIG.
In the case of a configuration including a crystal oscillator 218 that does not itself need to supply power as the oscillation element 213 as in 1 _n , a clock is supplied via a stop circuit 212 _{n including} a similar switch 215. The power may be supplied to the driver 214.

As described above, by operating the switch 215 of the stop circuit 212 in response to the stop signal indicating the corresponding bit of the stop instruction information, the n clock generation circuits distributed in various units are provided. The operation of 211 can be managed collectively, and any clock signal including the clock signal of the CPU can be selectively stopped. In this case, by changing the stop instruction information described above, the combination of clock signals to be stopped can be freely changed, and work such as disassembly and reassembly of the housing is not required. The measurement work of the electromagnetic wave interference can be promptly performed, and the source of the electromagnetic wave noise can be quickly and reliably located.

However, when the CPU clock signal is stopped, a write signal indicating the write timing to the register 224 is not output. Therefore, in order to rewrite the contents of the register 224, the generation of the CPU clock signal is restarted. There is a need. For this purpose, for example, a reset signal of the electronic device is connected to the reset terminal of each
If the measurement of electromagnetic interference is to be continued after stopping the clock signal of U, once resetting the electronic device clears the contents of all the latches, cancels the stop instruction, and resets all clocks. After the generation circuit 211 is brought into the operating state, new stop instruction information may be written into the register 224 again.

As described above, by directly inputting the reset signal of the electronic apparatus main body to the latch 223, the fifth aspect of the present invention is described.
By realizing the function of the canceling means 115 described above, it is possible to collectively cancel the stop state set up to that time and restart the generation of all clock signals including the CPU clock signal. In this case, it is necessary to restart the electronic device in response to the stop of the clock signal of the CPU. However, the labor-saving effect of disassembling and reassembling the housing is sufficiently large. .

It is also convenient when the user wants to return the electronic device to the original state during the electromagnetic interference measurement. By the way, as shown in FIG. 3, when the configuration is such that the reset signals are input to the reset terminals of all the latches, when the number of latches increases, the amount of hardware increases due to the wiring for inputting the reset signals. turn into.

Next, another method for collectively canceling the stop instruction to the n clock generation circuits 211 will be described. FIG. 4 shows another example of the configuration of the clock control unit to which the invention of claim 5 is applied. The stop signal generator 23 shown in FIG.
1 indicates that the stop signal generation unit 222 shown in FIG.
32 and n AND gates 233 are added, and the output of the latch 232 and the output of the n latches 223 are respectively input to the n AND gates 233, and the logical product thereof is output as a stop signal. I have.

In this case, the stop control unit 221 creates stop instruction information in which the 1-bit clock stop mode is added to the n-bit stop instruction to each clock generation unit 211, and sets the clock stop mode to the above-described latch 232. And hold it. At this time, the stop control unit 221
In this case, the clock stop mode may be set to logic "1" to indicate that the n-bit stop instruction is valid.

In this case, a reset signal accompanying the restart of the personal computer is input to the reset terminal of the latch 232, and the clock stop mode is set to logic "0". The signal is set to logic “0”, and the stop instruction can be released collectively. As described above, by controlling the operation of the clock generation circuit, when the clock generation circuit itself is a source of electromagnetic noise, the cause can be specified.

On the other hand, a wiring pattern for distributing a clock signal from the clock generation circuit to each part in the unit may be a source of electromagnetic noise. Next, a method of controlling transmission of a clock signal by the above-described wiring pattern will be described. FIG. 5 shows a detailed configuration diagram of a clock generation circuit to which claim 4 is applied.

The clock generation circuit 211 shown in FIG.
The clock driver 241 shapes the output signal of the crystal oscillator 218 by the driver circuit 242, and
3, k signal processing units 244 ₁ to 244 in the unit.
244 _k . In this case, the transmission switch 1 described in claim 4 is provided inside the distribution circuit 243.
14, an AND gate 245 corresponding to each of the k signal processing units 244 described above is provided.
The logical product of the stop signal corresponding to the clock signal obtained through the inverter 42 and the signals SP1 to SPk _obtained by inverting the logic of the corresponding stop signal by the inverters 246 ₁ to 246 _{k is} output to the corresponding signal processor 2
A configuration may be employed in which the clock signal is output as a clock signal to 44.

In this embodiment, the stop signal (SP1
... SPk) are at logic “0” and the clock signal of AND gate 245 is stopped, and at logic “1” the opposite is true. As described above, by inputting the stop signal and the clock signal to the AND gate 245 and supplying the logical product of the stop signal and the clock signal to the corresponding signal processing unit 244 as a clock signal,
Realizing the function of the transmission switch 114 described in claim 3,
The influence of the wiring pattern for transmitting the clock signal on the electromagnetic wave noise can be examined.

In this case, m of the n stop signals S1 to Sn obtained by the stop signal generation unit 222 shown in FIG.
The present assignment to the m signal processing unit 244 ₁ ~244 _m described above, the corresponding stop signals SP1 to SPm, may be input to the corresponding AND gates 245 ₁ to 245 _m of the distribution circuit 243. This makes it possible to independently control the transmission / disconnection of the clock signal for each of the wiring patterns corresponding to the plurality of signal processing units. We can assist in identifying the source.

[0039]

As described above, according to the present invention, the supply operation of the clock signal by the clock generation means distributed in a plurality of units is managed collectively.
Since the supply operation of each clock signal can be controlled independently, complicated operations such as disassembly and reassembly of electronic devices are not required, and the source of electromagnetic wave noise can be quickly and reliably specified. .

Further, claim 2, claim 3, and claim 4
By applying the present invention, it is also possible to separate the electromagnetic wave noise caused by the generation of the clock signal itself and the transmission of the clock signal. Further, when the invention of claim 5 is applied, supply of all clock signals including the clock of the central processing unit that controls the entire electronic device is restarted,
The electronic device can be operated in a normal state, and the work of measuring electromagnetic interference can proceed smoothly. You.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a configuration diagram of an electronic apparatus to which the clock control device of the present invention is applied.

FIG. 3 is a detailed configuration diagram of a stop signal generation unit and a stop circuit.

FIG. 4 is a diagram showing another configuration example of the stop signal generation unit to which the invention of claim 5 is applied.

FIG. 5 is a detailed configuration diagram of a clock generation circuit to which the invention of claim 4 is applied.

FIG. 6 is a configuration diagram of a display device to which a conventional clock control device is applied.

[Explanation of symbols]

 101 clock generation means 102 signal processing means 103, 201 unit 111 stop means 112 stop instruction means 113 power switch 114 transmission switch 115 release means 211, 410 clock generation circuit 212, 411 stop circuit 213 oscillation element 214 clock driver 215 switch 216 FET 217 Diode 218 Crystal oscillator 220 Clock controller 221 Stop controller 222, 231 Stop signal generator 223, 232 Latch 224 Register 225 Address determiner 226, 233, 245 AND gate 241 Driver circuit 244 Signal processor 246, 418 Inverter 412 NAND gate 413 frequency dividing circuit 414 processor 415 screen control circuit 416 parallel / serial (p / s) conversion section 417 screen memory

Claims (5)

[Claims] 1. An electronic apparatus comprising: a plurality of units each including at least one clock generation unit and at least one signal processing unit that operates in accordance with the supply of a clock signal obtained by the clock generation unit. In the clock control device, a stop unit that stops a clock signal supply operation by the corresponding clock generation unit in response to a stop instruction; and a clock signal output by at least one of the clock generation units respectively arranged in the plurality of units. A clock control device comprising: a stop instruction unit that creates and sends a stop instruction to a corresponding stop unit in response to a selection instruction to selectively stop a supply operation. 2. The clock control device according to claim 1, wherein the stop means includes a power switch for cutting off the supply of drive power to the corresponding clock generation means. 3. The clock control device according to claim 1, wherein the stop means has a transmission switch for cutting a wiring for transmitting a clock signal generated by the corresponding clock generation means. Clock control device. 4. The clock control device according to claim 3, wherein the stopping unit corresponding to the clock generating unit that supplies the clock signal to the plurality of signal processing units transmits the clock signal to the plurality of signal processing units. The transmission unit includes a plurality of transmission switches for disconnecting each of the wirings, and the stop instruction unit transmits information indicating that at least one of the plurality of wirings is disconnected as a stop instruction to the stop unit. A clock control device characterized by the above-mentioned. 5. The clock control device according to claim 1, wherein:
A clock control device comprising a release unit for instructing all clock generation units to supply a clock signal.