CN104917421A - Self-powered CMOS piezoelectric vibration energy harvester - Google Patents

Abstract

The invention discloses a self-powered CMOS piezoelectric vibration energy harvester. The self-powered CMOS piezoelectric vibration energy harvester is characterized in that the self-powered CMOS piezoelectric vibration energy harvester includes a CMOS piezoelectric synchronous charge extraction and collection interface circuit and a follow current energy storage circuit; the CMOS piezoelectric synchronous charge extraction and collection interface circuit is encapsulated in the form of an integrated circuit form; the CMOS piezoelectric synchronous charge extraction and collection interface circuit is provided with a first detection circuit output control interface, a second detection circuit output control interface, a first piezoelectric element connection interface, a second piezoelectric element connection interface, a first capacitance detection interface, a second capacitance detection interface, an external-connection inductance interface and a grounding port; the CMOS piezoelectric synchronous charge extraction and collection interface circuit includes a positive extremum detection module, a negative extremum detection module, a positive and negative extremum interlock switch, a positive and negative direction vibration automatic switching switch and a dynamic substrate level selection module. The self-powered CMOS piezoelectric vibration energy harvester has the advantages of easiness in integration, small circuit size, low power consumption and high energy extraction efficiency; and a self-powered design is adopted, so that the self-powered CMOS piezoelectric vibration energy harvester further has the advantage of no need for an external power source.

Description

A self-powered CMOS piezoelectric vibration energy harvester

technical field

The invention relates to the technical field of integrated circuits, in particular to a self-powered CMOS piezoelectric vibration energy collector.

Background technique

Vibration energy exists in almost any environment, such as water, air flow in nature, vibration of industrial machines, vibration during operation of vehicles, human movement, even breathing, heartbeat, etc. Piezoelectric vibration energy harvesters use the positive piezoelectric effect of piezoelectric materials to convert vibration energy in the environment into electrical energy. Piezoelectric vibration energy harvesters have the advantages of high energy density, simple structure, long life, and easy integration, and are widely used in contemporary micro-power mobile and wearable electronic devices.

Due to the vibration, the output voltage of the piezoelectric element is alternating, and the power supply of common microelectronic devices requires a stable DC voltage. Therefore, an interface circuit needs to be designed between the piezoelectric element and the electrical equipment, and the simplest is a diode. Full-bridge rectification and a filter capacitor rectification filter standard energy harvesting circuit (SEH), however, due to the existence of capacitor Cp in the internal equivalent circuit of the piezoelectric element, the piezoelectric element must first charge the capacitor Cp, when the voltage of the capacitor Cp Only after the voltage of the filter capacitor at the rear end of the rectifier bridge plus the voltage drop of the two diodes can the capacitor at the rear end be charged, this circuit not only has low recovery efficiency, but also the recovered energy is affected by the voltage of the rear end capacitor and the size of the load. degree of influence.

Therefore, researchers have proposed a variety of nonlinear energy extraction circuits, such as synchronous switched inductor circuit (P-SSHI), series synchronous switched inductor circuit (S-SSHI), synchronous charge extraction circuit (SECE), and derivatives based on this The dual synchronous switch circuit (DSSH), the enhanced dual synchronous switch inductance recovery circuit (ESSH) and the optimized synchronous charge extraction circuit (OSECE) etc. have come out.

Synchronous switch inductor circuit (P-SSHI) and series synchronous switch inductor circuit (S-SSHI) recover power is still greatly affected by the back-end capacitor voltage and load impedance; synchronous charge extraction circuit (SECE), double synchronous switch circuit ( DSSH), Enhanced Dual Synchronous Switch Inductance Recovery Circuit (ESSH) and Optimized Synchronous Charge Extraction Circuit (OSECE) solve this problem. It is very advantageous, but the actual implementation is either too complicated, or its own circuit cannot complete the acquisition alone, and needs to be powered by an external power supply, or the circuit is large in size and difficult to integrate due to the need for more discrete components, so it is difficult to promote.

Contents of the invention

The technical problem to be solved by the present invention is to provide a self-powered CMOS piezoelectric vibration energy harvester with small circuit volume and low power consumption. The self-powered design does not require an external power supply, and can realize efficient extraction of piezoelectric energy charges .

The technical scheme adopted by the present invention to solve the above-mentioned technical problems is: a self-powered CMOS piezoelectric vibration energy harvester, including a CMOS piezoelectric synchronous charge extraction and acquisition interface circuit and a freewheeling energy storage circuit, and the CMOS piezoelectric synchronous charge The extraction and acquisition interface circuit is packaged in the form of an integrated circuit. The CMOS piezoelectric synchronous charge extraction and acquisition interface circuit is provided with a first detection circuit output control interface, a second detection circuit output control interface, a first piezoelectric element connection interface, and a second detection circuit output control interface. Two piezoelectric element connection interfaces, a first capacitance detection interface, a second capacitance detection interface, an external inductance interface and a ground port, the first piezoelectric element connection interface is used to connect with one end of the piezoelectric element, and the second piezoelectric element connection interface Two piezoelectric element connection interfaces are used to connect with the other end of the piezoelectric element. The freewheeling energy storage circuit includes a freewheeling diode, an inductor and an energy storage capacitor, and the external inductor interface is connected to the freewheeling diode respectively. The anode of the freewheeling diode is connected to one end of the inductance, the cathode of the freewheeling diode is connected to the positive end of the energy storage capacitor, and the positive end of the energy storage capacitor is used to provide voltage to external electrical equipment, The negative end of the energy storage capacitor, the other end of the inductance and the grounding port are all grounded, and the CMOS piezoelectric synchronous charge extraction and acquisition interface circuit includes a forward extreme value detection module, a reverse extreme value Detection module, positive and negative extreme value interlock switch, positive and negative direction vibration automatic switching switch and dynamic substrate level selection module, the positive and negative extreme value interlock switch includes a third NMOS transistor, a fourth NMOS transistor, a ninth NMOS tubes, tenth NMOS tubes, seventh PMOS tubes and eighth PMOS tubes, the automatic switching switch for positive and negative vibrations includes seventh NMOS tubes, eighth NMOS tubes, third PMOS tubes and fourth PMOS tubes, so The dynamic substrate level selection module includes a fifth NMOS transistor and a sixth NMOS transistor, and the drain of the third NMOS transistor is respectively connected to the first signal transmission terminal of the forward extreme value detection module, the The second signal transmission terminal of the reverse extreme value detection module, the gate of the seventh NMOS transistor, the gate of the fourth PMOS transistor, the source of the tenth NMOS transistor, the The drain of the eighth PMOS transistor, the connection interface of the second piezoelectric element and one end of the piezoelectric element are connected, and the gate of the third NMOS transistor is respectively connected to the positive extreme value detection module The third signal transmission terminal, the gate of the ninth NMOS transistor, the gate of the eighth PMOS transistor and the output control interface of the first detection circuit are connected, and the source of the third NMOS transistor The pole is connected to the drain of the third PMOS transistor, and the gate of the third PMOS transistor is respectively connected to the interface of the first piezoelectric element, the other end of the piezoelectric element, and the The source of the ninth NMOS transistor, the drain of the seventh PMOS transistor, the second signal transmission terminal of the forward extreme detection module, the drain of the fourth NMOS transistor, the reverse To the first signal transmission end of the extreme value detection module and the gate of the eighth NMOS transistor connected, the source of the third PMOS transistor is respectively connected to the gate of the fifth NMOS transistor, the ground port, the drain of the sixth NMOS transistor and the drain of the fourth PMOS transistor The source is connected, and the gate of the fourth NMOS transistor is respectively connected to the third signal transmission end of the reverse extreme value detection module, the output control interface of the second detection circuit, and the tenth NMOS transistor The gate of the gate is connected to the gate of the seventh PMOS transistor, the source of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor, and the source of the fifth NMOS transistor is respectively It is connected to the integrated circuit substrate where the CMOS piezoelectric synchronous charge extraction and acquisition interface circuit is located and the source of the sixth NMOS transistor, and the drain of the fifth NMOS transistor is respectively connected to the external inductance interface , the source of the seventh NMOS transistor, the gate of the sixth NMOS transistor and the source of the eighth NMOS transistor are connected, and the drain of the seventh NMOS transistor is respectively connected to the The drain of the ninth NMOS transistor is connected to the source of the seventh PMOS transistor, and the drain of the eighth NMOS transistor is connected to the source of the eighth PMOS transistor and the tenth NMOS transistor respectively. The drain is connected, the fourth signal transmission end of the forward extreme value detection circuit is connected to the first capacitance detection interface, the fourth signal transmission end of the reverse extreme value detection circuit is connected to the The second capacitance detection interface is connected to the substrate of the third NMOS transistor, the substrate of the fourth NMOS transistor, the substrate of the seventh NMOS transistor, and the substrate of the eighth NMOS transistor , The substrate of the ninth NMOS transistor and the substrate of the tenth NMOS transistor are both isolated from the integrated circuit substrate by using a deep N well process.

The forward extreme value detection module includes a first NMOS transistor, a first PMOS transistor, a fifth PMOS transistor, a first detection capacitor and a first pull-down resistor, and the reverse extreme value detection module includes a second NMOS transistor , a second PMOS transistor, a sixth PMOS transistor, a second detection capacitor and a second pull-down resistor, the source of the first NMOS transistor is connected to the source of the first PMOS transistor, the fifth PMOS transistor The grid of the tube, the drain of the third NMOS tube, the grid of the second NMOS tube and one end of the second detection capacitor are connected, and the grid of the first NMOS tube is connected to the grid of the first NMOS tube respectively. One end of the first detection capacitor, the connection interface of the first piezoelectric element, the source of the second NMOS transistor, the source of the second PMOS transistor and the sixth PMOS transistor The gate of the first NMOS transistor is connected to the drain of the first NMOS transistor respectively with the gate of the first PMOS transistor, the drain of the first PMOS transistor, the source of the fifth PMOS transistor, The other end of the first detection capacitor, the source of the second NMOS transistor and the first capacitance detection interface are connected, and the drain of the fifth PMOS transistor is respectively connected to the first detection The circuit output control interface is connected to one end of the first pull-down resistor, the other end of the first pull-down resistor is connected to the ground port, and the drain of the second NMOS transistor is respectively connected to the The gate of the second PMOS transistor, the drain of the second PMOS transistor, the source of the sixth PMOS transistor, the other end of the second detection capacitor and the second capacitance detection interface connected, the drain of the sixth PMOS transistor is respectively connected to the output control interface of the second detection circuit and one end of the second pull-down resistor, and the other end of the second pull-down resistor is connected to the second pull-down resistor The ground port is connected, and the substrate of the first NMOS transistor and the substrate of the second NMOS transistor are both isolated from the integrated circuit substrate by using a deep N well process. The third NMOS tube, the ninth NMOS tube and the eighth PMOS tube in the positive and negative extreme value interlock switch are one group, and the fourth NMOS tube, the tenth NMOS tube and the seventh PMOS tube are another group; After the detection module detects the positive extreme value, it outputs a high level to the output control interface of the first detection circuit, drives the third NMOS transistor and the ninth NMOS transistor to conduct, and the eighth PMOS transistor is turned off. At this time, because the second detection circuit outputs The control interface keeps low level under the action of the pull-down resistor, so the fourth NMOS transistor and the tenth NMOS transistor are turned off, and the seventh PMOS transistor is turned on. The transmission gate formed by the ninth NMOS transistor and the seventh PMOS transistor is simultaneously turned on, which solves the problem of voltage loss when the NMOS transistor transmits the second piezoelectric element connection interface at low voltage; when the reverse extreme value detection module detects the reverse After the extreme value, output a high level to the output control interface of the second detection circuit to drive the fourth NMOS transistor and the tenth NMOS transistor to be turned on, and the seventh PMOS transistor to be turned off. Under the action, it keeps low level all the time, so the third NMOS tube and the ninth NMOS tube are turned off, and the eighth PMOS tube is turned on; the transmission gate formed by the tenth NMOS tube and the eighth PMOS tube is turned on at the same time, which solves the problem of the NMOS tube The problem of voltage loss when transmitting the low voltage of the connection interface of the first piezoelectric element.

Compared with the prior art, the present invention has the advantages that all detection circuits and switch loop circuits of the overall circuit are implemented by CMOS technology, which is easy to integrate, has few peripheral components, reduces the circuit volume, and reduces the conduction voltage drop and conduction Resistance, which reduces its own power consumption; adopts self-powered design without external power supply, can automatically detect the state of the piezoelectric element and control the on-off of the combination switch to extract energy, and provide power to external electrical equipment; use NMOS deep N well The technology isolates the NMOS tube from the external substrate, and can carry out independent logic control relatively freely. It can automatically detect the state of the piezoelectric element and control the on-off of the combined switch to extract energy, further reducing power consumption; automatic switching by positive and negative vibrations The parasitic diode in the switch maintains the original on and off state, and reversely charges part of the energy in the inductor back to the internal detection capacitor as the basic charge for the next extraction. Since the resonance frequency is much higher than the external oscillation frequency, the internal The capacitor quickly reverses the accumulation of charges, thereby quickly completing the state switching of the combined switch, and entering the energy accumulation and extraction process of the other half of the vibration cycle, increasing the time and level of charge accumulation, thus improving the efficiency of energy extraction; dynamic lining The bottom level selection module always selects the interface with the lowest level of the external inductor interface and the grounding port to be short-circuited with the integrated circuit substrate, so as to prevent the substrate of the NMOS transistor surrounded by the deep N well in the circuit and the integrated circuit substrate from conducting. It cannot work normally according to the potential difference between the source and gate of the NMOS transistor surrounded by the deep N well in the circuit alone.

Description of drawings

Fig. 1 is the schematic diagram of circuit structure of the present invention;

Fig. 2 is an external test circuit diagram of the present invention.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

A self-powered CMOS piezoelectric vibration energy harvester, including a CMOS piezoelectric synchronous charge extraction acquisition interface circuit and a freewheeling energy storage circuit, the CMOS piezoelectric synchronous charge extraction acquisition interface circuit is packaged in the form of an integrated circuit, and the CMOS piezoelectric synchronous charge extraction The acquisition interface circuit is provided with the output control interface CON1 of the first detection circuit, the output control interface CON2 of the second detection circuit, the first piezoelectric element connection interface PZT1, the second piezoelectric element connection interface PZT2, the first capacitance detection interface CDET1, the second piezoelectric element connection interface Two capacitance detection interface CDET2, external inductance interface LPIN and grounding port GND, the first piezoelectric element connection interface PZT1 is used to connect with one end of the piezoelectric element PZT, and the second piezoelectric element connection interface PZT2 is used to connect with the piezoelectric element PZT The other end is connected. The freewheeling energy storage circuit includes a freewheeling diode D1, an inductor L and an energy storage capacitor Crect. The external inductor interface LPIN is respectively connected to the positive pole of the freewheeling diode D1 and one end of the inductor L. The negative pole of the freewheeling diode D1 is connected to the storage capacitor. The positive end of the energy storage capacitor Crect is connected, the positive end of the energy storage capacitor Crect is used to provide voltage V _DC to the external electrical equipment, the negative end of the energy storage capacitor Crect, the other end of the inductor L and the grounding port GND are all grounded, and the CMOS piezoelectric The interface circuit for synchronous charge extraction and acquisition includes a forward extremum detection module, a reverse extremum detection module, a forward and reverse extremum interlock switch, a forward and reverse vibration automatic switching switch, and a dynamic substrate level selection module. The lock switch includes the third NMOS transistor Mn3, the fourth NMOS transistor Mn4, the ninth NMOS transistor Mn9, the tenth NMOS transistor Mn10, the seventh PMOS transistor Mp7 and the eighth PMOS transistor Mp8, and the forward and reverse direction vibration automatic switching switch includes the seventh NMOS transistor The transistor Mn7, the eighth NMOS transistor Mn8, the third PMOS transistor Mp3 and the fourth PMOS transistor Mp4, the dynamic substrate level selection module includes the fifth NMOS transistor Mn5 and the sixth NMOS transistor Mn6, and the drains of the third NMOS transistor Mn3 are respectively The first signal transmission end of the forward extreme value detection module, the second signal transmission end of the reverse extreme value detection module, the gate of the seventh NMOS transistor Mn7, the gate of the fourth PMOS transistor Mp4, the tenth NMOS transistor Mn10 The source of the eighth PMOS transistor Mp8, the second piezoelectric element connection interface PZT2 and one end of the piezoelectric element PZT are connected, and the gate of the third NMOS transistor Mn3 is respectively connected to the third signal of the forward extreme value detection module. The transmission end, the gate of the ninth NMOS transistor Mn9, the gate of the eighth PMOS transistor Mp8 are connected to the output control interface CON1 of the first detection circuit, the source of the third NMOS transistor Mn3 is connected to the drain of the third PMOS transistor Mp3, The gate of the third PMOS transistor Mp3 is respectively connected to the interface PZT1 of the first piezoelectric element, the other end of the piezoelectric element PZT, the source of the ninth NMOS transistor Mn9, the drain of the seventh PMOS transistor Mp7, and the forward extreme value detection The second signal transmission end of the module, the fourth NMO The drain of the S transistor Mn4 is connected to the first signal transmission terminal of the reverse extreme value detection module and the gate of the eighth NMOS transistor Mn8, and the source of the third PMOS transistor Mp3 is respectively connected to the gate of the fifth NMOS transistor Mn5 and grounded. The port GND, the drain of the sixth NMOS transistor Mn6 and the source of the fourth PMOS transistor Mp4 are connected, and the gate of the fourth NMOS transistor Mn4 is respectively connected to the third signal transmission end of the reverse extreme value detection module and the output of the second detection circuit. The control interface CON2, the gate of the tenth NMOS transistor Mn10 and the gate of the seventh PMOS transistor Mp7 are connected, the source of the fourth NMOS transistor Mn4 is connected with the drain of the fourth PMOS transistor Mp4, and the source of the fifth NMOS transistor Mn5 They are respectively connected to the integrated circuit substrate Sub where the CMOS piezoelectric synchronous charge extraction and acquisition interface circuit is located and the source of the sixth NMOS transistor Mn6, and the drain of the fifth NMOS transistor Mn5 is connected to the external inductance interface LPIN and the seventh NMOS transistor Mn7 respectively. The source, the gate of the sixth NMOS transistor Mn6 and the source of the eighth NMOS transistor Mn8 are connected, and the drain of the seventh NMOS transistor Mn7 is respectively connected to the drain of the ninth NMOS transistor Mn9 and the source of the seventh PMOS transistor Mp7 , the drain of the eighth NMOS transistor Mn8 is respectively connected to the source of the eighth PMOS transistor Mp8 and the drain of the tenth NMOS transistor Mn10, and the fourth signal transmission end of the forward extreme value detection circuit is connected to the first capacitance detection interface CDET1 , the fourth signal transmission end of the reverse extreme detection circuit is connected to the second capacitance detection interface CDET2, the substrate of the third NMOS transistor Mn3, the substrate of the fourth NMOS transistor Mn4, the substrate of the seventh NMOS transistor Mn7, the substrate of the seventh NMOS transistor Mn7, The substrates of the eighth NMOS transistor Mn8, the ninth NMOS transistor Mn9 and the tenth NMOS transistor Mn10 are all isolated from the integrated circuit substrate Sub by a deep N well process.

The forward extreme value detection module includes the first NMOS transistor Mn1, the first PMOS transistor Mp1, the fifth PMOS transistor Mp5, the first detection capacitor C1 and the first pull-down resistor Rdp1, and the reverse extreme value detection module includes the second NMOS transistor Mn2 , the second PMOS transistor Mp2, the sixth PMOS transistor Mp6, the second detection capacitor C2 and the second pull-down resistor Rdp2, the source of the first NMOS transistor Mn1 is respectively connected to the source of the first PMOS transistor Mp1, the source of the fifth PMOS transistor Mp5 The gate, the drain of the third NMOS transistor Mn3, the gate of the second NMOS transistor Mn2 and one end of the second detection capacitor C2 are connected, and the gate of the first NMOS transistor Mn1 is respectively connected to one end of the first detection capacitor C1, the first The piezoelectric element connection interface PZT1, the source of the second NMOS transistor Mn2, the source of the second PMOS transistor Mp2, and the gate of the sixth PMOS transistor Mp6 are connected, and the drain of the first NMOS transistor Mn1 is connected to the first PMOS transistor Mp1 respectively. The gate of the first PMOS transistor Mp1, the source of the fifth PMOS transistor Mp5, the other end of the first detection capacitor C1, the source of the second NMOS transistor Mn2 are connected to the first capacitance detection interface CDET1, and the fifth The drain of the PMOS transistor Mp5 is respectively connected to the output control interface CON1 of the first detection circuit and one end of the first pull-down resistor Rdp1, the other end of the first pull-down resistor Rdp1 is connected to the ground port GND, and the drain of the second NMOS transistor Mn2 respectively connected to the gate of the second PMOS transistor Mp2, the drain of the second PMOS transistor Mp2, the source of the sixth PMOS transistor Mp6, the other end of the second detection capacitor C2 and the second capacitance detection interface CDET2, the sixth PMOS transistor The drain of Mp6 is respectively connected to the second detection circuit output control interface CON2 and one end of the second pull-down resistor Rdp2, the other end of the second pull-down resistor Rdp2 is connected to the ground port GND, the substrate of the first NMOS transistor Mn1 and the second NMOS The substrate of the tube Mn2 is isolated from the integrated circuit substrate Sub by using a deep N-well process.

The detailed working principle of the above embodiment is as follows:

The second piezoelectric element connection interface PZT2 and the first piezoelectric element connection interface PZT1 are respectively connected to both ends of the piezoelectric element PZT, and the voltage Vpzt2 at the second piezoelectric element connection interface PZT2 is greater than that of the first piezoelectric element connection interface PZT1 During the half period of the positive vibration of the voltage Vpzt1, the working state of each part of the circuit changes as follows: In the positive extreme value detection module, due to the level of the gate of the first NMOS transistor Mn1 and the voltage of the first piezoelectric element connection interface PZT1 The level is the same, so the first NMOS transistor Mn1 is in the off state. Since there is a parasitic diode between the substrate of the first NMOS transistor Mn1 and the drain of the first NMOS transistor Mn1, when the voltage Vpzt2 of the second piezoelectric element connection interface PZT2 is higher than When the voltage Vpzt1 of the first piezoelectric element connection interface PZT1 is higher than a diode voltage drop VD, the parasitic diode is turned on, and the second piezoelectric element connection interface PZT2 charges the first detection capacitor C1 through the parasitic diode of the first NMOS transistor Mn1 , so that the level of the first capacitance detection interface CDET1 increases with the increase of Vpzt2, and its voltage VCDET1=Vpzt2-VD. When the piezoelectric element PZT vibrates to the positive extreme position, Vpzt2 reaches the maximum value. After passing the positive extreme position, Vpzt2 begins to drop, while VCDET1 remains unchanged. When Vpzt2 drops to one PMOS transistor lower than VCDET1 When the threshold voltage Vthp is turned on, Vpzt2=VCDET1-Vthp, the fifth PMOS transistor Mp5 is turned on, and the voltage VCDET1 is transmitted to the output control interface CON1 of the first detection circuit, which provides a turn-on signal for the positive and negative extreme value interlock switch of the next stage, Thus, the extraction of synchronous charges is completed, wherein the first PMOS transistor Mp1 uses its parasitic diode to extract the charges stored in the first detection capacitor C1 into the inductor. In this half cycle of positive vibration, since the level of the gate of the second NMOS transistor Mn2 is the same as the level of the second piezoelectric element connection interface PZT2, the second NMOS transistor Mn2 is in the conduction state, and the on-resistance is very low. Small, it can be equivalently considered that the second detection capacitor C2 is directly connected in parallel with the equivalent capacitance inside the piezoelectric element, and since there is no diode voltage drop, the energy in the second detection capacitor C2 can be extracted more completely.

In the reverse vibration half period when the voltage Vpzt1 of the first piezoelectric element connection interface PZT1 pin is greater than the voltage Vpzt2 of the second piezoelectric element connection interface PZT2, the working state of each part of the circuit changes as follows: due to the gate of the second NMOS transistor Mn2 The level is the same as the level of the second piezoelectric element connection interface PZT2, so the second NMOS transistor Mn2 is in the off state, because there is a parasitic diode between the substrate of the second NMOS transistor Mn2 and the drain of the second NMOS transistor Mn2, When the voltage Vpzt1 of the first piezoelectric element connection interface PZT1 is higher than the voltage Vpzt2 of the second piezoelectric element connection interface PZT2 by a diode drop VD, the parasitic diode is turned on, and the first piezoelectric element connection interface PZT1 passes through the second piezoelectric element connection interface PZT1. The parasitic diode of the NMOS transistor Mn2 charges the second detection capacitor C2, so that the level of the second capacitance detection interface CDET2 increases with the increase of Vpzt1, and its voltage VCDET2=Vpzt1-VD; when the piezoelectric element PZT vibrates to the opposite pole Vpzt1 reaches the maximum value position, when the piezoelectric element PZT vibrates past the reverse extreme position, Vpzt1 begins to drop, while VCDET2 remains unchanged, when Vpzt1 drops to a PMOS turn-on threshold voltage Vthp lower than VCDET2 At this time, Vpzt1=VCDET2-Vthp, the sixth PMOS transistor Mp6 is turned on, and the voltage VCDET2 is transmitted to the output control port of the second detection circuit to provide an open signal for the positive and negative interlock switch of the next stage, thereby completing the extraction of synchronous charges , wherein the second PMOS transistor Mp2 uses its parasitic diode to extract the charge stored in the second detection capacitor C2 to the inductance; The level of the piezoelectric element connection interface PZT1 is the same, so the first NMOS transistor Mn1 is in the on state, and the on-resistance is very small. It can be equivalently considered that the first detection capacitor C1 is directly connected in parallel with the internal equivalent capacitance of the piezoelectric element. There is no diode voltage drop, so the energy in the first detection capacitor C1 can be extracted more completely.

The third NMOS transistor Mn3, the ninth NMOS transistor Mn9 and the eighth PMOS transistor Mp8 in the positive and negative extreme value interlocking switch are one group, and the fourth NMOS transistor Mn4, the tenth NMOS transistor Mn10 and the seventh PMOS transistor Mp7 are another group ; When the positive extreme value detection module detects the positive extreme value, it outputs a high level to the output control interface CON1 of the first detection circuit to drive the third NMOS transistor Mn3 and the ninth NMOS transistor Mn9 to conduct, and the eighth PMOS transistor Mp8 is turned off, at this time, because the output control interface CON2 of the second detection circuit is kept low under the action of the pull-down resistor, the fourth NMOS transistor Mn4 and the tenth NMOS transistor Mn10 are turned off, and the seventh PMOS transistor Mp7 is turned on. The transmission gate formed by the ninth NMOS transistor Mn9 and the seventh PMOS transistor Mp7 is simultaneously turned on, which solves the problem of voltage loss when the NMOS transistor transmits the low voltage of the second piezoelectric element connection interface PZT2; when the reverse extreme value detection module After detecting the reverse extreme value, output a high level to the output control interface CON2 of the second detection circuit to drive the fourth NMOS transistor Mn4 and the tenth NMOS transistor Mn10 to be turned on, and the seventh PMOS transistor Mp7 to be turned off. The output control interface CON1 of the detection circuit keeps low level under the action of the pull-down resistor, so the third NMOS transistor Mn3 and the ninth NMOS transistor Mn9 are turned off, and the eighth PMOS transistor Mp8 is turned on. The transmission gate formed by the tenth NMOS transistor Mn10 and the eighth PMOS transistor Mp8 is turned on at the same time, which solves the problem of voltage loss when the NMOS transistor transmits the low voltage of the first piezoelectric element connection interface PZT1.

The third PMOS transistor Mp3 and the seventh NMOS transistor Mn7 in the positive and negative direction vibration automatic switching switch are one group, the fourth PMOS transistor Mp4 and the eighth NMOS transistor Mn8 are another group; the voltage at the connection interface PZT2 of the second piezoelectric element Vpzt2 is greater than the voltage Vpzt1 of the first piezoelectric element connection interface PZT1 in the positive vibration half cycle, when the voltage difference between the two ends is greater than the threshold voltage of the MOS transistor, the third PMOS transistor Mp3 and the seventh NMOS transistor Mn7 are turned on, and the fourth PMOS transistor Mp3 is turned on. The tube Mp4 and the eighth NMOS tube Mn8 are cut off; when the voltage Vpzt1 of the first piezoelectric element connection interface PZT1 of the piezoelectric element PZT is greater than the reverse vibration half cycle of the voltage Vpzt2 of the second piezoelectric element connection interface PZT2, when the two After the terminal voltage difference is greater than the threshold voltage of the MOS transistors, the fourth PMOS transistor Mp4 and the eighth NMOS transistor Mn8 are turned on, and the third PMOS transistor Mp3 and the seventh NMOS transistor Mn7 are turned off.

The extraction process of the piezoelectric vibration energy by the overall circuit is divided into two stages. In each stage, the potential at the two ends of the external inductance interface LPIN and the ground port GND changes. In the first stage, the internal voltage of the piezoelectric element PZT is equal to The effective capacitance and inductance L form LC resonance, the potential of the ground port GND is equal to the voltage of the equivalent capacitance inside the piezoelectric element PZT, so the level of the ground port GND is higher than the level of the external inductor interface LPIN, when the piezoelectric element PZT After the internal charge extraction of the internal equivalent capacitor is completed, it enters the second stage. Since the inductance L needs to maintain the original current, and the original circuit is disconnected, only induced electromotive force can be generated to carry out freewheeling through the freewheeling diode D1. At this time, the external The level of the inductance interface LPIN is higher than the level of the ground port GND; the function of the dynamic substrate level selection circuit is to always select the interface with the lowest level between the external inductance interface LPIN and the ground port GND to be short-circuited with the IC substrate Sub To prevent the substrate of the NMOS transistor surrounded by the deep N well in the circuit and the substrate Sub of the integrated circuit from being turned on, and unable to work normally based on the potential difference between the source and the gate alone.

After the LC resonance energy extraction is completed, the voltage difference between the first piezoelectric element connection interface PZT1 and the second piezoelectric element connection interface PZT2 has become zero, and the third PMOS transistor Mp3, the seventh NMOS transistor Mn7, and the fourth PMOS transistor Both Mp4 and the eighth NMOS transistor Mn8 have parasitic diodes, which can continue to maintain the original on and off states, so that the LC resonance can continue, and a part of the energy in the inductance L can be reversely charged back to the internal detection capacitor as the next step. The basic charge "seed" extracted at one time; because the resonance frequency is much higher than the external oscillation frequency, the internal capacitor quickly reverses the charge accumulation, thereby quickly completing the state switching of the combination switch, and entering the energy accumulation and extraction process of the other half of the vibration cycle , increasing the time and level height of charge accumulation, thus improving the efficiency of energy extraction.

Since the first pull-down resistor Rdp1 and the second pull-down resistor Rdp2 usually have relatively large resistance values, while the first detection capacitor C1 and the second detection capacitor C2 are both small on-chip capacitors, in practical applications, according to different piezoelectric elements Or the performance of the mechanism, you can refer to the external test circuit diagram shown in Figure 2 to connect an external resistor in parallel to the pull-down resistor to reduce the pull-down resistor value, or increase the capacitance value by connecting an external detection capacitor in parallel.

Claims (2)

1. a self-powered CMOS piezoelectric vibration energy collector, it is characterized in that comprising CMOS piezoelectricity synchronous charge-extraction acquisition interface circuit and afterflow accumulator, described CMOS piezoelectricity synchronous charge-extraction acquisition interface circuit adopts integrated circuit form encapsulation, described CMOS piezoelectricity synchronous charge-extraction acquisition interface circuit is provided with the first testing circuit and exports control interface, second testing circuit exports control interface, first piezoelectric element connecting interface, second piezoelectric element connecting interface, first capacitance detecting interface, second capacitance detecting interface, external inductive interface and grounding ports, the first described piezoelectric element connecting interface is used for being connected with one end of piezoelectric element, the second described piezoelectric element connecting interface is used for being connected with the other end of piezoelectric element, described afterflow accumulator comprises fly-wheel diode, inductance and storage capacitor, described external inductive interface is connected with the positive pole of described fly-wheel diode and one end of described inductance respectively, the negative pole of described fly-wheel diode is connected with the anode of described storage capacitor, the anode of described storage capacitor is used for providing voltage to external electric equipment, the negative terminal of described storage capacitor, the other end of described inductance and the equal ground connection of described grounding ports, described CMOS piezoelectricity synchronous charge-extraction acquisition interface circuit comprises forward extremum extracting module, reverse extreme value detection module, positive and negative extreme value interlock switch, both forward and reverse directions vibration automatic transfer switch and dynamic substrate lever selection module, described positive and negative extreme value interlock switch comprises the 3rd NMOS tube, 4th NMOS tube, 9th NMOS tube, tenth NMOS tube, 7th PMOS and the 8th PMOS, described both forward and reverse directions vibration automatic transfer switch comprises the 7th NMOS tube, 8th NMOS tube, 3rd PMOS and the 4th PMOS, described dynamic substrate lever selection module comprises the 5th NMOS tube and the 6th NMOS tube, the drain electrode of the 3rd described NMOS tube respectively with the first Signal transmissions end of described forward extremum extracting module, the secondary signal transmission ends of described reverse extreme value detection module, the grid of the 7th described NMOS tube, the grid of the 4th described PMOS, the source electrode of the tenth described NMOS tube, the drain electrode of the 8th described PMOS, one end of the second described piezoelectric element connecting interface and described piezoelectric element connects, the grid of the 3rd described NMOS tube respectively with the 3rd Signal transmissions end of described forward extremum extracting module, the grid of the 9th described NMOS tube, the grid of the 8th described PMOS and the first described testing circuit export control interface and connect, the source electrode of the 3rd described NMOS tube is connected with the drain electrode of the 3rd described PMOS, the grid of the 3rd described PMOS respectively with the first described piezoelectric element connecting interface, the other end of described piezoelectric element, the source electrode of the 9th described NMOS tube, the drain electrode of the 7th described PMOS, the secondary signal transmission ends of described forward extremum extracting module, the drain electrode of the 4th described NMOS tube, first Signal transmissions end of described reverse extreme value detection module and the grid of the 8th described NMOS tube connect, the source electrode of the 3rd described PMOS respectively with the grid of the 5th described NMOS tube, described grounding ports, the drain electrode of the 6th described NMOS tube and the source electrode of the 4th described PMOS connect, the grid of the 4th described NMOS tube respectively with the 3rd Signal transmissions end of described reverse extreme value detection module, the second described testing circuit exports control interface, the grid of the tenth described NMOS tube and the grid of the 7th described PMOS connect, the source electrode of the 4th described NMOS tube is connected with the drain electrode of the 4th described PMOS, the source electrode of the 5th described NMOS tube connects with the IC substrate at described CMOS piezoelectricity synchronous charge-extraction acquisition interface circuit place and the source electrode of the 6th described NMOS tube respectively, the drain electrode of the 5th described NMOS tube respectively with described external inductive interface, the source electrode of the 7th described NMOS tube, the grid of the 6th described NMOS tube and the source electrode of the 8th described NMOS tube connect, the drain electrode of the 7th described NMOS tube is connected with the drain electrode of the 9th described NMOS tube and the source electrode of the 7th described PMOS respectively, the drain electrode of the 8th described NMOS tube is connected with the source electrode of the 8th described PMOS and the drain electrode of the tenth described NMOS tube respectively, 4th Signal transmissions end of described forward extremum extracting circuit is connected with the first described capacitance detecting interface, 4th Signal transmissions end of described reverse extreme value testing circuit is connected with the second described capacitance detecting interface, the substrate of the 3rd described NMOS tube, the substrate of the 4th described NMOS tube, the substrate of the 7th described NMOS tube, the substrate of the 8th described NMOS tube, the substrate of the 9th described NMOS tube and the substrate of the tenth described NMOS tube all adopt dark N-well process and described IC substrate to isolate.

2. a kind of self-powered CMOS piezoelectric vibration energy collector according to claim 1, it is characterized in that described forward extremum extracting module comprises the first NMOS tube, first PMOS, 5th PMOS, first Detection capacitance and the first pull down resistor, described reverse extreme value detection module comprises the second NMOS tube, second PMOS, 6th PMOS, second Detection capacitance and the second pull down resistor, the source electrode of the first described NMOS tube respectively with the source electrode of the first described PMOS, the grid of the 5th described PMOS, the drain electrode of the 3rd described NMOS tube, the grid of the second described NMOS tube and one end of the second described Detection capacitance connect, the grid of the first described NMOS tube respectively with one end of the first described Detection capacitance, the first described piezoelectric element connecting interface, the source electrode of the second described NMOS tube, the source electrode of the second described PMOS and the grid of the 6th described PMOS connect, the drain electrode of the first described NMOS tube respectively with the grid of the first described PMOS, the drain electrode of the first described PMOS, the source electrode of the 5th described PMOS, the other end of the first described Detection capacitance, source electrode and the first described capacitance detecting interface of the second described NMOS tube connect, one end that the drain electrode of the 5th described PMOS exports control interface and the first described pull down resistor with the first described testing circuit is respectively connected, the other end of the first described pull down resistor is connected with described grounding ports, the drain electrode of the second described NMOS tube respectively with the grid of the second described PMOS, the drain electrode of the second described PMOS, the source electrode of the 6th described PMOS, the other end and the second described capacitance detecting interface of the second described Detection capacitance connect, one end that the drain electrode of the 6th described PMOS exports control interface and the second described pull down resistor with the second described testing circuit is respectively connected, the other end of the second described pull down resistor is connected with described grounding ports, the substrate of the first described NMOS tube and the substrate of the second described NMOS tube all adopt dark N-well process and described IC substrate to isolate.