CN104917421A - Self-powered CMOS piezoelectric vibration energy harvester - Google Patents
Self-powered CMOS piezoelectric vibration energy harvester Download PDFInfo
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- CN104917421A CN104917421A CN201510300530.2A CN201510300530A CN104917421A CN 104917421 A CN104917421 A CN 104917421A CN 201510300530 A CN201510300530 A CN 201510300530A CN 104917421 A CN104917421 A CN 104917421A
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Abstract
The invention discloses a self-powered CMOS piezoelectric vibration energy harvester. The self-powered CMOS piezoelectric vibration energy harvester is characterized in that the self-powered CMOS piezoelectric vibration energy harvester includes a CMOS piezoelectric synchronous charge extraction and collection interface circuit and a follow current energy storage circuit; the CMOS piezoelectric synchronous charge extraction and collection interface circuit is encapsulated in the form of an integrated circuit form; the CMOS piezoelectric synchronous charge extraction and collection interface circuit is provided with a first detection circuit output control interface, a second detection circuit output control interface, a first piezoelectric element connection interface, a second piezoelectric element connection interface, a first capacitance detection interface, a second capacitance detection interface, an external-connection inductance interface and a grounding port; the CMOS piezoelectric synchronous charge extraction and collection interface circuit includes a positive extremum detection module, a negative extremum detection module, a positive and negative extremum interlock switch, a positive and negative direction vibration automatic switching switch and a dynamic substrate level selection module. The self-powered CMOS piezoelectric vibration energy harvester has the advantages of easiness in integration, small circuit size, low power consumption and high energy extraction efficiency; and a self-powered design is adopted, so that the self-powered CMOS piezoelectric vibration energy harvester further has the advantage of no need for an external power source.
Description
Technical field
The present invention relates to technical field of integrated circuits, especially a kind of self-powered CMOS piezoelectric vibration energy collector.
Background technology
Vibrational energy is almost present in any environment, the vibration of the flowing of water in the Nature, air, industrial machine, the vibration when vehicles run, human motion, even breathing, heartbeat, etc.Piezoelectric type vibration energy collecting device utilizes the direct piezoelectric effect of piezoelectric, the vibrational energy in environment can be converted to electric energy.Piezoelectric vibration energy collector has the advantages such as energy density is high, structure is simple, the life-span is long, easy of integration and is widely used in contemporary Micro Energy Lose and moves and dress in electronic equipment.
Voltage piezoelectric element being exported due to vibration is alternation, and common small electronic equipment to power be need galvanic current pressure, so, design interface circuit is needed between piezoelectric element and power consumption equipment, it is the most simply the rectifying and wave-filtering standard energy Acquisition Circuit (SEH) of diode full-bridge rectification and a filter capacitor, but, due to the existence of electric capacity Cp in the inside equivalent electric circuit of piezoelectric element, first piezoelectric element will charge to electric capacity Cp, after the voltage exceeding the filter capacitor of rectifier bridge rear end when the voltage of electric capacity Cp adds the pressure drop of two diodes, could to the capacitor charging of rear end, not only organic efficiency is low to cause this circuit, and the energy reclaimed is by rear end capacitance voltage and load impact to a certain extent.
Therefore, researcher proposes multiple nonlinear energy and extracts circuit, as synchronous switched inductor circuit (P-SSHI), series connection synchro switch inductive circuit (S-SSHI), synchronously charge-extraction circuit (SECE), and the two simultaneous switching circuits (DSSH) derived from this basis, enhancement mode two synchro switch inductance recovery circuit (ESSH) and the synchronous charge-extraction circuit (OSECE) of Optimization-type etc.
Synchro switch inductive circuit (P-SSHI) still affects larger by the size of rear end capacitance voltage and load impedance with synchro switch inductive circuit (S-SSHI) regenerative power of connecting, synchronous charge-extraction circuit (SECE), two simultaneous switching circuit (DSSH), the two synchro switch inductance recovery circuit (ESSH) of enhancement mode and the synchronous charge-extraction circuit (OSECE) of Optimization-type solve this problem, its regenerative power has nothing to do with rear end electric capacity and load, but, although these circuit in theory very have advantage, actually to implement or too complicated, or self circuit cannot complete collection separately, need to be powered by external power source, or cause circuit volume larger owing to needing more discrete component, not easy of integration, therefore be difficult to promote.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of circuit small volume, self-powered CMOS piezoelectric vibration energy collector that power consumption is lower, adopts self-powered design without the need to external power source, and can realize the high efficiency extraction to piezoelectric energy electric charge.
The present invention solves the problems of the technologies described above adopted technical scheme: a kind of self-powered CMOS piezoelectric vibration energy collector, comprise CMOS piezoelectricity synchronous charge-extraction acquisition interface circuit and afterflow accumulator, described CMOS piezoelectricity synchronous charge-extraction acquisition interface circuit adopts integrated circuit form encapsulation, described CMOS piezoelectricity synchronous charge-extraction acquisition interface circuit is provided with the first testing circuit and exports control interface, second testing circuit exports control interface, first piezoelectric element connecting interface, second piezoelectric element connecting interface, first capacitance detecting interface, second capacitance detecting interface, external inductive interface and grounding ports, the first described piezoelectric element connecting interface is used for being connected with one end of piezoelectric element, the second described piezoelectric element connecting interface is used for being connected with the other end of piezoelectric element, described afterflow accumulator comprises fly-wheel diode, inductance and storage capacitor, described external inductive interface is connected with the positive pole of described fly-wheel diode and one end of described inductance respectively, the negative pole of described fly-wheel diode is connected with the anode of described storage capacitor, the anode of described storage capacitor is used for providing voltage to external electric equipment, the negative terminal of described storage capacitor, the other end of described inductance and the equal ground connection of described grounding ports, described CMOS piezoelectricity synchronous charge-extraction acquisition interface circuit comprises forward extremum extracting module, reverse extreme value detection module, positive and negative extreme value interlock switch, both forward and reverse directions vibration automatic transfer switch and dynamic substrate lever selection module, described positive and negative extreme value interlock switch comprises the 3rd NMOS tube, 4th NMOS tube, 9th NMOS tube, tenth NMOS tube, 7th PMOS and the 8th PMOS, described both forward and reverse directions vibration automatic transfer switch comprises the 7th NMOS tube, 8th NMOS tube, 3rd PMOS and the 4th PMOS, described dynamic substrate lever selection module comprises the 5th NMOS tube and the 6th NMOS tube, the drain electrode of the 3rd described NMOS tube respectively with the first Signal transmissions end of described forward extremum extracting module, the secondary signal transmission ends of described reverse extreme value detection module, the grid of the 7th described NMOS tube, the grid of the 4th described PMOS, the source electrode of the tenth described NMOS tube, the drain electrode of the 8th described PMOS, one end of the second described piezoelectric element connecting interface and described piezoelectric element connects, the grid of the 3rd described NMOS tube respectively with the 3rd Signal transmissions end of described forward extremum extracting module, the grid of the 9th described NMOS tube, the grid of the 8th described PMOS and the first described testing circuit export control interface and connect, the source electrode of the 3rd described NMOS tube is connected with the drain electrode of the 3rd described PMOS, the grid of the 3rd described PMOS respectively with the first described piezoelectric element connecting interface, the other end of described piezoelectric element, the source electrode of the 9th described NMOS tube, the drain electrode of the 7th described PMOS, the secondary signal transmission ends of described forward extremum extracting module, the drain electrode of the 4th described NMOS tube, first Signal transmissions end of described reverse extreme value detection module and the grid of the 8th described NMOS tube connect, the source electrode of the 3rd described PMOS respectively with the grid of the 5th described NMOS tube, described grounding ports, the drain electrode of the 6th described NMOS tube and the source electrode of the 4th described PMOS connect, the grid of the 4th described NMOS tube respectively with the 3rd Signal transmissions end of described reverse extreme value detection module, the second described testing circuit exports control interface, the grid of the tenth described NMOS tube and the grid of the 7th described PMOS connect, the source electrode of the 4th described NMOS tube is connected with the drain electrode of the 4th described PMOS, the source electrode of the 5th described NMOS tube connects with the IC substrate at described CMOS piezoelectricity synchronous charge-extraction acquisition interface circuit place and the source electrode of the 6th described NMOS tube respectively, the drain electrode of the 5th described NMOS tube respectively with described external inductive interface, the source electrode of the 7th described NMOS tube, the grid of the 6th described NMOS tube and the source electrode of the 8th described NMOS tube connect, the drain electrode of the 7th described NMOS tube is connected with the drain electrode of the 9th described NMOS tube and the source electrode of the 7th described PMOS respectively, the drain electrode of the 8th described NMOS tube is connected with the source electrode of the 8th described PMOS and the drain electrode of the tenth described NMOS tube respectively, 4th Signal transmissions end of described forward extremum extracting circuit is connected with the first described capacitance detecting interface, 4th Signal transmissions end of described reverse extreme value testing circuit is connected with the second described capacitance detecting interface, the substrate of the 3rd described NMOS tube, the substrate of the 4th described NMOS tube, the substrate of the 7th described NMOS tube, the substrate of the 8th described NMOS tube, the substrate of the 9th described NMOS tube and the substrate of the tenth described NMOS tube all adopt dark N-well process and described IC substrate to isolate.
Described forward extremum extracting module comprises the first NMOS tube, first PMOS, 5th PMOS, first Detection capacitance and the first pull down resistor, described reverse extreme value detection module comprises the second NMOS tube, second PMOS, 6th PMOS, second Detection capacitance and the second pull down resistor, the source electrode of the first described NMOS tube respectively with the source electrode of the first described PMOS, the grid of the 5th described PMOS, the drain electrode of the 3rd described NMOS tube, the grid of the second described NMOS tube and one end of the second described Detection capacitance connect, the grid of the first described NMOS tube respectively with one end of the first described Detection capacitance, the first described piezoelectric element connecting interface, the source electrode of the second described NMOS tube, the source electrode of the second described PMOS and the grid of the 6th described PMOS connect, the drain electrode of the first described NMOS tube respectively with the grid of the first described PMOS, the drain electrode of the first described PMOS, the source electrode of the 5th described PMOS, the other end of the first described Detection capacitance, source electrode and the first described capacitance detecting interface of the second described NMOS tube connect, one end that the drain electrode of the 5th described PMOS exports control interface and the first described pull down resistor with the first described testing circuit is respectively connected, the other end of the first described pull down resistor is connected with described grounding ports, the drain electrode of the second described NMOS tube respectively with the grid of the second described PMOS, the drain electrode of the second described PMOS, the source electrode of the 6th described PMOS, the other end and the second described capacitance detecting interface of the second described Detection capacitance connect, one end that the drain electrode of the 6th described PMOS exports control interface and the second described pull down resistor with the second described testing circuit is respectively connected, the other end of the second described pull down resistor is connected with described grounding ports, the substrate of the first described NMOS tube and the substrate of the second described NMOS tube all adopt dark N-well process and described IC substrate to isolate.In positive and negative extreme value interlock switch, the 3rd NMOS tube, the 9th NMOS tube and the 8th PMOS are one group, and the 4th NMOS tube, the tenth NMOS tube and the 7th PMOS are another groups; After forward extremum extracting module detects forward extreme value, export a high level export control interface to the first testing circuit, drive the 3rd NMOS tube, the 9th NMOS tube conducting, 8th PMOS is closed, now under pull down resistor effect, keep low level because the second testing circuit exports control interface always, so the 4th NMOS tube and the tenth NMOS tube are closed, the 7th PMOS conducting.Wherein the transmission gate conducting simultaneously of the 9th NMOS tube and the 7th PMOS formation, solves NMOS tube and transmits the loss of voltage problem of the second piezoelectric element connecting interface when low-voltage; After reverse extreme value detection module detects reverse extreme value, export a high level export control interface to the second testing circuit, drive the 4th NMOS tube, the tenth NMOS tube conducting, 7th PMOS is closed, now under the effect of pull down resistor, keep low level because the first testing circuit exports control interface always, so the 3rd NMOS tube, the 9th NMOS tube are closed, the 8th PMOS conducting; Wherein the transmission gate conducting simultaneously of the tenth NMOS tube and the 8th PMOS formation, solves the loss of voltage problem of NMOS tube when the low-voltage of transmission first piezoelectric element connecting interface.
Compared with prior art, the invention has the advantages that all detection roads of integrated circuit and switching circuitry circuit all adopt CMOS technology to realize, be easy to integrated, peripheral cell is few, reduce circuit volume, reduce conduction voltage drop and conducting resistance simultaneously, reduce oneself power consumption; Adopt self-powered design without the need to external power source, automatically can detect the state of piezoelectric element and the break-make of control switchgroup to extract energy, and provide electric energy to external electric equipment; Adopt the dark N-well process of NMOS that NMOS tube and external substrate are isolated, can carry out comparatively freely independent logic control automatically can detect the state of piezoelectric element and the break-make of control switchgroup to extract energy, reduce further power consumption; Both forward and reverse directions is utilized to vibrate parasitic diode in automatic transfer switch, keep original conducting and closed condition, part energy reverse charging in inductance is got back to inner Detection capacitance inner, as the basic electric charge extracted next time, because resonance frequency is higher than outside frequency of oscillation a lot, make internal capacitance snap back stored charge, thus the state completing unit switch fast switches, and enter energy accumulation and the leaching process of other half vibration period, increase time and the level height of charge accumulated, therefore improve the efficiency of Energy extraction; The interface that dynamic substrate lever selection module selects level in external inductive interface and grounding ports minimum all the time and IC substrate short circuit, the substrate of the NMOS tube of surrounding to prevent the dark N trap in circuit and IC substrate conducting, and the potential difference on the source electrode of the NMOS tube that cannot surround according to the dark N trap in circuit separately and grid normally works.
Accompanying drawing explanation
Fig. 1 is electrical block diagram of the present invention;
Fig. 2 is external test circuitry figure of the present invention.
Embodiment
Below in conjunction with accompanying drawing embodiment, the present invention is described in further detail.
A kind of self-powered CMOS piezoelectric vibration energy collector, comprise CMOS piezoelectricity synchronous charge-extraction acquisition interface circuit and afterflow accumulator, CMOS piezoelectricity synchronous charge-extraction acquisition interface circuit adopts integrated circuit form encapsulation, CMOS piezoelectricity synchronous charge-extraction acquisition interface circuit is provided with the first testing circuit and exports control interface CON1, second testing circuit exports control interface CON2, first piezoelectric element connecting interface PZT1, second piezoelectric element connecting interface PZT2, first capacitance detecting interface CDET1, second capacitance detecting interface CDET2, external inductive interface LPIN and grounding ports GND, first piezoelectric element connecting interface PZT1 is used for being connected with one end of piezoelectric element PZT, second piezoelectric element connecting interface PZT2 is used for being connected with the other end of piezoelectric element PZT, afterflow accumulator comprises sustained diode 1, inductance L and storage capacitor Crect, external inductive interface LPIN is connected with the positive pole of sustained diode 1 and one end of inductance L respectively, the negative pole of sustained diode 1 is connected with the anode of storage capacitor Crect, the anode of storage capacitor Crect is used for providing voltage V to external electric equipment
dC, the negative terminal of storage capacitor Crect, the other end of inductance L and the equal ground connection of grounding ports GND, CMOS piezoelectricity synchronous charge-extraction acquisition interface circuit comprises forward extremum extracting module, reverse extreme value detection module, positive and negative extreme value interlock switch, both forward and reverse directions vibration automatic transfer switch and dynamic substrate lever selection module, positive and negative extreme value interlock switch comprises the 3rd NMOS tube Mn3, 4th NMOS tube Mn4, 9th NMOS tube Mn9, tenth NMOS tube Mn10, 7th PMOS Mp7 and the 8th PMOS Mp8, both forward and reverse directions vibration automatic transfer switch comprises the 7th NMOS tube Mn7, 8th NMOS tube Mn8, 3rd PMOS Mp3 and the 4th PMOS Mp4, dynamic substrate lever selection module comprises the 5th NMOS tube Mn5 and the 6th NMOS tube Mn6, the drain electrode of the 3rd NMOS tube Mn3 respectively with the first Signal transmissions end of forward extremum extracting module, the secondary signal transmission ends of reverse extreme value detection module, the grid of the 7th NMOS tube Mn7, the grid of the 4th PMOS Mp4, the source electrode of the tenth NMOS tube Mn10, the drain electrode of the 8th PMOS Mp8, one end of second piezoelectric element connecting interface PZT2 and piezoelectric element PZT connects, the grid of the 3rd NMOS tube Mn3 respectively with the 3rd Signal transmissions end of forward extremum extracting module, the grid of the 9th NMOS tube Mn9, the grid of the 8th PMOS Mp8 and the first testing circuit export control interface CON1 and connect, and the source electrode of the 3rd NMOS tube Mn3 is connected with the drain electrode of the 3rd PMOS Mp3, the grid of the 3rd PMOS Mp3 respectively with the first piezoelectric element connecting interface PZT1, the other end of piezoelectric element PZT, the source electrode of the 9th NMOS tube Mn9, the drain electrode of the 7th PMOS Mp7, the secondary signal transmission ends of forward extremum extracting module, the drain electrode of the 4th NMOS tube Mn4, the grid of the first Signal transmissions end of reverse extreme value detection module and the 8th NMOS tube Mn8 connects, the source electrode of the 3rd PMOS Mp3 respectively with the grid of the 5th NMOS tube Mn5, grounding ports GND, the source electrode of the drain electrode of the 6th NMOS tube Mn6 and the 4th PMOS Mp4 connects, the grid of the 4th NMOS tube Mn4 respectively with the 3rd Signal transmissions end of reverse extreme value detection module, second testing circuit exports control interface CON2, the grid of the tenth NMOS tube Mn10 and the grid of the 7th PMOS Mp7 connect, the source electrode of the 4th NMOS tube Mn4 is connected with the drain electrode of the 4th PMOS Mp4, the source electrode of the 5th NMOS tube Mn5 respectively IC substrate Sub at charge-extraction acquisition interface circuit place synchronous with CMOS piezoelectricity and the source electrode of the 6th NMOS tube Mn6 connects, the drain electrode of the 5th NMOS tube Mn5 respectively with external inductive interface LPIN, the source electrode of the 7th NMOS tube Mn7, the grid of the 6th NMOS tube Mn6 and the source electrode of the 8th NMOS tube Mn8 connect, the drain electrode of the 7th NMOS tube Mn7 is connected with the drain electrode of the 9th NMOS tube Mn9 and the source electrode of the 7th PMOS Mp7 respectively, the drain electrode of the 8th NMOS tube Mn8 is connected with the source electrode of the 8th PMOS Mp8 and the drain electrode of the tenth NMOS tube Mn10 respectively, 4th Signal transmissions end of forward extremum extracting circuit is connected with the first capacitance detecting interface CDET1, 4th Signal transmissions end of reverse extreme value testing circuit is connected with the second capacitance detecting interface CDET2, the substrate of the 3rd NMOS tube Mn3, the substrate of the 4th NMOS tube Mn4, the substrate of the 7th NMOS tube Mn7, the substrate of the 8th NMOS tube Mn8, the substrate of the 9th NMOS tube Mn9 and the substrate of the tenth NMOS tube Mn10 all adopt dark N-well process and IC substrate Sub to isolate.
Forward extremum extracting module comprises the first NMOS tube Mn1, first PMOS Mp1, 5th PMOS Mp5, first Detection capacitance C1 and the first pull down resistor Rdp1, reverse extreme value detection module comprises the second NMOS tube Mn2, second PMOS Mp2, 6th PMOS Mp6, the source electrode of the second Detection capacitance C2 and the second pull down resistor Rdp2, the first NMOS tube Mn1 respectively with the source electrode of the first PMOS Mp1, the grid of the 5th PMOS Mp5, the drain electrode of the 3rd NMOS tube Mn3, one end of the grid of the second NMOS tube Mn2 and the second Detection capacitance C2 connects, the grid of the first NMOS tube Mn1 respectively with one end of the first Detection capacitance C1, first piezoelectric element connecting interface PZT1, the source electrode of the second NMOS tube Mn2, the grid of the source electrode of the second PMOS Mp2 and the 6th PMOS Mp6 connects, the drain electrode of the first NMOS tube Mn1 respectively with the grid of the first PMOS Mp1, the drain electrode of the first PMOS Mp1, the source electrode of the 5th PMOS Mp5, the other end of the first Detection capacitance C1, source electrode and the first capacitance detecting interface CDET1 of the second NMOS tube Mn2 connect, the drain electrode of the 5th PMOS Mp5 exports control interface CON1 and the first pull down resistor Rdp1 respectively one end with the first testing circuit is connected, the other end of the first pull down resistor Rdp1 is connected with grounding ports GND, the drain electrode of the second NMOS tube Mn2 respectively with the grid of the second PMOS Mp2, the drain electrode of the second PMOS Mp2, the source electrode of the 6th PMOS Mp6, the other end and the second capacitance detecting interface CDET2 of the second Detection capacitance C2 connect, the drain electrode of the 6th PMOS Mp6 exports control interface CON2 and the second pull down resistor Rdp2 respectively one end with the second testing circuit is connected, the other end of the second pull down resistor Rdp2 is connected with grounding ports GND, and the substrate of the first NMOS tube Mn1 and the substrate of the second NMOS tube Mn2 all adopt dark N-well process and IC substrate Sub to isolate.
The detailed operation principle of above embodiment is as follows:
Second piezoelectric element connecting interface PZT2 is connected with the two ends of piezoelectric element PZT respectively with the first piezoelectric element connecting interface PZT1, be greater than in the forward vibration half period of the voltage Vpzt1 of the first piezoelectric element connecting interface PZT1 at the voltage Vpzt2 of the second piezoelectric element connecting interface PZT2, the various piece operating state change of circuit is as follows: in forward extremum extracting module, because the level of the grid of the first NMOS tube Mn1 is identical with the level of the first piezoelectric element connecting interface PZT1, so the first NMOS tube Mn1 is in closed condition, owing to there is parasitic diode between the substrate of the first NMOS tube Mn1 and the drain electrode of the first NMOS tube Mn1, when the voltage Vpzt2 of the second piezoelectric element connecting interface PZT2 exceeds a diode drop VD than the voltage Vpzt1 of the first piezoelectric element connecting interface PZT1, this parasitic diode conducting, second piezoelectric element connecting interface PZT2 is charged to the first Detection capacitance C1 by the parasitic diode of the first NMOS tube Mn1, the level of the first capacitance detecting interface CDET1 is made to followed by the increase of Vpzt2 and increase, its voltage VCDET1=Vpzt2-VD.When piezoelectric element PZT vibrates forward extreme value place, Vpzt2 reaches maximum, after having crossed forward extreme value place, Vpzt2 starts to decline, and VCDET1 remains unchanged, when Vpzt2 drop to than VCDET1 also a low PMOS on state threshold voltage Vthp time, Vpzt2=VCDET1-Vthp, 5th PMOS Mp5 conducting, voltage VCDET1 is transferred to the first testing circuit and export control interface CON1, for the positive and negative extreme value interlock switch of next stage provides start signal, thus complete the extraction of synchronous electric charge, wherein the first PMOS Mp1 utilizes its parasitic diode also to be extracted in inductance by the electric charge stored in the first Detection capacitance C1.In this forward vibration half period, because the level of the grid of the second NMOS tube Mn2 is identical with the level of the second piezoelectric element connecting interface PZT2, so the second NMOS tube Mn2 is in conducting state, conducting resistance is very little, directly equivalent capacity inner with piezoelectric element is in parallel for the second Detection capacitance C2 that thinks that can be equivalent, owing to there is not diode drop, the energy in extraction second Detection capacitance C2 that therefore can be more complete.
Be greater than in the reversal of vibrations half period of the second piezoelectric element connecting interface PZT2 voltage Vpzt2 at the first piezoelectric element connecting interface PZT1 pin voltage Vpzt1, the various piece operating state change of circuit is as follows: because the level of the grid of the second NMOS tube Mn2 is identical with the level of the second piezoelectric element connecting interface PZT2, so the second NMOS tube Mn2 is in closed condition, owing to there is parasitic diode between the substrate of the second NMOS tube Mn2 and the drain electrode of the second NMOS tube Mn2, when the voltage Vpzt1 of the first piezoelectric element connecting interface PZT1 exceeds a diode drop VD than the voltage Vpzt2 of the second piezoelectric element connecting interface PZT2, this parasitic diode conducting, first piezoelectric element connecting interface PZT1 is charged to the second Detection capacitance C2 by the parasitic diode of the second NMOS tube Mn2, the level of the second capacitance detecting interface CDET2 is made to followed by the increase of Vpzt1 and increase, its voltage VCDET2=Vpzt1-VD, when piezoelectric element PZT vibrates reverse extreme value place, Vpzt1 reaches maximum, when after the vibrated reverse extreme value place of piezoelectric element PZT, Vpzt1 starts to decline, and VCDET2 remains unchanged, when Vpzt1 drop to than VCDET2 also a low PMOS on state threshold voltage Vthp time, Vpzt1=VCDET2-Vthp, 6th PMOS Mp6 conducting, voltage VCDET2 is transferred to the second testing circuit output control terminal mouth, for the positive and negative extreme value interlock switch of next stage provides start signal, thus complete the extraction of synchronous electric charge, wherein the second PMOS Mp2 utilizes its parasitic diode also to be extracted in inductance by the electric charge stored in the second Detection capacitance C2, in forward extremum extracting module, because the grid of the first NMOS tube Mn1 is identical with the level of the first piezoelectric element connecting interface PZT1, so the first NMOS tube Mn1 is in conducting state, conducting resistance is very little, directly equivalent capacity inner with piezoelectric element is in parallel for the first Detection capacitance C1 that thinks that can be equivalent, owing to there is not diode drop, so the energy in extraction first Detection capacitance C1 that can be more complete.
In positive and negative extreme value interlock switch, the 3rd NMOS tube Mn3, the 9th NMOS tube Mn9 and the 8th PMOS Mp8 are one group, and the 4th NMOS tube Mn4, the tenth NMOS tube Mn10 and the 7th PMOS Mp7 are another groups; After forward extremum extracting module detects forward extreme value, export a high level and export control interface CON1 to the first testing circuit, drive the 3rd NMOS tube Mn3, the 9th NMOS tube Mn9 conducting, 8th PMOS Mp8 closes, now under pull down resistor effect, keep low level because the second testing circuit exports control interface CON2 always, so the 4th NMOS tube Mn4 and the tenth NMOS tube Mn10 closes, the 7th PMOS Mp7 conducting.Wherein the transmission gate conducting simultaneously of the 9th NMOS tube Mn9 and the 7th PMOS Mp7 formation, solves the loss of voltage problem of NMOS tube when the low-voltage of transmission second piezoelectric element connecting interface PZT2; After reverse extreme value detection module detects reverse extreme value, export a high level and export control interface CON2 to the second testing circuit, drive the 4th NMOS tube Mn4, the tenth NMOS tube Mn10 conducting, 7th PMOS Mp7 closes, now under the effect of pull down resistor, keep low level because the first testing circuit exports control interface CON1 always, so the 3rd NMOS tube Mn3, the 9th NMOS tube Mn9 close, the 8th PMOS Mp8 conducting.Wherein the transmission gate conducting simultaneously of the tenth NMOS tube Mn10 and the 8th PMOS Mp8 formation, solves the loss of voltage problem of NMOS tube when the low-voltage of transmission first piezoelectric element connecting interface PZT1.
In both forward and reverse directions vibration automatic transfer switch, the 3rd PMOS Mp3 and the 7th NMOS tube Mn7 is one group, and the 4th PMOS Mp4 and the 8th NMOS tube Mn8 is another group; Be greater than in the forward vibration half period of the voltage Vpzt1 of the first piezoelectric element connecting interface PZT1 at the voltage Vpzt2 of the second piezoelectric element connecting interface PZT2, after two ends pressure reduction is greater than metal-oxide-semiconductor threshold voltage, 3rd PMOS Mp3 and the 7th NMOS tube Mn7 conducting, the 4th PMOS Mp4 and the 8th NMOS tube Mn8 ends; When the voltage Vpzt1 of the first piezoelectric element connecting interface PZT1 at piezoelectric element PZT is greater than in the reversal of vibrations half period of the voltage Vpzt2 of the second piezoelectric element connecting interface PZT2, after two ends pressure reduction is greater than metal-oxide-semiconductor threshold voltage, 4th PMOS Mp4 and the 8th NMOS tube Mn8 conducting, the 3rd PMOS Mp3 and the 7th NMOS tube Mn7 ends.
The leaching process of integrated circuit to piezoelectric vibration energy is divided into two stages, in each stage, the current potential at external inductive interface LPIN and grounding ports GND two ends has height change, at first stage, the equivalent capacity of piezoelectric element PZT inside and inductance L form LC resonance, the voltage of the current potential of grounding ports GND and the equivalent capacity of piezoelectric element PZT inside is equal, so the level of grounding ports GND is higher than the level of external inductive interface LPIN, after the internal charge of the equivalent capacity of piezoelectric element PZT inside has been extracted, enter second stage, because inductance L will keep original electric current, and original loop disconnects, induced electromotive force can only be produced and carry out afterflow through sustained diode 1, now the level of external inductive interface LPIN is higher than the level of grounding ports GND, the function of dynamic substrate level selection circuit is an interface and IC substrate Sub short circuit of selecting level in external inductive interface LPIN and grounding ports GND minimum all the time, the substrate of the NMOS tube of surrounding to prevent the dark N trap in circuit and IC substrate Sub conducting, and cannot normally work according to the potential difference on its source electrode and grid separately.
After completing the extraction of LC resonant energy, the voltage difference at the first piezoelectric element connecting interface PZT1 and the second piezoelectric element connecting interface PZT2 two ends has been zero, and the 3rd PMOS Mp3, the 7th NMOS tube Mn7, the 4th PMOS Mp4 and the 8th NMOS tube Mn8 have the existence of parasitic diode, can continue to keep original conducting and closed condition, LC resonance is proceeded, part energy reverse charging in inductance L is got back to inner Detection capacitance inner, as the basic electric charge " seed " extracted next time; Because resonance frequency is higher than outside frequency of oscillation a lot, make internal capacitance snap back stored charge, thus the state completing unit switch fast switches, and enter energy accumulation and the leaching process of other half vibration period, increase time and the level height of charge accumulated, therefore improve the efficiency of Energy extraction.
Due to the first pull down resistor Rdp1 and the usual resistance of the second pull down resistor Rdp2 larger, and the first Detection capacitance C1 and the second Detection capacitance C2 is electric capacity in less sheet, during practical application, according to the performance of different piezoelectric elements or mechanism, non-essential resistance in parallel can be carried out to reduce pull down resistor value to pull down resistor by external test circuitry figure shown in reference diagram 2, or increase capacitance by external detection electric capacity in parallel.
Claims (2)
1. a self-powered CMOS piezoelectric vibration energy collector, it is characterized in that comprising CMOS piezoelectricity synchronous charge-extraction acquisition interface circuit and afterflow accumulator, described CMOS piezoelectricity synchronous charge-extraction acquisition interface circuit adopts integrated circuit form encapsulation, described CMOS piezoelectricity synchronous charge-extraction acquisition interface circuit is provided with the first testing circuit and exports control interface, second testing circuit exports control interface, first piezoelectric element connecting interface, second piezoelectric element connecting interface, first capacitance detecting interface, second capacitance detecting interface, external inductive interface and grounding ports, the first described piezoelectric element connecting interface is used for being connected with one end of piezoelectric element, the second described piezoelectric element connecting interface is used for being connected with the other end of piezoelectric element, described afterflow accumulator comprises fly-wheel diode, inductance and storage capacitor, described external inductive interface is connected with the positive pole of described fly-wheel diode and one end of described inductance respectively, the negative pole of described fly-wheel diode is connected with the anode of described storage capacitor, the anode of described storage capacitor is used for providing voltage to external electric equipment, the negative terminal of described storage capacitor, the other end of described inductance and the equal ground connection of described grounding ports, described CMOS piezoelectricity synchronous charge-extraction acquisition interface circuit comprises forward extremum extracting module, reverse extreme value detection module, positive and negative extreme value interlock switch, both forward and reverse directions vibration automatic transfer switch and dynamic substrate lever selection module, described positive and negative extreme value interlock switch comprises the 3rd NMOS tube, 4th NMOS tube, 9th NMOS tube, tenth NMOS tube, 7th PMOS and the 8th PMOS, described both forward and reverse directions vibration automatic transfer switch comprises the 7th NMOS tube, 8th NMOS tube, 3rd PMOS and the 4th PMOS, described dynamic substrate lever selection module comprises the 5th NMOS tube and the 6th NMOS tube, the drain electrode of the 3rd described NMOS tube respectively with the first Signal transmissions end of described forward extremum extracting module, the secondary signal transmission ends of described reverse extreme value detection module, the grid of the 7th described NMOS tube, the grid of the 4th described PMOS, the source electrode of the tenth described NMOS tube, the drain electrode of the 8th described PMOS, one end of the second described piezoelectric element connecting interface and described piezoelectric element connects, the grid of the 3rd described NMOS tube respectively with the 3rd Signal transmissions end of described forward extremum extracting module, the grid of the 9th described NMOS tube, the grid of the 8th described PMOS and the first described testing circuit export control interface and connect, the source electrode of the 3rd described NMOS tube is connected with the drain electrode of the 3rd described PMOS, the grid of the 3rd described PMOS respectively with the first described piezoelectric element connecting interface, the other end of described piezoelectric element, the source electrode of the 9th described NMOS tube, the drain electrode of the 7th described PMOS, the secondary signal transmission ends of described forward extremum extracting module, the drain electrode of the 4th described NMOS tube, first Signal transmissions end of described reverse extreme value detection module and the grid of the 8th described NMOS tube connect, the source electrode of the 3rd described PMOS respectively with the grid of the 5th described NMOS tube, described grounding ports, the drain electrode of the 6th described NMOS tube and the source electrode of the 4th described PMOS connect, the grid of the 4th described NMOS tube respectively with the 3rd Signal transmissions end of described reverse extreme value detection module, the second described testing circuit exports control interface, the grid of the tenth described NMOS tube and the grid of the 7th described PMOS connect, the source electrode of the 4th described NMOS tube is connected with the drain electrode of the 4th described PMOS, the source electrode of the 5th described NMOS tube connects with the IC substrate at described CMOS piezoelectricity synchronous charge-extraction acquisition interface circuit place and the source electrode of the 6th described NMOS tube respectively, the drain electrode of the 5th described NMOS tube respectively with described external inductive interface, the source electrode of the 7th described NMOS tube, the grid of the 6th described NMOS tube and the source electrode of the 8th described NMOS tube connect, the drain electrode of the 7th described NMOS tube is connected with the drain electrode of the 9th described NMOS tube and the source electrode of the 7th described PMOS respectively, the drain electrode of the 8th described NMOS tube is connected with the source electrode of the 8th described PMOS and the drain electrode of the tenth described NMOS tube respectively, 4th Signal transmissions end of described forward extremum extracting circuit is connected with the first described capacitance detecting interface, 4th Signal transmissions end of described reverse extreme value testing circuit is connected with the second described capacitance detecting interface, the substrate of the 3rd described NMOS tube, the substrate of the 4th described NMOS tube, the substrate of the 7th described NMOS tube, the substrate of the 8th described NMOS tube, the substrate of the 9th described NMOS tube and the substrate of the tenth described NMOS tube all adopt dark N-well process and described IC substrate to isolate.
2. a kind of self-powered CMOS piezoelectric vibration energy collector according to claim 1, it is characterized in that described forward extremum extracting module comprises the first NMOS tube, first PMOS, 5th PMOS, first Detection capacitance and the first pull down resistor, described reverse extreme value detection module comprises the second NMOS tube, second PMOS, 6th PMOS, second Detection capacitance and the second pull down resistor, the source electrode of the first described NMOS tube respectively with the source electrode of the first described PMOS, the grid of the 5th described PMOS, the drain electrode of the 3rd described NMOS tube, the grid of the second described NMOS tube and one end of the second described Detection capacitance connect, the grid of the first described NMOS tube respectively with one end of the first described Detection capacitance, the first described piezoelectric element connecting interface, the source electrode of the second described NMOS tube, the source electrode of the second described PMOS and the grid of the 6th described PMOS connect, the drain electrode of the first described NMOS tube respectively with the grid of the first described PMOS, the drain electrode of the first described PMOS, the source electrode of the 5th described PMOS, the other end of the first described Detection capacitance, source electrode and the first described capacitance detecting interface of the second described NMOS tube connect, one end that the drain electrode of the 5th described PMOS exports control interface and the first described pull down resistor with the first described testing circuit is respectively connected, the other end of the first described pull down resistor is connected with described grounding ports, the drain electrode of the second described NMOS tube respectively with the grid of the second described PMOS, the drain electrode of the second described PMOS, the source electrode of the 6th described PMOS, the other end and the second described capacitance detecting interface of the second described Detection capacitance connect, one end that the drain electrode of the 6th described PMOS exports control interface and the second described pull down resistor with the second described testing circuit is respectively connected, the other end of the second described pull down resistor is connected with described grounding ports, the substrate of the first described NMOS tube and the substrate of the second described NMOS tube all adopt dark N-well process and described IC substrate to isolate.
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