CN104917421B - A kind of self-powered CMOS piezoelectric vibration energy harvester - Google Patents

Abstract

The invention discloses a kind of self-powered CMOS piezoelectric vibration energy harvester, feature is including CMOS piezoelectricity synchronization charge-extraction acquisition interface circuit and afterflow accumulator, CMOS piezoelectricity synchronization charge-extraction acquisition interface circuit adopts integrated circuit form to encapsulate, it is provided with the first testing circuit output control interface on CMOS piezoelectricity synchronization charge-extraction acquisition interface circuit, second testing circuit output control interface, first piezoelectric element connecting interface, second piezoelectric element connecting interface, first capacitance detecting interface, second capacitance detecting interface, external inductive interface and grounding ports, CMOS piezoelectricity synchronization charge-extraction acquisition interface circuit includes positive extremum extracting module, reversely extremum extracting module, positive and negative extreme value interlock switch, both forward and reverse directions vibration automatic transfer switch and dynamic substrate lever selection module；Advantage be easily integrated, circuit small volume, power consumption relatively low, using self-powered design without external power source, energy extraction efficiency is higher.

Description

A kind of self-powered CMOS piezoelectric vibration energy harvester

Technical field

The present invention relates to technical field of integrated circuits, especially a kind of self-powered CMOS piezoelectric vibration energy harvester.

Background technology

Vibrational energy is almost present in any environment, the vibration of water, air flow, industrial machine, traffic in the Nature Instrument run when vibration, human motion, in addition breathing, heart beating, etc..Piezoelectric type vibration energy collecting device utilizes piezoelectric Direct piezoelectric effect, the vibrational energy in environment can be converted to electric energy.Piezoelectric vibration energy harvester has energy density height, knot Structure is simple, life-span length, easy of integration the advantages of and be widely used in that contemporary Micro Energy Lose is mobile and wearing electronic equipment in.

It is alternation because vibration makes the voltage that piezoelectric element exports, and it is to need surely that common small electronic equipment is powered Fixed DC voltage, so, need design interface circuit between piezoelectric element and electrical equipment, simplest is that diode is complete The rectifying and wave-filtering standard energy Acquisition Circuit of bridge rectification and a filter capacitor（SEH）But, due to the inside etc. of piezoelectric element The presence of electric capacity Cp in effect circuit, piezoelectric element first has to electric capacity Cp be charged, when the voltage of electric capacity Cp exceedes rectifier bridge rear end Filter capacitor voltage add the pressure drop of two diodes after, the electric capacity of rear end could be charged, lead to this circuit not Only organic efficiency is low, and the energy reclaiming is affected to a certain extent by rear end capacitance voltage and load.

Therefore, research worker proposes multiple nonlinear energies and extracts circuit, such as synchronous switched inductor circuit（P-SSHI）、 Series connection synchro switch inductive circuit（S-SSHI）, synchronous charge-extraction circuit（SECE）, and derive from this basis Double simultaneous switching circuits（DSSH）, the double synchro switch inductance recovery circuit of enhancement mode（ESSH）With Optimization-type synchronization charge-extraction electricity Road（OSECE）Deng.

Synchro switch inductive circuit（P-SSHI）With synchro switch inductive circuit of connecting（S-SSHI）Regenerative power is still subject to The size impact of rear end capacitance voltage and load impedance is larger；Synchronous charge-extraction circuit（SECE）, double simultaneous switching circuits （DSSH）, the double synchro switch inductance recovery circuit of enhancement mode（ESSH）With Optimization-type synchronization charge-extraction circuit（OSECE）Solve This problem, its regenerative power is unrelated with rear end electric capacity and load, although however, these circuit have in theory very much Advantageous, actual implement or excessively complicated, or itself circuit cannot individually complete to gather, and needs to be entered by external power source Row power supply, or due to needing more discrete component to lead to circuit volume larger, not easy of integration, therefore, it is difficult to promoting.

Content of the invention

The technical problem to be solved is the self-powered CMOS pressure providing a kind of circuit small volume, power consumption relatively low Electric oscillation energy collecting device, is designed without external power source using self-powered, and is capable of efficiently carrying to piezoelectric energy electric charge Take.

The present invention solves the technical scheme that adopted of above-mentioned technical problem：A kind of self-powered CMOS piezoelectric vibration energy is adopted Storage, including CMOS piezoelectricity synchronization charge-extraction acquisition interface circuit and afterflow accumulator, the synchronous electricity of described CMOS piezoelectricity Lotus is extracted acquisition interface circuit and adopts integrated circuit form to encapsulate, the synchronous charge-extraction acquisition interface circuit of described CMOS piezoelectricity On be provided with the first testing circuit output control interface, the second testing circuit output control interface, the first piezoelectric element connect Mouth, the second piezoelectric element connecting interface, the first capacitance detecting interface, the second capacitance detecting interface, external inductive interface and ground connection Port, the first described piezoelectric element connecting interface is used for being connected with one end of piezoelectric element, and the second described piezoelectric element is even Connection interface is used for being connected with the other end of piezoelectric element, and described afterflow accumulator includes fly-wheel diode, inductance and energy storage Electric capacity, described external inductive interface is connected with the positive pole of described fly-wheel diode and one end of described inductance respectively, institute The negative pole of the fly-wheel diode stated is connected with the anode of described storage capacitor, and the anode of described storage capacitor is used for outside Electrical equipment provides voltage, and the described negative terminal of storage capacitor, the other end of described inductance and described grounding ports all connect Ground, described CMOS piezoelectricity synchronization charge-extraction acquisition interface circuit includes positive extremum extracting module, reverse extremum extracting mould Block, positive and negative extreme value interlock switch, both forward and reverse directions vibration automatic transfer switch and dynamic substrate lever selection module, described is positive and negative Extreme value interlock switch includes the 3rd NMOS tube, the 4th NMOS tube, the 9th NMOS tube, the tenth NMOS tube, the 7th PMOS and the 8th PMOS, described both forward and reverse directions vibration automatic transfer switch includes the 7th NMOS tube, the 8th NMOS tube, the 3rd PMOS and the Four PMOS, described dynamic substrate lever selection module includes the 5th NMOS tube and the 6th NMOS tube, described the 3rd NMOS The drain electrode of pipe respectively with the first signal transmission end of described positive extremum extracting module, described reverse extremum extracting module Secondary signal transmission ends, the described grid of the 7th NMOS tube, the described grid of the 4th PMOS, the tenth described NMOS tube Source electrode, the described drain electrode of the 8th PMOS, the one of the second described piezoelectric element connecting interface and described piezoelectric element End connects, grid the 3rd signal transmission end, the institute with described positive extremum extracting module respectively of described the 3rd NMOS tube The grid of the 9th NMOS tube, the described grid of the 8th PMOS and the first described testing circuit output control interface stated are even Connect, the described source electrode of the 3rd NMOS tube is connected with the drain electrode of the 3rd described PMOS, the grid of described the 3rd PMOS Respectively with the first described piezoelectric element connecting interface, the other end of described piezoelectric element, the 9th described NMOS tube source Pole, the described drain electrode of the 7th PMOS, the secondary signal transmission ends of described positive extremum extracting module, the described the 4th The grid of the drain electrode of NMOS tube, the first signal transmission end of described reverse extremum extracting module and the 8th described NMOS tube is even Connect, the source electrode of described the 3rd PMOS respectively with the grid of the 5th described NMOS tube, described grounding ports, described The source electrode of the drain electrode of six NMOS tube and the 4th described PMOS connects, the grid of described the 4th NMOS tube respectively with described Reversely the 3rd signal transmission end of extremum extracting module, the second described testing circuit output control interface, the described the tenth The grid of the grid of NMOS tube and the 7th described PMOS connects, the described source electrode of the 4th NMOS tube and the described the 4th The drain electrode of PMOS connects, and the source electrode of the 5th described NMOS tube is connect with described CMOS piezoelectricity synchronization charge-extraction collection respectively The IC substrate that mouth circuit is located and the source electrode of the 6th described NMOS tube connect, and the drain electrode of the 5th described NMOS tube divides Not with described external inductive interface, the described source electrode of the 7th NMOS tube, the described grid of the 6th NMOS tube and described The source electrode of the 8th NMOS tube connects, the drain electrode of described the 7th NMOS tube respectively with the drain electrode of the 9th described NMOS tube and described The source electrode of the 7th PMOS connect, drain electrode source electrode and the institute with the 8th described PMOS respectively of described the 8th NMOS tube The drain electrode of the tenth NMOS tube stated connects, and described the 4th signal transmission end of positive extremum extracting circuit is electric with described first Hold detection interface connection, described the 4th signal transmission end of reverse extreme value testing circuit and the second described capacitance detecting interface Connect, the described substrate of the 3rd NMOS tube, the described substrate of the 4th NMOS tube, the described substrate of the 7th NMOS tube, institute The substrate of the substrate of the 8th NMOS tube, the described substrate of the 9th NMOS tube and the tenth described NMOS tube stated is all using deep N Trap technique is isolated with described IC substrate.

Described positive extremum extracting module includes the first NMOS tube, the first PMOS, the 5th PMOS, the first detection electricity Hold and the first pull down resistor, described reverse extremum extracting module include the second NMOS tube, the second PMOS, the 6th PMOS, Second detection electric capacity and the second pull down resistor, the source electrode source with the first described PMOS respectively of described the first NMOS tube Pole, the described grid of the 5th PMOS, the described drain electrode of the 3rd NMOS tube, the described grid of the second NMOS tube and described One end of the second detection electric capacity connect, the grid of described the first NMOS tube respectively with the first described detection electric capacity one End, the first described piezoelectric element connecting interface, the described source electrode of the second NMOS tube, the described source electrode of the second PMOS and The grid of the 6th described PMOS connects, the drain electrode grid with the first described PMOS respectively of described the first NMOS tube Pole, the described drain electrode of the first PMOS, the described source electrode of the 5th PMOS, described first detection electric capacity the other end, The described source electrode of the second NMOS tube and the first described capacitance detecting interface connect, and the drain electrode of the 5th described PMOS is distinguished It is connected with one end of the first described testing circuit output control interface and the first described pull down resistor, described first is drop-down The other end of resistance is connected with described grounding ports, the drain electrode of described the second NMOS tube respectively with the second described PMOS Grid, the described drain electrode of the second PMOS, the described source electrode of the 6th PMOS, described second detection electric capacity another End and described second capacitance detecting interface connect, the drain electrode of described the 6th PMOS respectively with the second described testing circuit One end of output control interface and the second described pull down resistor connects, the described other end of the second pull down resistor with described Grounding ports connect, the substrate of the described substrate of the first NMOS tube and the second described NMOS tube all adopt deep N-well technique and Described IC substrate isolation.In positive and negative extreme value interlock switch, the 3rd NMOS tube, the 9th NMOS tube and the 8th PMOS are One group, the 4th NMOS tube, the tenth NMOS tube and the 7th PMOS are another group；When positive extremum extracting module detects positive pole After value, one high level of output, to the first testing circuit output control interface, drives the 3rd NMOS tube, the 9th NMOS tube conducting, the Eight PMOS are closed, now because the second testing circuit output control interface is always maintained at low level under pull down resistor effect, So the 4th NMOS tube and the tenth NMOS tube are closed, the 7th PMOS conducting.Wherein the 9th NMOS tube and the 7th PMOS are constituted Transmission gate simultaneously turn on, solve NMOS tube transmission the loss of voltage in low-voltage for the second piezoelectric element connecting interface ask Topic；Export a high level to connect to the second testing circuit output control after reverse extremum extracting module detects reverse extreme value Mouthful, drive the 4th NMOS tube, the tenth NMOS tube conducting, the 7th PMOS is closed, now due to the first testing circuit output control Interface is always maintained at low level in the presence of pull down resistor, so the 3rd NMOS tube, the 9th NMOS tube are closed, the 8th PMOS Conducting；The transmission gate of the wherein the tenth NMOS tube and the 8th PMOS composition simultaneously turns on, and solves NMOS tube in transmission first pressure The loss of voltage problem during low-voltage of electric device connecting interface.

Compared with prior art, it is an advantage of the current invention that integrated circuit all detections road and switching circuitry circuit all adopt CMOS technology is realized it is easy to integrated, and peripheral cell is few, reduces circuit volume, reduces conduction voltage drop and conducting resistance simultaneously, Reduce oneself power consumption；Using self-powered design without external power source, the state of energy automatic detection piezoelectric element control combination Switch on-off to extract energy, and provide electric energy to external electric equipment；NMOS tube is made with outward using the deep N-well technique of NMOS Portion's substrate isolation, more can freely carry out the state of independent logic control energy automatic detection piezoelectric element and control combination is opened The break-make closed, to extract energy, reduce further power consumption；Using parasitic diode in both forward and reverse directions vibration automatic transfer switch, Keep original on and off, the part energy reverse charging in inductance is returned to inside internal detection electric capacity, makees For the basic electric charge extracting next time, because resonant frequency is more much higher than outside frequency of oscillation, internal capacitance snap back is made to amass Tired electric charge, thus being rapidly completed the state switching of cubicle switch, and enters energy accumulation and the extraction of other half vibration period Process, increases time and the level height of charge accumulated, therefore improves the efficiency of Energy extraction；Dynamic substrate lever selection mould Block selects a minimum interface of level in external inductive interface and grounding ports and IC substrate short circuit all the time, to prevent The substrate of the NMOS tube that the deep N-well in circuit is surrounded and IC substrate conducting, and cannot be individually according to the deep N in circuit Potential difference on the source electrode and grid of the NMOS tube that trap is surrounded carrys out normal work.

Brief description

Fig. 1 is the electrical block diagram of the present invention；

Fig. 2 is the external test circuitry figure of the present invention.

Specific embodiment

Below in conjunction with accompanying drawing embodiment, the present invention is described in further detail.

A kind of self-powered CMOS piezoelectric vibration energy harvester, including CMOS piezoelectricity synchronization charge-extraction acquisition interface circuit With afterflow accumulator, CMOS piezoelectricity synchronization charge-extraction acquisition interface circuit is using integrated circuit form encapsulation, CMOS piezoelectricity First testing circuit output control interface CON1, the second testing circuit output are provided with synchronous charge-extraction acquisition interface circuit Control interface CON2, the first piezoelectric element connecting interface PZT1, the second piezoelectric element connecting interface PZT2, the first capacitance detecting connect Mouth CDET1, the second capacitance detecting interface CDET2, external inductive interface LPIN and grounding ports GND, the first piezoelectric element connects Interface PZT1 is used for being connected with one end of piezoelectric element PZT, and the second piezoelectric element connecting interface PZT2 is used for and piezoelectric element PZT The other end connect, afterflow accumulator includes sustained diode 1, inductance L and storage capacitor Crect, external inductive interface LPIN is connected with the positive pole of sustained diode 1 and one end of inductance L respectively, the negative pole of sustained diode 1 and storage capacitor The anode of Crect connects, and the anode of storage capacitor Crect is used for providing voltage V to external electric equipment_DC, storage capacitor Crect Negative terminal, the other end of inductance L and grounding ports GND be all grounded, CMOS piezoelectricity synchronization charge-extraction acquisition interface circuit includes Positive extremum extracting module, reverse extremum extracting module, positive and negative extreme value interlock switch, both forward and reverse directions vibration automatic transfer switch and Dynamic substrate lever selection module, positive and negative extreme value interlock switch includes the 3rd NMOS tube Mn3, the 4th NMOS tube Mn4, the 9th NMOS Pipe Mn9, the tenth NMOS tube Mn10, the 7th PMOS Mp7 and the 8th PMOS Mp8, both forward and reverse directions vibrate automatic transfer switch bag Include the 7th NMOS tube Mn7, the 8th NMOS tube Mn8, the 3rd PMOS Mp3 and the 4th PMOS Mp4, dynamic substrate lever selection mould Block includes the 5th NMOS tube Mn5 and the 6th NMOS tube Mn6, the drain electrode of the 3rd NMOS tube Mn3 respectively with positive extremum extracting module The first signal transmission end, the secondary signal transmission ends of reverse extremum extracting module, the grid of the 7th NMOS tube Mn7, the 4th The grid of PMOS Mp4, the source electrode of the tenth NMOS tube Mn10, the drain electrode of the 8th PMOS Mp8, the second piezoelectric element connecting interface One end of PZT2 and piezoelectric element PZT connects, grid the 3rd letter with positive extremum extracting module respectively of the 3rd NMOS tube Mn3 Number transmission ends, the grid of the 9th NMOS tube Mn9, the grid of the 8th PMOS Mp8 and the first testing circuit output control interface CON1 connects, and the source electrode of the 3rd NMOS tube Mn3 is connected with the drain electrode of the 3rd PMOS Mp3, and the grid of the 3rd PMOS Mp3 is respectively With the first piezoelectric element connecting interface PZT1, the other end of piezoelectric element PZT, the source electrode of the 9th NMOS tube Mn9, the 7th PMOS The drain electrode of Mp7, the secondary signal transmission ends of positive extremum extracting module, the drain electrode of the 4th NMOS tube Mn4, reverse extremum extracting mould The grid of the first signal transmission end of block and the 8th NMOS tube Mn8 connects, the source electrode of the 3rd PMOS Mp3 respectively with the 5th NMOS The grid of pipe Mn5, the source electrode of grounding ports GND, the drain electrode of the 6th NMOS tube Mn6 and the 4th PMOS Mp4 connect, the 4th NMOS The grid of pipe Mn4 the 3rd signal transmission end, the second testing circuit output control interface with reverse extremum extracting module respectively The grid of CON2, the grid of the tenth NMOS tube Mn10 and the 7th PMOS Mp7 connects, the source electrode and the 4th of the 4th NMOS tube Mn4 The drain electrode of PMOS Mp4 connects, the source electrode synchronous charge-extraction acquisition interface circuit with CMOS piezoelectricity respectively of the 5th NMOS tube Mn5 The IC substrate Sub being located and the source electrode of the 6th NMOS tube Mn6 connect, the drain electrode of the 5th NMOS tube Mn5 respectively with external Inductive interface LPIN, the source electrode of the source electrode, the grid of the 6th NMOS tube Mn6 and the 8th NMOS tube Mn8 of the 7th NMOS tube Mn7 connect Connect, the drain electrode of the 7th NMOS tube Mn7 is connected with the drain electrode of the 9th NMOS tube Mn9 and the source electrode of the 7th PMOS Mp7 respectively, the 8th The drain electrode of NMOS tube Mn8 is connected with the source electrode of the 8th PMOS Mp8 and the drain electrode of the tenth NMOS tube Mn10 respectively, positive extreme value inspection 4th signal transmission end of slowdown monitoring circuit is connected with the first capacitance detecting interface CDET1, the 4th signal of reverse extreme value testing circuit Transmission ends are connected with the second capacitance detecting interface CDET2, the substrate of the 3rd NMOS tube Mn3, the substrate of the 4th NMOS tube Mn4, The substrate of seven NMOS tube Mn7, the lining of the substrate, the substrate of the 9th NMOS tube Mn9 and the tenth NMOS tube Mn10 of the 8th NMOS tube Mn8 Bottom is all isolated with IC substrate Sub using deep N-well technique.

Positive extremum extracting module includes the first NMOS tube Mn1, the first PMOS Mp1, the 5th PMOS Mp5, the first inspection Survey electric capacity C1 and the first pull down resistor Rdp1, reverse extremum extracting module include the second NMOS tube Mn2, the second PMOS Mp2, the Six PMOS Mp6, the second detection electric capacity C2 and the second pull down resistor Rdp2, the source electrode of the first NMOS tube Mn1 is respectively with first The source electrode of PMOS Mp1, the grid of the 5th PMOS Mp5, the drain electrode of the 3rd NMOS tube Mn3, the grid of the second NMOS tube Mn2 and One end of second detection electric capacity C2 connects, grid one end, first pressure with the first detection electric capacity C1 respectively of the first NMOS tube Mn1 Electric device connecting interface PZT1, the grid of the source electrode of the second NMOS tube Mn2, the source electrode of the second PMOS Mp2 and the 6th PMOS Mp6 Pole connects, the drain electrode of the first NMOS tube Mn1 respectively with the grid of the first PMOS Mp1, the drain electrode of the first PMOS Mp1, the 5th The source electrode of PMOS Mp5, the other end of the first detection electric capacity C1, the source electrode of the second NMOS tube Mn2 and the first capacitance detecting interface CDET1 connects, the drain electrode of the 5th PMOS Mp5 respectively with the first testing circuit output control interface CON1 and the first pull down resistor One end of Rdp1 connects, and the other end of the first pull down resistor Rdp1 is connected with grounding ports GND, the drain electrode of the second NMOS tube Mn2 Respectively with the grid of the second PMOS Mp2, the drain electrode of the second PMOS Mp2, the source electrode of the 6th PMOS Mp6, the second detection electricity Hold the other end of C2 and the second capacitance detecting interface CDET2 connect, the drain electrode of the 6th PMOS Mp6 respectively with the second testing circuit One end connection, the other end of the second pull down resistor Rdp2 and the earth terminal of output control interface CON2 and the second pull down resistor Rdp2 Mouth GND connects, and the substrate of the substrate of the first NMOS tube Mn1 and the second NMOS tube Mn2 is all served as a contrast with integrated circuit using deep N-well technique Bottom Sub isolates.

The detailed operation principle of above example is as follows：

Second piezoelectric element connecting interface PZT2 and the first piezoelectric element connecting interface PZT1 are respectively with piezoelectric element PZT's Two ends connect, and are more than the first piezoelectric element connecting interface PZT1 in the voltage Vpzt2 of the second piezoelectric element connecting interface PZT2 In the positive vibration half period of voltage Vpzt1, the various pieces working condition change of circuit is as follows：Positive extremum extracting module In, because the level of the grid of the first NMOS tube Mn1 is identical with the level of the first piezoelectric element connecting interface PZT1, so first NMOS tube Mn1 is closed, and posts due to existing between the substrate of the first NMOS tube Mn1 and the drain electrode of the first NMOS tube Mn1 Raw diode, when the second piezoelectric element connecting interface PZT2 voltage Vpzt2 than the first piezoelectric element connecting interface PZT1 electricity Vpzt1 is when exceeding a diode drop VD for pressure, and this parasitic diode turns on, and the second piezoelectric element connecting interface PZT2 passes through the The parasitic diode of one NMOS tube Mn1 charges to the first detection electric capacity C1, so that the level of the first capacitance detecting interface CDET1 is followed The increase of Vpzt2 and increase, its voltage VCDET1=Vpzt2-VD.When piezoelectric element PZT vibrates positive extreme value place, Vpzt2 reaches maximum, and after having crossed positive extreme value place, Vpzt2 begins to decline, and VCDET1 keeps constant, when Vpzt2 declines To than a VCDET1 also low PMOS on state threshold voltage Vthp when, Vpzt2=VCDET1-Vthp, the 5th PMOS Mp5 turns on, and voltage VCDET1 is transmitted to the first testing circuit output control interface CON1, is that the interlocking of next stage positive and negative extreme value is opened Close and open signal is provided, thus completing the extraction of synchronous electric charge, the wherein first PMOS Mp1 is will be using its parasitic diode The electric charge of the first detection electric capacity C1 memory storage also extracts in inductance.In this forward direction vibration half period, due to the second NMOS tube The level of the grid of Mn2 is identical with the level of the second piezoelectric element connecting interface PZT2, so the second NMOS tube Mn2 is on State, conducting resistance very little, can be equivalent think that the second detection electric capacity C2 is directly in parallel with equivalent capacity inside piezoelectric element, Due to there is not diode drop, extraction second that therefore can be more complete detects the energy in electric capacity C2.

It is more than the second piezoelectric element connecting interface PZT2 voltage in the first piezoelectric element connecting interface PZT1 foot voltage Vpzt1 In the reversal of vibrations half period of Vpzt2, the various pieces working condition change of circuit is as follows：Grid due to the second NMOS tube Mn2 The level of pole is identical with the level of the second piezoelectric element connecting interface PZT2, so the second NMOS tube Mn2 is closed, by There is parasitic diode between the substrate of the second NMOS tube Mn2 and the drain electrode of the second NMOS tube Mn2, when the first piezoelectric element connects The voltage Vpzt1 of connection interface PZT1 exceeds a diode drop than the voltage Vpzt2 of the second piezoelectric element connecting interface PZT2 During VD, this parasitic diode turns on, and the first piezoelectric element connecting interface PZT1 passes through the parasitic diode pair of the second NMOS tube Mn2 Second detection electric capacity C2 charges, and so that the level of the second capacitance detecting interface CDET2 is followed by the increase of Vpzt1 and increase, its electricity Pressure VCDET2=Vpzt1-VD；When piezoelectric element PZT vibrates reverse extreme value place, Vpzt1 reaches maximum, when piezoelectricity unit After the vibrated reverse extreme value place of part PZT, Vpzt1 begins to decline, and VCDET2 keeps constant, when Vpzt1 drops to ratio VCDET2 also will a low PMOS on state threshold voltage Vthp when, Vpzt1=VCDET2-Vthp, the 6th PMOS Mp6 is led Logical, voltage VCDET2 is transmitted to the second testing circuit output control port, provides for next stage positive and negative extreme value interlock switch and open Open signal, thus completing the extraction of synchronous electric charge, the wherein second PMOS Mp2 is will be in the second detection using its parasitic diode The electric charge of electric capacity C2 memory storage also extracts in inductance；In positive extremum extracting module, due to the grid of the first NMOS tube Mn1 Identical with the level of the first piezoelectric element connecting interface PZT1, so the first NMOS tube Mn1 is in the conduction state, conducting resistance is very Little, can be equivalent think that the first detection electric capacity C1 is directly in parallel with equivalent capacity inside piezoelectric element, due to there are not two poles Tube voltage drop is it is possible to more complete extraction first detects the energy in electric capacity C1.

In positive and negative extreme value interlock switch, the 3rd NMOS tube Mn3, the 9th NMOS tube Mn9 and the 8th PMOS Mp8 are one group, the Four NMOS tube Mn4, the tenth NMOS tube Mn10 and the 7th PMOS Mp7 are another group；When positive extremum extracting module just detects To after extreme value, one high level of output to the first testing circuit output control interface CON1, drive the 3rd NMOS tube Mn3, the 9th NMOS tube Mn9 turns on, and the 8th PMOS Mp8 is closed, now because the second testing circuit output control interface CON2 is in drop-down electricity It is always maintained at low level, so the 4th NMOS tube Mn4 and the tenth NMOS tube Mn10 are closed, the 7th PMOS Mp7 is led under resistance effect Logical.The transmission gate that wherein the 9th NMOS tube Mn9 and the 7th PMOS Mp7 are constituted simultaneously turns on, and solves NMOS tube in transmission the The loss of voltage problem during low-voltage of two piezoelectric element connecting interfaces PZT2；When reverse extremum extracting module detects reversed pole After value, one high level of output, to the second testing circuit output control interface CON2, drives the 4th NMOS tube Mn4, the tenth NMOS Pipe Mn10 turns on, and the 7th PMOS Mp7 is closed, now because the first testing circuit output control interface CON1 is in pull down resistor It is always maintained at low level under effect, so the 3rd NMOS tube Mn3, the 9th NMOS tube Mn9 are closed, the 8th PMOS Mp8 conducting.Its In the transmission gate that constitutes of the tenth NMOS tube Mn10 and the 8th PMOS Mp8 simultaneously turn on, solve NMOS tube in transmission first pressure The loss of voltage problem during low-voltage of electric device connecting interface PZT1.

In both forward and reverse directions vibration automatic transfer switch, the 3rd PMOS Mp3 and the 7th NMOS tube Mn7 are one group, the 4th PMOS Pipe Mp4 and the 8th NMOS tube Mn8 are another group；It is more than the first pressure in the voltage Vpzt2 of the second piezoelectric element connecting interface PZT2 In the positive vibration half period of the voltage Vpzt1 of electric device connecting interface PZT1, when two ends pressure reduction is more than metal-oxide-semiconductor threshold voltage Afterwards, the 3rd PMOS Mp3 and the conducting of the 7th NMOS tube Mn7, the 4th PMOS Mp4 and the cut-off of the 8th NMOS tube Mn8；When in piezoelectricity The voltage Vpzt1 of first piezoelectric element connecting interface PZT1 of element PZT is more than the electricity of the second piezoelectric element connecting interface PZT2 In the reversal of vibrations half period of pressure Vpzt2, after two ends pressure reduction is more than metal-oxide-semiconductor threshold voltage, the 4th PMOS Mp4 and the 8th NMOS tube Mn8 turns on, and the 3rd PMOS Mp3 and the 7th NMOS tube Mn7 are ended.

Integrated circuit is divided into two stages to the extraction process of piezoelectric vibration energy, external inductive interface in each stage The current potential at LPIN and grounding ports GND two ends has height change, in first stage, equivalent within piezoelectric element PZT Electric capacity and inductance L constitute LC resonance, and the voltage of the equivalent capacity within the current potential of grounding ports GND and piezoelectric element PZT is equal, So the level of grounding ports GND is higher than the level of external inductive interface LPIN, the equivalent capacity within as piezoelectric element PZT After the completion of internal charge is extracted, enter second stage, because inductance L will keep original electric current, and original loop disconnects, only Induction electromotive force can be produced and carry out afterflow through sustained diode 1, now the level of external inductive interface LPIN is higher than ground connection The level of port GND；The function of dynamic substrate level selection circuit is to select external inductive interface LPIN and grounding ports all the time A minimum interface of level and IC substrate Sub short circuit in GND, with the NMOS preventing the deep N-well in circuit from being surrounded The substrate of pipe and IC substrate Sub conducting, and cannot individually according to the potential difference on its source electrode and grid come normal work.

After completing LC resonant energy and extract, the first piezoelectric element connecting interface PZT1 and the second piezoelectric element connecting interface The voltage difference at PZT2 two ends has been zero, and the 3rd PMOS Mp3, the 7th NMOS tube Mn7, the 4th PMOS Mp4 and the 8th NMOS tube Mn8 has the presence of parasitic diode, can continue to keep original on and off, make LC resonance continue into OK, the part energy reverse charging in inductance L is returned to inside internal detection electric capacity, as the basic electric charge extracting next time " seed "；Because resonant frequency is more much higher than outside frequency of oscillation, make internal capacitance snap back stored charge, thus quickly complete The state becoming cubicle switch switches, and enters energy accumulation and the extraction process of other half vibration period, increases charge accumulated Time and level height, therefore improve the efficiency of Energy extraction.

Because the first pull down resistor Rdp1 and the usual resistance of the second pull down resistor Rdp2 are larger, and first detection electric capacity C1 and Second detection electric capacity C2 is less interior electric capacity, during practical application, according to the performance of different piezoelectric elements or mechanism, May be referred to the external test circuitry figure shown in Fig. 2 pull down resistor is carried out non-essential resistance in parallel to reduce pull down resistor value, or Person in parallel external detection electric capacity increasing capacitance.

Claims (2)

1. a kind of self-powered CMOS piezoelectric vibration energy harvester is it is characterised in that include the synchronization charge-extraction collection of CMOS piezoelectricity Interface circuit and afterflow accumulator, described CMOS piezoelectricity synchronization charge-extraction acquisition interface circuit adopts integrated circuit form Encapsulation, described CMOS piezoelectricity synchronization charge-extraction acquisition interface circuit is provided with the first testing circuit output control interface, Second testing circuit output control interface, the first piezoelectric element connecting interface, the second piezoelectric element connecting interface, the first electric capacity inspection Survey interface, the second capacitance detecting interface, external inductive interface and grounding ports, the first described piezoelectric element connecting interface is used for It is connected with one end of piezoelectric element, the second described piezoelectric element connecting interface is used for being connected with the other end of piezoelectric element, institute The afterflow accumulator stated includes fly-wheel diode, inductance and storage capacitor, described external inductive interface respectively with described One end connection of the positive pole of fly-wheel diode and described inductance, the described negative pole of fly-wheel diode and described storage capacitor Anode connect, the anode of described storage capacitor is used for external electric equipment is provided voltage, described storage capacitor negative End, the described other end of inductance and described grounding ports are all grounded, and described CMOS piezoelectricity synchronization charge-extraction collection connects Mouth circuit includes positive extremum extracting module, reverse extremum extracting module, positive and negative extreme value interlock switch, both forward and reverse directions vibration automatically Switching switch and dynamic substrate lever selection module, described positive and negative extreme value interlock switch includes the 3rd NMOS tube, the 4th NMOS Pipe, the 9th NMOS tube, the tenth NMOS tube, the 7th PMOS and the 8th PMOS, described both forward and reverse directions vibration automatic switchover is opened Close and include the 7th NMOS tube, the 8th NMOS tube, the 3rd PMOS and the 4th PMOS, described dynamic substrate lever selection module Including the 5th NMOS tube and the 6th NMOS tube, the drain electrode of described the 3rd NMOS tube respectively with described positive extremum extracting module The first signal transmission end, the secondary signal transmission ends of described reverse extremum extracting module, the grid of the 7th described NMOS tube Pole, the described grid of the 4th PMOS, the described source electrode of the tenth NMOS tube, the described drain electrode of the 8th PMOS, described The second piezoelectric element connecting interface and one end of described piezoelectric element connect, the grid of described the 3rd NMOS tube respectively with 3rd signal transmission end of described positive extremum extracting module, the described grid of the 9th NMOS tube, the 8th described PMOS The grid of pipe and described first testing circuit output control interface connect, the described source electrode of the 3rd NMOS tube and described the The drain electrode of three PMOS connects, the grid of described the 3rd PMOS respectively with the first described piezoelectric element connecting interface, institute The other end of the piezoelectric element stated, the described source electrode of the 9th NMOS tube, the described drain electrode of the 7th PMOS, described forward direction The secondary signal transmission ends of extremum extracting module, the described drain electrode of the 4th NMOS tube, described reverse extremum extracting module The grid of the first signal transmission end and the 8th described NMOS tube connects, the source electrode of described the 3rd PMOS respectively with described The grid of the 5th NMOS tube, the source of described grounding ports, the described drain electrode of the 6th NMOS tube and the 4th described PMOS Pole connects, grid the 3rd signal transmission end, the institute with described reverse extremum extracting module respectively of described the 4th NMOS tube The grid of the second testing circuit output control interface, the described grid of the tenth NMOS tube and the 7th described PMOS stated is even Connect, the described source electrode of the 4th NMOS tube is connected with the drain electrode of the 4th described PMOS, the source electrode of described the 5th NMOS tube The IC substrate and the described the 6th being located with described CMOS piezoelectricity synchronization charge-extraction acquisition interface circuit respectively The source electrode of NMOS tube connects, the drain electrode of described the 5th NMOS tube respectively with described external inductive interface, the described the 7th The source electrode of the source electrode of NMOS tube, the described grid of the 6th NMOS tube and the 8th described NMOS tube connects, and the described 7th The drain electrode of NMOS tube is connected with the drain electrode of the 9th described NMOS tube and the source electrode of the 7th described PMOS respectively, and described The drain electrode of eight NMOS tube is connected with the source electrode of the 8th described PMOS and the drain electrode of the tenth described NMOS tube respectively, described 4th signal transmission end of positive extremum extracting circuit is connected with the first described capacitance detecting interface, and described reverse extreme value is examined 4th signal transmission end of slowdown monitoring circuit is connected with the second described capacitance detecting interface, the described substrate of the 3rd NMOS tube, institute The substrate of the 4th NMOS tube stated, the described substrate of the 7th NMOS tube, the described substrate of the 8th NMOS tube, the described the 9th The substrate of the substrate of NMOS tube and the tenth described NMOS tube is all isolated with described IC substrate using deep N-well technique.

2. a kind of self-powered CMOS piezoelectric vibration energy harvester according to claim 1 it is characterised in that described just Include the first NMOS tube, the first PMOS, the 5th PMOS, the first detection electric capacity and the first drop-down electricity to extremum extracting module Resistance, described reverse extremum extracting module include the second NMOS tube, the second PMOS, the 6th PMOS, second detection electric capacity and Second pull down resistor, the source electrode of described the first NMOS tube respectively with the source electrode of the first described PMOS, the described the 5th The grid of PMOS, the described drain electrode of the 3rd NMOS tube, the described grid of the second NMOS tube and the described second detection electricity The one end holding connects, the grid of described the first NMOS tube respectively with one end of the first described detection electric capacity, described first Piezoelectric element connecting interface, the described source electrode of the second NMOS tube, the described source electrode of the second PMOS and the described the 6th The grid of PMOS connects, the drain electrode of described the first NMOS tube respectively with the grid of the first described PMOS, described the The drain electrode of one PMOS, the described source electrode of the 5th PMOS, described first detection electric capacity the other end, described second The source electrode of NMOS tube and described first capacitance detecting interface connect, and the drain electrode of described the 5th PMOS is respectively with described the One end of one testing circuit output control interface and the first described pull down resistor connects, described the first pull down resistor another End is connected with described grounding ports, drain electrode grid, the institute with the second described PMOS respectively of described the second NMOS tube The drain electrode of the second PMOS stated, the described source electrode of the 6th PMOS, the other end of the described second detection electric capacity and described The second capacitance detecting interface connect, the drain electrode of described the 6th PMOS respectively with the second described testing circuit output control One end connection of interface and the second described pull down resistor, the described other end of the second pull down resistor and described grounding ports Connect, the substrate of the described substrate of the first NMOS tube and the second described NMOS tube is all using deep N-well technique and described collection Become circuitry substrate isolation.