CN104916758A - 形成发光二极管封装的方法 - Google Patents
形成发光二极管封装的方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 22
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 239000000463 material Substances 0.000 claims abstract description 24
- 239000013078 crystal Substances 0.000 claims description 37
- 239000002245 particle Substances 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 239000011521 glass Substances 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 239000004411 aluminium Substances 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229920003192 poly(bis maleimide) Polymers 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- -1 pottery Substances 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 claims description 2
- 239000000956 alloy Substances 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 claims description 2
- 239000003365 glass fiber Substances 0.000 claims description 2
- 239000004033 plastic Substances 0.000 claims description 2
- 229920003023 plastic Polymers 0.000 claims description 2
- 238000007747 plating Methods 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 239000011347 resin Substances 0.000 claims description 2
- 238000005538 encapsulation Methods 0.000 description 12
- 238000012856 packing Methods 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910052594 sapphire Inorganic materials 0.000 description 4
- 239000010980 sapphire Substances 0.000 description 4
- 238000001816 cooling Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 229910017083 AlN Inorganic materials 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004020 luminiscence type Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000004575 stone Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005246 galvanizing Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L33/58—Optical field-shaping elements
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- H01L2224/24105—Connecting bonding areas at different heights
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- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/24246—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
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- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/2499—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids
- H01L2224/24996—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/24998—Reinforcing structures, e.g. ramp-like support
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/732—Location after the connecting process
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Abstract
本发明公开了一种形成发光二极管封装的方法,包括提供具有一第一导电型通孔结构及一第二导电型通孔结构形成于其中的一基板。于上述基板的一上表面上形成一反射层。提供具有一第一导电型焊垫及一第二导电型焊垫的一发光二极管晶粒,上述第一导电型焊垫及上述第二导电型焊垫分别形成于上述发光二极管晶粒的一下表面及一上表面上。将上述发光二极管晶粒黏着于上述基板上。于邻近上述发光二极管晶粒的至少一侧形成一介电层的倾斜结构,用以支撑导电线路。于上述倾斜结构的上表面上形成一重布层导电线路,以在上述第二导电型焊垫与上述第二导电型通孔结构之间提供路径。
Description
技术领域
本发明涉及一种制程方法,尤其涉及一种形成发光二极管封装的方法。
背景技术
高效能集成电路的封装在本领域中广为人知。工业需求驱动了集成电路封装的改进,以求达到更高的散热及电性表现,与更小之尺寸及更少之制造成本。在发光二极管组件的领域中,发光二极管需要如集成电路组件般进行封装。随着组件尺寸不断地缩小,晶粒密度也不断地提高。在如此之高密度组件中封装的技术需求也必须要提高以满足上述情况。传统上,在覆晶连接方法(flip-chipattachment method)中,一焊锡凸块数组形成于晶粒的表面上。上述焊锡凸块的形成可以通过使用一焊锡复合材料(solder composite material),经过一阻焊屏蔽(solder mask)来制造出所要的焊锡凸块图案。芯片封装的功能包含功率散布(power distribution)、讯号散布(signal distribution)、散热(heatdissipation)、保护与支撑等等。当半导体变的更复杂,传统的封装技术,例如导线架封装(lead frame package)、软性封装(flex package)、刚性封装技术(rigid package technique),已无法满足在一个更小的芯片上制造高密度组件的需求。
上述封装可具有一核芯,其由一常见材料例如玻璃纤维环氧树脂(glassepoxy)所制成,且可具有附加的层堆栈至核芯上。金属或导电层中可透过不同的蚀刻程序例如湿蚀刻建立图样,上述湿蚀刻在本领域为广为人知故此处不进一步叙述。输入、输出功能一般利用多个层之间的金属导线达成。每一导线通过其在封装上的几何关系及位置予以产生。由于制造技术与材料要求,具有堆栈层的封装通常在金属层中包括数个排气孔。排气孔得以允许气体在封装制程期间被蒸发,藉此不会有气泡形成于封装中。导线可安排于排气孔的上方或下方或邻近排气孔或以上的组合。由于上述导线并非位于封装上的同一位置,且会通过金属层中的排气孔所造成的若干个非金属区域,故上述导线会具有阻抗变化或不匹配。这些附加层亦称为「堆栈」层。这些堆栈层一般从介电材料及导电材料的交替层所形成。
伊贝森公开了一种发光二极管封装,标题为「用于封装发光组件之芯片级方法以及经芯片尺寸封装的发光组件」。经封装的发光组件包括具有上表面及下表面的承载基板、从基板上表面延伸到基板下表面的第一和第二导电通孔以及位于基板上表面上且与第一导电通孔电性接触的接合垫。具有第一和第二电极的二极管安装于接合垫上,第一电极与接合垫相电性接触。在二极管上形成有钝化层,以暴露二极管的第二电极。于承载基板的上表面上形成有导电线路,以与第二导电通孔和第二电极电性接触。导电线路在钝化层上并延伸穿过钝化层,以接触第二电极。封装发光组件之方法包括提供包括成长基板和成长基板上的磊晶结构的磊晶圆,将承载基板接合到磊晶圆的磊晶结构,形成通过承载基板的多个导电通孔,在磊晶结构中定义多个隔离的二极管,以及将至少一导电通孔电性连接到多个隔离的二极管中相应的二极管。
然而,上述封装太厚且结构亦过于复杂。
发明内容
本发明的目的在于提供一种具有倾斜结构的发光二极管封装。本发明提供具有P型、N型通孔的发光二极管结构,上述P型、N型通孔从上表面形成至下表面,藉此改善效率及缩小组件尺寸。
为达到上述目的,本发明采用以下技术方案:
一种发光二极管封装包括基板,具有贯穿该基板的第一导电型通孔及第二导电型通孔;反射层,形成于上述基板的上表面上;发光二极管晶粒,上述发光二极管晶粒具有第一导电型焊垫及第二导电型焊垫,其中上述第一导电型焊垫与上述第一导电型通孔相对准;倾斜结构,其由介电层形成,且形成于邻近上述发光二极管晶粒的至少一侧,用以支撑导电线路;导电线路,形成于上述倾斜结构的上表面上,以在上述第二导电型焊垫与上述第二导电型通孔之间提供路径;以及填充材料,形成于上述第一导电型通孔及上述第二导电型通孔之内。
上述发光二极管封装更包括透镜,形成于基板的上表面上,以覆盖发光二极管晶粒。上述发光二极管封装更包括第一导电型终端垫,上述第一导电型终端垫在上述基板下方且耦合至上述第一导电型焊垫;以及第二导电型终端垫,上述第二导电型终端垫在上述基板下方且耦合至上述第二导电型焊垫。上述发光二极管晶粒包括P/N膜,形成于上述发光二极管晶粒基板之上。上述反射层包括有机膜、金属或合金;其中上述反射层通过溅镀或电镀银、铝或金而形成。上述基板的材料包括蓝宝石、硅、碳化硅或氮化铝。上述透镜具有荧光粉材料于其中。上述填充材料为铝、钛、铜、镍或银。上述填充材料为铜和镍和金。
于另一观点中,本发明提出一种形成发光二极管封装的方法,包括提供具有一第一导电型通孔结构及一第二导电型通孔结构形成于其中的一基板。于上述基板的一上表面上形成一反射层。提供具有一第一导电型焊垫及一第二导电型焊垫的一发光二极管晶粒,上述第一导电型焊垫及上述第二导电型焊垫分别形成于上述发光二极管晶粒的一下表面及一上表面上。将上述发光二极管晶粒黏着于上述基板上。在0.1至0.01托的真空及温度为摄氏70至110度的情况下形成一干膜于上述发光二极管晶粒的上方,上述干膜利用弹性特性流动至上述发光二极管晶粒的边缘以填满邻近上述发光二极管晶粒的倾斜区域,用以形成一倾斜结构。通过溅镀或电镀铜和镍和金于上述倾斜结构的上表面上形成一重布层导电线路,以在上述发光二极管晶粒的上述第二导电型焊垫与上述基板的上述第二导电型通孔结构之间提供路径。
附图说明
图1根据本发明显示发光二极管芯片的横切面示意图。
图2根据本发明显示发光二极管芯片组件的横切面示意图。
主要组件符号说明:
10发光二极管封装 100基板 102通孔 104通孔
106散热垫或终端垫 108散热垫或终端垫 110黏着层 112反射层
114第二导电型(P型或N型)焊垫 116发光二极管组件 118 P/N膜 122倾斜结构
120第一导电型(P型或N型)焊垫 124导电线路 126金属焊垫 130透镜
具体实施方式
本发明将以本发明的较佳实施例及后附图式加以详细描述。然而,本领域中具通常知识者应得以领会,本发明的较佳实施例用以说明之用。除此处所述的较佳实施例以外,本发明亦可广泛施行于其它不同的实施例中。本发明的范围除了前附权利要求书所指定之外在文义上并不受限制。如图1所示,本发明发光二极管封装组件,包括发光二极管晶粒、导电线路以及金属互连结构。本发明的概念亦可应用至集成电路封装,特别是用于功率组件。
图1为发光二极管封装10的横切面示意图,上述发光二极管封装10具有基板100,基板100包括形成于其中的预定通孔102及104。基板100的材料可为金属、玻璃、陶瓷、硅、塑料、双马来酰亚胺三氮杂苯树脂(BT,BismaleimideTriacine)、玻璃纤维板(FR4)、耐高温玻璃纤维板(FR5)或聚酰亚胺(Polyimide,PI)等。基板100的厚度约为40至200微米。其可为单层或多层(配线电路(wiringcircuit))基板。反射层112可将晶粒所发射出的光加以反射。故本发明可改善光发射效率。
具有垂直设置的焊垫的发光二极管组件116接着通过黏着层110黏着于基板100的上表面上。黏着层110可能仅覆盖芯片尺寸区域。如图1所示,第一导电型(P型或N型)焊垫120及第二导电型(P型或N型)焊垫114分别形成于晶粒116的上表面及下表面上。P型焊垫指用于发光二极管P型导电材料的焊垫,而N型焊垫指用于发光二极管N型导电材料的焊垫。如图1所示,发光二极管组件116从基板100面朝上且允许第一导电型焊垫120及第二导电型焊垫114均可以垂直方式排列。用以发射光线的P/N膜118配置于晶粒116的上表面上。反射导电层112的材料可为银、铜、铝、钛、有机膜及其任意组合。
光阻层(未显示)通过光微影蚀刻程序加以图案化,以在基板100的背侧表面上形成期望的电路图案,用以作为散热垫或终端垫108、106。填充材料形成于通孔102、104之内,以形成导电通孔结构。如图1所示,以填充材料形成的终端垫108、106亦定义于基板的背侧表面上,某些终端垫108、106可连接至填充有填充材料的通孔102、104。在定义导线之后,光阻层通过溶液剥除。沉积用于通孔102、104的填充材料较佳通过本领域所熟知的电镀程序形成。请参照图2,用于发光二极管封装10的透镜130装附于基板100的上表面上,以覆盖整个发光二极管晶粒112及基板100的主要部份。透镜130可能会以含有荧光粉(磷)涂布。
通孔可利用雷射、机械钻孔或蚀刻形成于基板100之内。第二导电型(P型或N型)焊垫114及第一导电型(P型或N型)焊垫120可透过填充有填充材料的通孔102、104耦合至终端垫108、106。如图式所示,填充有填充材料的通孔(亦称为互连结构)102、104耦合至N型、P型焊垫及终端垫108、106。导电线路(未显示)可设置于基板100的下表面或上表面上。本发明可压缩封装尺寸。于一实例中,P型、N型焊垫形成于发光二极管的下表面上。因此,所发射出来的光将完全不会被焊垫106、108所阻挡。通孔102的开口尺寸小于发光二极管晶粒尺寸。发光二极管晶粒一般取放于基板上,且通过工具使晶粒面朝上设置于黏着层110上,接着固化黏着层。
请参照图1及图2,倾斜结构122形成于邻近发光二极管晶粒116的至少一侧,以支撑导电线路。导电线路124形成于倾斜结构122的上表面上,以在第一导电型(P型或N型)焊垫120与互连结构104上的金属焊垫126之间提供较平滑的路径。主动区域指发光二极管的P/N膜118内的区域。发光二极管组件116形成于第二导电型焊垫114之上,而终端垫108通过互连结构102耦合至第二导电型焊垫114。第一导电型焊垫120形成于晶粒116之上,且透过倾斜结构122上方的导电线路124连接于金属焊垫126,再透过互连结构104耦合至终端垫106。此排列及设置可提供较简易且较平滑的发光二极管用讯号迹线,藉此改善组件效能。具有重布层的倾斜结构122可替代习知的接合线结构,以提供较佳的强度且在热应力情况下提供较佳的可靠度。用于倾斜结构的介电层为干膜类型(dry film type),且在真空、高温及接合情况下形成。例如,晶粒厚度可约为100微米,干膜约为35微米。一旦干膜在高度真空及高温情况下形成于晶粒的上方时,则干膜将会利用材料的弹性特性流动至晶粒边缘,迫使干膜填满邻近晶粒的倾斜区域。上述情况如下:真空1E-1至1E-2托(torr);温度约摄氏70至110度。
本发明可利用习知发光二极管,上述习知发光二极管具有蓝宝石(sapphire)基板,上述蓝宝石基板在发光二极管下方可具有或不具有反射层。反射层112将通过溅镀程序或涂布有机膜而形成于基板100的上表面上,藉此可以简易的材料及低成本制造发光二极管封装。通孔及终端垫中的填充材料可提供较短距离以用于讯号传输及较佳的热导率。所发射出的光可从发光二极管完全地辐射出来,并达到较少的反射损失。散热金属垫易于形成;其提供最低的热阻。另则,填充材料可以溅镀、电镀铜/镍/金而形成。发光二极管晶粒116具有垂直设置的焊垫,发光二极管的基板的材料可为硅、碳化硅、氮化铝等。发光二极管晶粒于BT基板上面朝上,重布层形成于两侧(顶侧及底侧)。BT基板具有导电通孔及及接触金属垫。
以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本发明的保护范围之内。因此,本发明的保护范围应所述以权利要求的保护范围为准。
Claims (11)
1.一种形成发光二极管封装的方法,其特征在于,包括:
提供具有一第一导电型通孔结构及一第二导电型通孔结构形成于其中的一基板;
于该基板的一上表面上形成一反射层;
提供具有一第一导电型焊垫及一第二导电型焊垫的一发光二极管晶粒,该第一导电型焊垫及第二导电型焊垫分别形成于发光二极管晶粒的一下表面及一上表面上;
将该发光二极管晶粒黏着于基板上;
在0.1至0.01托的真空及温度为摄氏70至110度的情况下形成一干膜于发光二极管晶粒的上方,干膜利用弹性特性流动至发光二极管晶粒的边缘以填满邻近该发光二极管晶粒的倾斜区域,用以形成一倾斜结构;以及
通过溅镀及电镀于倾斜结构的上表面上形成一重布层导电线路,以在发光二极管晶粒的第二导电型焊垫与基板的第二导电型通孔结构之间提供路径。
2.根据权利要求1所述的形成发光二极管封装的方法,其特征在于,还包括在该第一导电型通孔结构上形成一金属焊垫,以电性连接重布层导电线路。
3.根据权利要求1所述的形成发光二极管封装的方法,其特征在于,还包括于基板的上表面上形成一透镜,以覆盖发光二极管晶粒。
4.根据权利要求1所述的形成发光二极管封装的方法,其特征在于,还包括在基板下方形成一第一导电型终端垫,以耦合至第一导电型焊垫;以及在基板下方形成一第二导电型终端垫,以耦合至第二导电型焊垫。
5.根据权利要求1所述的形成发光二极管封装的方法,其特征在于,还包含于发光二极管晶粒基板之上形成一PN膜。
6.根据权利要求1所述的形成发光二极管封装的方法,其特征在于,其中反射层包括有机膜、金属或合金。
7.根据权利要求6所述的形成发光二极管封装的方法,其特征在于,其中反射层包含银、铝或金。
8.根据权利要求1所述的形成发光二极管封装的方法,其特征在于,其中基板的材料包括金属、玻璃、陶瓷、硅、塑料、双马来酰亚胺三氮杂苯树脂、玻璃纤维板、耐高温玻璃纤维板或聚酰亚胺。
9.根据权利要求1所述的形成发光二极管封装的方法,其特征在于,其中于基板的一上表面上形成一反射层的步骤是通过一溅镀程序或涂布一有机膜来实施。
10.根据权利要求1所述的形成发光二极管封装的方法,其特征在于,其中第一导电型通孔结构及第二导电型通孔结构是通过溅镀或电镀来形成。
11.根据权利要求1所述的形成发光二极管封装的方法,其特征在于,其中重布层导电线路的材料包含铜、镍和金。
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DE102014116079A1 (de) * | 2014-11-04 | 2016-05-04 | Osram Opto Semiconductors Gmbh | Optoelektronisches Bauelement und Verfahren zu seiner Herstellung |
US11158775B2 (en) * | 2018-06-08 | 2021-10-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
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JP2994219B2 (ja) * | 1994-05-24 | 1999-12-27 | シャープ株式会社 | 半導体デバイスの製造方法 |
US7880182B2 (en) * | 2002-07-15 | 2011-02-01 | Epistar Corporation | Light-emitting element array |
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DE102006042774A1 (de) * | 2006-09-12 | 2008-03-27 | Qimonda Ag | Verfahren zur Herstellung einer elektrischen Ankontaktierung |
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TWI505428B (zh) * | 2010-03-11 | 2015-10-21 | Xintec Inc | 晶片封裝體及其形成方法 |
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2012
- 2012-01-12 US US13/348,787 patent/US20130181227A1/en not_active Abandoned
- 2012-12-28 TW TW101151144A patent/TWI482321B/zh not_active IP Right Cessation
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2013
- 2013-01-08 CN CN201510239822.XA patent/CN104916758A/zh active Pending
- 2013-01-08 CN CN2013100070141A patent/CN103208584A/zh active Pending
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- 2014-12-10 US US14/566,178 patent/US20150099319A1/en not_active Abandoned
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US20080191237A1 (en) * | 2005-08-04 | 2008-08-14 | Cree, Inc. | Submounts for semiconductor light emitting devices and methods of forming packaged light emitting devices including dispensed encapsulants |
CN101060159A (zh) * | 2006-04-21 | 2007-10-24 | 三星电机株式会社 | 具有多阶梯反射表面结构的发光二极管封装及其制造方法 |
US20100163904A1 (en) * | 2008-12-29 | 2010-07-01 | Lg Innotek Co., Ltd. | Semiconductor light-emitting device and light-emitting device package having the same |
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TWI482321B (zh) | 2015-04-21 |
US20150099319A1 (en) | 2015-04-09 |
TW201427116A (zh) | 2014-07-01 |
CN103208584A (zh) | 2013-07-17 |
US20130181227A1 (en) | 2013-07-18 |
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