CN104916614A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN104916614A
CN104916614A CN201410371309.1A CN201410371309A CN104916614A CN 104916614 A CN104916614 A CN 104916614A CN 201410371309 A CN201410371309 A CN 201410371309A CN 104916614 A CN104916614 A CN 104916614A
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China
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mentioned
junction surface
semiconductor chip
semiconductor device
connector
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CN201410371309.1A
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English (en)
Inventor
福井刚
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Toshiba Corp
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Toshiba Corp
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Publication of CN104916614A publication Critical patent/CN104916614A/zh
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Abstract

本发明提供一种可实现可靠性的提高及导通电阻的降低的半导体装置及其制造方法。本实施方式的半导体装置具备半导体芯片、金属制的引线框、树脂制的密封部和金属制的连接器。半导体芯片具有表面电极。引线框具有搭载半导体芯片的第1部分和与第1部分分离地设置的第2部分。密封部以将半导体芯片覆盖的方式形成。连接器具有与半导体芯片的表面接合的第1接合部、与引线框的第2部分的表面接合的平板状的第2接合部、和将第1接合部与第2接合部之间连结的连结部。第2接合部相对于引线框的第2部分垂直地接合。

Description

半导体装置及其制造方法
相关申请的交叉引用
本申请主张以日本专利申请2014－49436号(申请日：2014年3月12日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式涉及半导体装置及其制造方法。
背景技术
在将半导体芯片和引线框通过连接器电连接而得到的以往的半导体装置中，当通过回流(reflow)处理来接合连接器时，由于熔融后的焊料的浮力而存在发生连接器的位置偏移及倾斜这样的问题。连接器的位置偏移及倾斜会导致裂纹的发生、成品率的降低、连接器与树脂的剥离、以及各种可靠性的降低等问题。
此外，在以往的半导体装置中，半导体芯片及将半导体芯片和引线框连接的连接端子(金属线或连接器)整体被绝缘性的树脂覆盖。在这样的以往的半导体装置中，由于经由与金属相比热传导率低的树脂进行散热，因此难以将半导体芯片所发生的热充分地散热。例如，如车载用或产业用的半导体装置那样，在使用时流过大电流的半导体装置中，半导体芯片发生的热增大而成为问题。
发明内容
本发明提供一种可实现可靠性的提高以及导通电阻的降低的半导体装置及其制造方法。
本实施方式的半导体装置具备半导体芯片、金属制的引线框、树脂制的密封部和金属制的连接器。半导体芯片具有表面电极。引线框具有搭载半导体芯片的第1部分和与第1部分分离地设置的第2部分。密封部以将半导体芯片覆盖的方式形成。连接器具有与半导体芯片的表面接合的第1接合部、与引线框的第2部分的表面接合的平板状的第2接合部、和将第1接合部与第2接合部之间连结的连结部。第2接合部相对于引线框的第2部分垂直地接合。
附图说明
图1是表示第1实施方式的半导体装置的概略构成图。
图2是表示第1实施方式的半导体装置的其它例的概略构成图。
图3是表示第1实施方式的半导体装置的其它例的概略构成图。
图4是表示第1实施方式的半导体装置的其它例的概略构成图。
图5是表示第1实施方式的半导体装置的其它例的概略构成图。
图6是表示第1实施方式的半导体装置的制造工序的说明图。
图7是表示第2实施方式的半导体装置的概略构成图。
图8是表示第3实施方式的半导体装置的概略构成图。
具体实施方式
以下，对于本发明的实施方式的半导体装置及其制造方法，参照附图进行说明。
(第1实施方式)
首先，参照图1～图5对于第1实施方式的半导体装置进行说明。本实施方式的半导体装置中，半导体芯片1和引线框2通过连接器3电连接，半导体芯片1通过树脂制的密封部4密封。
这里，图1(A)是表示本实施方式的半导体装置的平面图。图1(A)中，省略了将半导体芯片1密封的密封部4。此外，图1(B)是图1(A)的X－X线剖面图。图1(B)中，图示出将半导体芯片1密封的密封部4。图2～图7也是同样的，在平面图中将密封部4省略，在剖面图中图示出密封部4。如图1所示，本实施方式的半导体装置具备半导体芯片1、引线框2、连接器3、密封部4和接合部51、52、53。
半导体芯片1例如在内部具有IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)、功率MOS(Metal Oxide Semiconductor，金属氧化物半导体)晶体管以及功率IC(Integrated Circuit，集成电路)等，并且在表面及背面具有用于对它们进行驱动的电极。在半导体芯片1的表面形成的电极(以下称作“表面电极”)设置于半导体芯片1的表面的整体或一部分。表面电极例如与高压侧电源连接。在半导体芯片1的背面形成的电极(以下称作“背面电极”)设置于半导体芯片1的背面的整体或一部分。背面电极例如与低压侧电源连接。另外，在本说明中，表面表示剖面图中的上侧的面，背面表示剖面图中的下侧的面。半导体芯片1与引线框2的框身(bed)部21接合。
引线框2是将半导体芯片1固定的金属制的板状部件，具备框身部21和接线柱(post)部22、23。如图1(A)所示，框身部21以及接线柱部22、23分别具备用于将半导体芯片1和外部配线连接的外引线24。此外，如图1(B)所示，引线框2的框身部21的背面从密封部4露出。
在框身部21(第1部分)的表面，搭载有半导体芯片1。半导体芯片1通过接合部51接合于框身部21的表面。接合部51由导电性的接合剂形成，作为接合剂，例如使用焊料或含银的导电性的树脂。通过导电性的接合部51，将框身部21的表面与半导体芯片1的背面接合，将框身部21与半导体芯片1的背面电极电连接。此外，由此将与框身部21的外引线24连接的外部配线(例如低压侧电源)和半导体芯片1的背面电极电连接。
如上述那样，框身部21由于为金属制所以与树脂相比热传导率高。此外，框身部21的背面从密封部4露出。本实施方式的半导体装置能够经由这样构成的框身部21将半导体芯片1所发生的热散热，因此能够提高半导体装置的散热性。
接线柱部22(第2部分)经由连接器3而与半导体芯片1的表面电极电连接。接线柱部22经由外引线24而与外部配线连接。接线柱部22与框身部21分离地设置。
接线柱部23与半导体芯片1的控制电极电连接。半导体芯片1的控制电极通过与接线柱部23电连接，从而与和接线柱部23的外引线24连接的外部配线(例如控制电路)电连接。半导体芯片1的控制电极和接线柱部23通过金属线或连接器等任意的连接端子电连接。接线柱部23与框身部21以及接线柱部22分离地设置。
另外，框身部21以及接线柱部22、23相互绝缘即可，例如，可以在框身部21与接线柱部22，23之间埋入绝缘性的树脂。
连接器3是用于将半导体芯片1的表面电极与接线柱部22电连接的金属制的板状部件。通过由连接器3将半导体芯片1的表面电极与接线柱部22电连接，从而将半导体芯片1的表面电极与和接线柱部22的外引线24连接的外部配线(例如高压侧电源)电连接。
连接器3例如由铜、镀镍的铜、镀银的铜、镀金的铜、铜合金或者铝等金属材料形成。由此，与由铝、金、铜等金属材料形成的金属线相比，连接器3表现出优良的低导通电阻特性，并且表现出与接合剂之间的高密接性。连接器3具备芯片接合部31、接线柱接合部32和连结部33。
芯片接合部31(第1接合部)的背面通过接合部52而与半导体芯片1的表面接合。接合部52由导电性的接合剂形成，作为接合剂，例如使用焊料或含银的导电性的树脂材料。通过导电性的接合部52，将芯片接合部31与半导体芯片1的表面接合。由此，将芯片接合部31与半导体芯片1的表面电极电连接。
芯片接合部31如图1所示，是平板状，以将半导体芯片1的表面的全部或一部分覆盖的方式配置，在背面、即与半导体芯片1接合的一侧的面形成有多个凸部34。凸部34通过准下料(half blanking)加工等冲压(press)加工形成，俯视形状是矩形。多个凸部34的至少一部分优选配置在不与X方向(图1的X－X线方向)及Y方向(图1的与X－X线垂直的方向)中的各个方向平行的位置。通过这样配置凸部34，后述的回流处理中当接合剂熔融时，凸部34以将半导体芯片1压住的方式起作用，接合部52的高度的偏差被抑制。因而，能够防止连接器3相对于半导体芯片1倾斜地接合。
图1中，优选的是，凸部34的总面积相对于接合面的面积的比例在规定值以下。这是因为，若凸部34的总面积的比例大于规定值，则通过由凸部34引起的空隙的发生或应力的增加，有可能产生导通电阻的增大、接合强度及可靠性的降低等问题。为了避免这样的问题，使凸部34的总面积的比例例如在5％以下。另外，凸部34的数量、形状、配置能够任意设计。
此外，在芯片接合部31的表面，形成至少1个凹部35。图1中，通过用冲压加工形成芯片接合部31的背面的凸部34，从而在凸部34的相反侧的表面形成凹部35。若在芯片接合部31的表面形成凹部35，则通过锚固效应(anchor effect)，芯片接合部31与密封部4的密接强度提高。由此，在回流处理等的热处理时，抑制芯片接合部31与密封部4的剥离，能够降低接合部52所负担的应力。
另外，凹部35可以如图1那样通过冲压加工而与凸部34一体地形成，也可以如图2所示那样，与凸部34分别形成。图2所示的凹部35例如能够通过激光加工等形成。
此外，凹部35也可以如图3所示那样，通过切口加工，形成在芯片接合部31的外周部。无论在哪种情况下，凹部35的数量、形状以及配置都能够任意地设计。
无论在哪种情况下，都优选以使得芯片接合部31的表面的面积大于背面的面积的方式形成凸部34以及凹部35。由此，能够提高芯片接合部31与密封部4的密接强度。
接线柱接合部32(第2接合部)通过接合部53而与引线框2的接线柱部22的表面接合。接合部53由导电性的接合剂形成，作为接合剂，例如使用焊料或含银的导电性的树脂材料。通过导电性的接合部53，将接线柱接合部32与接线柱部22接合，从而将接线柱接合部32与接线柱部22电气连接。
接线柱接合部32形成为相对于芯片接合部31垂直的平板状。即，接线柱接合部32是由金属一体地形成的连接器3中的从连结部33朝向接线柱部22弯曲的平板上的部分。通过将接线柱接合部32的接线柱部22侧的端部与接线柱部22接合，从而将接线柱接合部32与接线柱部22垂直地接合。通过这样的构成，在将接线柱接合部32与接线柱部22接合时，接线柱接合部32所负担的熔融后的接合剂的浮力变小。因而，能够抑制接合部53的厚度的偏差，防止连接器3倾斜地被接合，并且，能够防止通过熔融后的接合剂的浮力而使接线柱接合部32位置偏移。
此外，熔融的接合剂由于爬上接线柱接合部32的侧面而形成倒角(fillet)，因此能够充分确保接线柱接合部32与接线柱部22的接合强度，防止由应力引起的裂纹的发生等。本实施方式中，接合部53的倒角的高度优选在接线柱接合部32的高度的3分之1以上，以使得充分确保接线柱接合部32与接线柱部22的接合强度。
此外，接线柱接合部32如图4所示，优选在与接线柱部22接合的下端部的侧面的至少一部分具有凹部36。凹部36能够通过切口加工等形成。凹部36的长度以及高度能够任意设计，例如形成为，长度为接线柱接合部32的下端部的长度的3分之1，高度为接线柱接合部32的高度的3分之1。通过这样的构成，在将接线柱接合部32与接线柱部22接合时，熔融后的接合剂的浮力进一步变小，因此能够抑制连接器3的倾斜及接线柱接合部32的位置偏移。此外，熔融后的接合剂进入凹部36，接合部53的水平方向的面积变小，因此能够降低接合部53所负担的应力。
连结部33是将芯片接合部31与接线柱接合部32之间连结的部分。连结部33能够形成为可将芯片接合部31与接线柱接合部32连接的任意的形状，如图1所示，连结部33可以形成为与芯片接合部31平行的平板状。
此外，优选在连结部33的表面形成至少1个凹部37。若在连结部33的表面形成凹部37，则通过锚固效应，连结部33与密封部4的密接强度提高。由此，在回流处理等的热处理时，能够抑制连结部33与密封部4之间的剥离。
凹部37可以如图2所示那样通过激光加工形成在连结部33的表面，也可以如图3所示那样通过切口加工形成在连结部33的表面的外周部。此外，凹部37也可以如图5所示那样通过冲切加工以从连结部33的表面贯通到背面的方式形成。无论在哪种情况下，凹部37的数量、形状以及配置都能够任意地设计。
密封部4以将半导体芯片1的整体覆盖的方式形成，保护半导体芯片1不受外力或外气的损害，构成半导体装置的壳体。密封部4以引线框2从背面露出、外引线24从侧面突出的方式通过绝缘性的树脂形成。
如以上说明的那样，本实施方式的半导体装置，由于将平板状的接线柱接合部32与接线柱部22垂直地接合，因此当接合剂熔融时对接线柱接合部32负担的接合剂的浮力变小。由此，将接合部53形成为均匀的厚度，抑制连接器3的倾斜，并且抑制接线柱接合部32的位置偏移。这样，连接器3的倾斜及位置偏移所导致的可靠性降低得以抑制，因此本实施方式的半导体装置具有高可靠性。
此外，本实施方式的半导体装置，半导体芯片1所发生的热经由引线框2的框身部21而散热。框身部21由热传导性高的金属制造，其背面从密封部4露出。因而，本实施方式的半导体装置具有高散热性。通过这样的构成，本实施方式的半导体装置能够作为要求高散热性的具备IGBT、功率MOS晶体管以及功率IC等的功率模块而被适宜地利用。
另外，半导体装置也可以是具备多个半导体芯片的结构。例如，能够应用于具备高电压侧的半导体芯片和低电压侧的半导体芯片、并将2个半导体芯片经由连接器3连接而得到的变换器(inverter)等。
接着，关于本实施方式的半导体装置的制造方法，参照图6进行说明。这里，图6是表示本实施方式的半导体装置的制造方法的说明图，图6(A)～(D)示出了各工序中的半导体装置的剖面图。
首先，在引线框2的框身部21的表面的规定位置，涂敷焊料糊或含银的树脂糊等接合剂，在该接合剂上载置半导体芯片1。然后，通过回流处理将半导体芯片1与框身部21接合。即，在载置了半导体芯片1的状态下进行加热，使接合剂熔融，通过除热使接合剂凝固。由此，形成接合部51，通过接合部51将半导体芯片1与框身部21的表面接合(参照图6(A))。
接着，在半导体芯片1的表面的规定位置以及引线框2的接线柱部22的表面的规定位置，涂敷焊料糊或含银的树脂等接合剂，在该接合剂上载置连接器3(参照图6(B))。然后，通过回流处理将连接器3接合。即，在载置了连接器3的状态下进行加热，使接合剂熔融，通过除热使接合剂凝固。由此，形成接合部52、53，通过接合部52将接线柱接合部32与接线柱部22接合，通过接合部53将芯片接合部31与半导体芯片1的表面接合(参照图6(C))。这时，优选在接合部53形成接线柱接合部32的高度的3分之1以上的高度的倒角。
接着，将图6(C)的状态的半导体装置导入模制模具进行树脂成形。即，以将半导体芯片1的整体覆盖的方式通过绝缘性的树脂进行密封(参照图6(D))。图6(D)中，连接器3、引线框2的框身部21以及接线柱部22、23整体被密封部4覆盖，引线框2的外引线24从密封部4的侧面突出。
例如利用CMP(Chemical Mechanical Polishing：化学机械研磨)法对这样形成的密封部4的背面进行研磨，从而制造图1所示的本实施方式的半导体装置。对密封部4的背面进行研磨，直到引线框2的框身部21的背面的至少一部分露出。
这样，在树脂成形后，通过对密封部4的背面进行研磨，将密封部4平坦化，能够降低密封部4的表面侧及背面侧的应力。由此，能够提高半导体装置的可靠性。此外，也可以通过对密封部4的表面进行研磨，使密封部4平坦化。
如以上说明的那样，根据本实施方式的半导体装置的制造方法，在将平板状的接线柱接合部32相对于接线柱部22垂直地进行载置后，通过回流处理使接合剂熔融，将接线柱接合部32与接线柱部22接合。因而，能够减小回流处理时当接合剂熔融时对接线柱接合部32负担的接合剂的浮力。由此，能够抑制熔融后的接合剂所引起的连接器3的倾斜及位置偏移，提高半导体装置的可靠性。
另外，本实施方式的半导体装置的制造方法中，省略了对引线框2的框身部21涂敷接合剂后的回流处理，能够将该回流处理与用于将连接器3接合的回流处理一并进行。
此外，本实施方式的半导体装置的制造方法中，能够以不通过密封部4将引线框2的背面覆盖的方式进行树脂成形。通过这样的构成，能够削减上述的研磨工序，或者实现简略化。
(第2实施方式)
接着，关于第2实施方式的半导体装置，参照图7进行说明。本实施方式的半导体装置以将引线框2的接线柱部22与连接器3的接线柱接合部32之间的接合面包围的方式形成有防浸润部61。关于其它构成以及制造方法，与第1实施方式相同，因此省略说明。
防浸润部61是以使熔融后的接合剂的浸润性变差(接触角变小)的方式加工而得到的部分，例如能够通过对引线框2的接线柱部22的表面进行激光加工而形成。通过激光加工而在加工部位形成的氧化膜与周围相比，浸润性变差，所以作为防浸润部61发挥功能。
防浸润部61例如以从接合面离开50μm以上并将接合面包围的方式以规定间隔形成。防浸润部61的长度及配置等的设计能够根据接合面的电压特性及面积来任意选择。
根据本实施方式，在用于将接线柱部22与接线柱接合部32接合的回流处理时，熔融后的接合剂向接合面外侧的流动得以抑制，因此能够使对接线柱接合部32进行接合的接合剂的量适量。因而，能够抑制由接合剂的量多或量少引起的半导体元件的可靠性的降低。
(第3实施方式)
接着，关于第3实施方式的半导体装置，参照图8进行说明。本实施方式的半导体装置，在连接器3的芯片接合部31的表面的一部分，具有由密封剂形成的绝缘部38。关于其它构成以及制造方法，与第1实施方式相同，因此省略说明。
绝缘部38通过在芯片接合部31的表面涂敷密封剂而形成。密封剂例如包含单组分热硬化性的硅胶、聚酰亚胺以及聚酰胺中的至少一种。在芯片接合部31的表面，以将绝缘部38的周围包围的方式形成防浸润部62，以使得密封剂流动且不将半导体芯片1覆盖。或者，也可以在芯片接合部31的表面以将绝缘部38的周围包围的方式实施准下料加工。
通过以上的构成，根据本实施方式，通过在芯片接合部31的表面设置绝缘部38，能够提高芯片接合部31的抗湿性，并且，提高芯片接合部31与密封部4的密接强度，能够防止在回流处理等热处理中密封部4从连接器3剥离。此外，由于绝缘部38以不将半导体芯片1覆盖的方式构成，所以能够防止半导体元件动作时以及高温、低温循环(circle)时的铝电极的滑动(Al滑动)。
对本发明的几个实施方式进行了说明，但这些实施方式是作为例子而提示的，并不意欲限定发明的范围。这些新的实施方式能够以其它各种形态实施，在不脱离发明主旨的范围内，能够进行各种省略、替换、变更。这些实施方式及其变形包含在发明的范围及主旨中，并且包含在权利要求所记载的发明及其等同范围内。

Claims (11)

1.一种半导体装置，具备：
半导体芯片，具有表面电极；
金属制的引线框，具有搭载上述半导体芯片的第1部分、和与上述第1部分分离地设置的第2部分；
树脂制的密封部，以将上述半导体芯片覆盖的方式形成；以及
金属制的连接器，具有与上述半导体芯片的表面接合的第1接合部、与上述引线框的上述第2部分的表面接合的平板状的第2接合部、和将上述第1接合部与上述第2接合部之间连结的连结部，上述第2接合部相对于上述引线框的上述第2部分被垂直地接合。
2.如权利要求1记载的半导体装置，
上述第2接合部是由金属一体形成的上述连接器中的、从上述连结部朝向上述第2部分弯曲的平板上的部分，通过将上述第2接合部的上述第2部分侧的端部与上述第2部分接合，将上述第2接合部与上述第2部分垂直地接合。
3.如权利要求1或2记载的半导体装置，
在上述第2部分的表面具备防浸润部，该防浸润部以将上述第2部分与上述第2接合部之间的接合面包围的方式，抑制熔融后的接合剂的浸润。
4.如权利要求3记载的半导体装置，
上述防浸润部由氧化膜形成。
5.如权利要求1或2记载的半导体装置，
上述连接器的第1接合部的背面具有多个凸部。
6.如权利要求1或2记载的半导体装置，
在上述连接器的第2接合部的下端部的侧面的至少一部分形成有凹部。
7.如权利要求1或2记载的半导体装置，
在上述连接器的上述第2接合部的侧面，形成由该第2接合部的高度的3分之1以上的高度的接合剂形成的倒角。
8.如权利要求1或2记载的半导体装置，
在上述连接器的第1接合部以及连结部的至少一方的表面，形成至少1个凹部。
9.如权利要求1或2记载的半导体装置，
在上述连接器的第1接合部的表面的至少一部分具有绝缘部，该绝缘部含有硅、聚酰亚胺以及聚酰胺中的至少一种。
10.如权利要求1或2记载的半导体装置，
上述连接器由铜、镀镍的铜、镀银的铜、镀金的铜、铜合金、或者铝形成。
11.一种半导体装置的制造方法，具备以下步骤：
将具有表面电极的半导体芯片接合到引线框的第1部分的表面；
对上述半导体芯片的表面、和与上述第1部分分离地设置的上述引线框的第2部分的表面涂敷接合剂；
以使金属制的连接器的第2接合部相对于上述引线框的第2部分垂直地接合的方式，通过上述接合剂将上述金属制的连接器与上述半导体芯片和上述引线框接合，上述金属制的连接器具有：与上述半导体芯片的表面接合的第1接合部、与上述引线框的上述第2部分的表面接合的平板状的上述第2接合部、和将上述第1接合部及上述第2接合部之间连结的连结部；以及
以将上述半导体芯片以及上述连接器覆盖的方式通过树脂进行密封。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111902889A (zh) * 2018-03-23 2020-11-06 日本贵弥功株式会社 汇流条叠层板、该汇流条叠层板的电子元件安装模块及汇流条叠层板的制造方法
CN113206049A (zh) * 2020-01-31 2021-08-03 株式会社东芝 半导体装置

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7199639B2 (ja) * 2018-03-23 2023-01-06 日本ケミコン株式会社 バスバー積層体及びそれを備える電子部品実装モジュール、バスバー積層体の製造方法
JP7310571B2 (ja) * 2019-11-28 2023-07-19 株式会社デンソー 半導体装置
JP2023138193A (ja) * 2022-03-19 2023-10-02 株式会社東芝 半導体装置
JP2023139980A (ja) * 2022-03-22 2023-10-04 株式会社東芝 半導体装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1360814A (zh) * 1999-05-27 2002-07-24 理查德·K·威廉斯 功率半导体器件的表面安装封装
CN101213663A (zh) * 2005-06-30 2008-07-02 费查尔德半导体有限公司 半导体管芯封装及其制作方法
US20080233679A1 (en) * 2005-02-15 2008-09-25 Alpha & Omega Semiconductor, Inc. Semiconductor package with plated connection
CN102714201A (zh) * 2010-01-19 2012-10-03 维西埃-硅化物公司 半导体封装和方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI462261B (zh) * 2011-10-28 2014-11-21 Alpha & Omega Semiconductor Cayman Ltd 結合封裝高端及低端晶片之半導體元件及其製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1360814A (zh) * 1999-05-27 2002-07-24 理查德·K·威廉斯 功率半导体器件的表面安装封装
US20080233679A1 (en) * 2005-02-15 2008-09-25 Alpha & Omega Semiconductor, Inc. Semiconductor package with plated connection
CN101213663A (zh) * 2005-06-30 2008-07-02 费查尔德半导体有限公司 半导体管芯封装及其制作方法
CN102714201A (zh) * 2010-01-19 2012-10-03 维西埃-硅化物公司 半导体封装和方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111902889A (zh) * 2018-03-23 2020-11-06 日本贵弥功株式会社 汇流条叠层板、该汇流条叠层板的电子元件安装模块及汇流条叠层板的制造方法
CN111902889B (zh) * 2018-03-23 2022-05-03 日本贵弥功株式会社 汇流条叠层板、该汇流条叠层板的电子元件安装模块及汇流条叠层板的制造方法
CN113206049A (zh) * 2020-01-31 2021-08-03 株式会社东芝 半导体装置

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