CN104914914B - Circuit structure and its control method - Google Patents
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- CN104914914B CN104914914B CN201510231068.5A CN201510231068A CN104914914B CN 104914914 B CN104914914 B CN 104914914B CN 201510231068 A CN201510231068 A CN 201510231068A CN 104914914 B CN104914914 B CN 104914914B
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Abstract
The present invention provides a kind of circuit structure and its control method, including power line, constant-current generating circuit, low pressure difference linear voltage regulator, positive pump circuit, analog circuit and decoupling capacitor, and the analog circuit is connected with the power line with primary nodal point；The constant-current generating circuit is connected with the power line with secondary nodal point, and the input of the constant-current generating circuit connects a reference current；One end of the decoupling capacitor is connected between the primary nodal point and the secondary nodal point, other end ground connection；The constant-current generating circuit is connected with the low pressure difference linear voltage regulator and the positive pump circuit respectively with the 3rd node, and the input of the low pressure difference linear voltage regulator connects a reference voltage.In the present invention, stablizing for secondary nodal point voltage and current is maintained by constant-current generating circuit and low pressure difference linear voltage regulator, reduce impact of the positive pump circuit to the voltage of power line.
Description
Technical field
The present invention relates to IC design technical field, more particularly to a kind of circuit structure and its control method.
Background technology
In the circuit design of imageing sensor, with reference to shown in Fig. 1, generally by positive pump circuit 2 come for imageing sensor battle array
Row (Panel Array) provide a voltage higher than the voltage AVDD of power line 3.Under the excitation of clock signal clk, positive pump
Electric capacity C1, C2 of circuit 2 can carry out periodic charging and discharging, final to produce an output voltage higher than supply voltage
Value, its course of work are as follows：
When the first clock control signal CLK be low level when, second clock control signal CLKb be high level, a NMOS
Transistor MN1 ends, and the second nmos pass transistor MN2 conductings, the cut-off of the first PMOS transistor MP1, the second PMOS transistor MP2 are led
Logical, power line 3 is charged to the second electric capacity C2 by node B, and the first electric capacity C1 is charged to the 3rd electric capacity C3 by node D；Then,
The voltage of the first clock control signal CLK is gradually increasing, and second clock control signal CLKb is gradually reduced, and the second electric capacity C2's is upper
The voltage of pole plate rises, and the voltage of the top crown of the first electric capacity C1 declines so that the gate source voltage of the first nmos pass transistor MN1
Vgs1 rises, and the gate source voltage Vgs2 of the second nmos pass transistor declines, on the gate source voltage Vgsp1 of the first PMOS transistor MP1
Rise, the gate source voltage Vgsp2 of the second PMOS transistor MP2 declines, the second nmos pass transistor MN2 cut-offs, the first nmos pass transistor
MN1 is turned on, and the conducting of the first PMOS transistor MP1, the cut-off of the second PMOS transistor MP2, power line 3 are electric to first by node B
Hold C1 to charge, the charging and discharging currents at node B rise, the second electric capacity C2 charges the 3rd electric capacity C3 by node C；When first
When clock control signal CLK rises to high level voltage, second clock control signal drops to low level, with the first electric capacity C1's
The carrying out charged, the voltage of the top crown of the first electric capacity C1 raise so that under the gate source voltage Vgs1 of the first nmos pass transistor MN1
Drop, the gate source voltage Vgsp1 of the first PMOS transistor MP1 decline, and the gate source voltage Vgsp2 of the second PMOS transistor MP2 rises,
So as to the charging and discharging currents at node B decline；Afterwards, the voltage of the first clock control signal CLK declines, second clock control letter
The voltage of number CLKb rises, and the voltage of the top crown of the second electric capacity C2 declines, and the voltage of the top crown of the first electric capacity C1 rises, the
The gate source voltage Vgs2 of bi-NMOS transistor MN2 rises, and the gate source voltage Vgs1 of the first nmos pass transistor MN1 declines, and first
Nmos pass transistor MN1 ends, the second nmos pass transistor MN2 conductings, the cut-off of the first PMOS transistor MP1, the second PMOS transistor
MP2 is turned on, and node B charges to the second electric capacity C2, and the first electric capacity C1 is charged to the 3rd electric capacity C3 by node C, filling at node B
Discharge current rises；Finally, when the first clock control signal CLK drops to low level, second clock control signal CLKb rises
For high level when, with the charging of the second electric capacity C2, the voltage of the top crown of the second electric capacity C2 rises, transistor seconds MN2's
Grid source current Vgs2 declines, and the charging and discharging currents at node B decline.With the voltage signal week of the first clock control signal CLK
The change of phase property, the also periodically rise and fall of the charging and discharging currents at node B, so as to produce ripple, the voltage at node B with
Change.So as to at node A voltage produce interference, dramatically affect and 1 grade of analog circuit being connected at node A its
The performance of his analog circuit.Meanwhile, the performance of imageing sensor can be impacted, cause the horizontal noise of big image
(Horizontal Noise)。
In existing solution, usually providing a single power supply (I/O Pad) for positive pump circuit 2 makes positive pump electricity
Road 2 does not share power supply with analog circuit 1, reduces the impact produced to analog circuit.Individually power supply can increase cost.Existing skill
Can also be by larger electric capacity of voltage regulation be arranged beside supply voltage AVDD in art, the electric capacity of setting increases the area of chip,
So as to can also increase cost.
The content of the invention
It is an object of the present invention to provide a kind of circuit structure and its control method, weaken positive pump circuit to supply voltage
Interference.
To solve above-mentioned technical problem, the present invention provides a kind of circuit structure, including power line, constant current produce electricity
Road, low pressure difference linear voltage regulator, positive pump circuit, analog circuit and decoupling capacitor, the analog circuit is with primary nodal point and institute
State power line connection；The constant-current generating circuit is connected with the power line with secondary nodal point, and the constant current is produced
The input of circuit connects a reference current；One end of the decoupling capacitor is connected to the primary nodal point and the secondary nodal point
Between, other end ground connection；The constant-current generating circuit with the 3rd node respectively with the low pressure difference linear voltage regulator and institute
Positive pump circuit connection is stated, the input of the low pressure difference linear voltage regulator connects a reference voltage.
Optionally, the positive pump circuit includes：
Negative circuit, the input of the negative circuit connect the first clock control signal, the output of the negative circuit
End connection second clock control signal；
First nmos pass transistor, the drain electrode of first nmos pass transistor connect the 3rd node, and source electrode is with Section five
The outfan of the point connection negative circuit, grid connect the input of the negative circuit with fourth node；
First electric capacity, first capacitances in series is between the 5th node and the outfan of the negative circuit；
Second nmos pass transistor, the drain electrode of second nmos pass transistor connect the 3rd node, and source electrode connection is described
The input of negative circuit, grid connect the 5th node；
Second electric capacity, second capacitances in series is between the input of the fourth node and the negative circuit；
First PMOS transistor, the drain electrode of first PMOS transistor connect the fourth node, and source electrode is with Section six
The positive pump circuit outfan of point connection, grid connect the 5th node；
Second PMOS transistor, the drain electrode of second PMOS transistor connect the 5th node, and source electrode connection is described
6th node, grid connect the fourth node；
3rd electric capacity, the 3rd capacitances in series in one end connect the 6th node, other end ground connection.
Optionally, the frequency of first clock control signal is 20MHz-200MHz.
Optionally, the low pressure difference linear voltage regulator includes：
Amplifier, the amplifier include first input end and the second input, and the first input end of the amplifier connects
Connect the reference voltage；
3rd PMOS transistor, the source electrode of the 3rd PMOS transistor connect the 3rd node, grounded drain, grid
Connect the outfan of the amplifier；
First resistor, the first resistor are series between the second input of the amplifier and the 3rd node；
Second resistance, the second resistance are series between the second input of the amplifier and ground terminal.
Optionally, the size of the reference voltage is 1.2V-1.4V.
Optionally, the constant-current generating circuit includes：
4th PMOS transistor, the source electrode of the 4th PMOS transistor connect the secondary nodal point, and drain and gate connects
Connect the reference current；
Mirrored transistor string, the mirrored transistor string respectively with the secondary nodal point, the 3rd node and the described 4th
The grid connection of PMOS transistor.
Optionally, the mirrored transistor string includes at least three PMOS transistors of parallel connection.
Optionally, the source electrode of at least three PMOS transistors in parallel is all connected with the secondary nodal point, and grid is all connected with institute
The grid of the 4th PMOS transistor is stated, drain electrode is all connected with the 3rd node.
Optionally, the size of the reference current is 10 μ A-20 μ A.
Accordingly, the present invention also provides a kind of control method of above-mentioned circuit structure, including：
The reference voltage is provided to the low pressure difference linear voltage regulator, the 3rd node exports a constant voltage, institute
Stating constant voltage is supplied to the constant-current generating circuit and the positive pump circuit, the positive pump circuit to fill with a change
Discharge current；
The reference current is provided to the constant-current generating circuit, the constant-current generating circuit is in the 3rd node
Produce a constant output current, maximum of the constant output current more than the charging and discharging currents；
The constant output current more than the charging and discharging currents portion of electrical current be residual current, the residual current by
The low pressure difference linear voltage regulator absorbs, and power line is supplied to the current constant of the secondary nodal point.
Circuit structure and its control method that the present invention is provided, low pressure difference linear voltage regulator produce a constant voltage,
In the positive pump circuit of constant-current generating circuit one ratio of generation, the big constant current of maximum charging and discharging currents gives positive pump circuit, greatly
Absorbed by low pressure difference linear voltage regulator in the portion of electrical current of positive pump circuit charging and discharging currents so that the electric current of the 3rd node, voltage
It is constant, the electric current and voltage constant of the secondary nodal point being connected with constant-current generating circuit so as to power line, it is to avoid positive pump electricity
Impact of the current ripples to the voltage of power line in road.
Description of the drawings
Fig. 1 is the circuit diagram including positive pump circuit of the prior art；
Fig. 2 is the schematic diagram of circuit structure in the present invention；
Fig. 3 is the schematic diagram of circuit structure in one embodiment of the invention；
Fig. 4 is the flow chart of circuit structure control method in one embodiment of the invention.
Specific embodiment
The circuit structure and its control method of the present invention are described in more detail below in conjunction with schematic diagram, wherein table
Show the preferred embodiments of the present invention, it should be appreciated that those skilled in the art can change invention described herein, and still
Realize the advantageous effects of the present invention.Therefore, description below be appreciated that it is widely known for those skilled in the art, and
It is not intended as limitation of the present invention.
The core concept of the present invention is first, low pressure difference linear voltage regulator to be carried out according to the voltage condition of power line
Configuration so that the lower voltage of low pressure difference linear voltage regulator producing ratio power line voltage is supplied to constant-current generating circuit to make
For the outfan of its constant output current, and as the supply voltage of positive pump circuit.The electric current of positive pump circuit can be with positive pump electricity
The charge status of the size, loading condition and coupled capacitor itself of the supply voltage on road periodically change.According to positive pump
The current conditions of circuit are configured to constant-current generating circuit again so that constant-current generating circuit generation one is constant defeated
Go out electric current, the maximum of offer required under particular power source voltage and loading condition that the constant output current is greater than positive pump circuit
Source current.Constant output current is absorbed by low pressure difference linear voltage regulator more than the part electric current of positive pump circuit electric current, permanent
Determine output current to be then held essentially constant, the output voltage that low pressure difference linear voltage regulator is provided also is held essentially constant, power line
It is supplied to the electric current of secondary nodal point also be held essentially constant, interference of the so positive pump circuit to power line is also just greatly reduced
.
The control method of the circuit structure and circuit structure of the present invention is carried out specifically below in conjunction with Fig. 2, Fig. 3 and Fig. 4
Explanation.
With reference to shown in Fig. 2, the circuit structure that the present invention is provided, including：It is power line 30, constant-current generating circuit 50, low
Pressure reduction linear voltage regulator 40, positive pump circuit 20, analog circuit 10 and decoupling capacitor C0, the analog circuit 10 is with primary nodal point
N1 is connected with the power line 30；The constant-current generating circuit 50 is connected with the power line 30 with secondary nodal point B, described
The input of constant-current generating circuit 30 connects a reference current Iref；Described decoupling capacitor C0 one end is connected to described first
Between node N1 and the secondary nodal point N2, the other end ground connection of the decoupling capacitor C0；The constant current produces electric current 50
It is connected with the low pressure difference linear voltage regulator 40 and the positive pump circuit 20 with the 3rd node N3 respectively, the low pressure difference linearity is steady
The input of depressor 40 connects a reference voltage Vref.
With continued reference to shown in Fig. 2, the positive pump circuit 20 includes：
Negative circuit 21, the input of the negative circuit 21 connect the first clock control signal CLK, outfan connection the
The frequency of two clock control signal CLKb, the first clock control signal CLK is 20-MHz 200MHz；
The drain electrode of the first nmos pass transistor MN1, the first nmos pass transistor MN1 connects the 3rd node, source electrode with
5th node connects the outfan of the negative circuit 21, and grid connects the input of the negative circuit 21 with fourth node；
First electric capacity C1, the first electric capacity C1 are series at the outfan of the 5th node N5 and the negative circuit 21
Between；
The drain electrode of the second nmos pass transistor MN2, the second nmos pass transistor MN2 connects the 3rd node N3, source electrode
Connect the input of the negative circuit 21, grid connects the 5th node N5；
Second electric capacity C2, the second electric capacity C2 are series at the input of fourth node N4 and the negative circuit 21
Between；
First PMOS transistor MP1, the drain electrode of first PMOS transistor MP1 connect fourth node N4, source electrode
Positive pump circuit outfan VOUT is connected with the 6th node N6, grid connects the 5th node N5；
Second PMOS transistor MP2, the drain electrode of second PMOS transistor MP2 connect the 5th node N5, source electrode
Connect the 6th node N6, grid connects fourth node N4；
One end of 3rd electric capacity C3, the 3rd electric capacity C3 connects the 6th node N6, and the 3rd electric capacity C3's is another
One end is grounded.
With reference to shown in Fig. 3, the low pressure difference linear voltage regulator 40 includes：
Amplifier 41, the amplifier 41 include first input end 411 and the second input 412, the amplifier 41
First input end 411 connects the reference voltage Vref；
3rd PMOS transistor MP3, the source electrode of the 3rd PMOS transistor MP3 connect the 3rd node N3, drain electrode
Ground connection, grid connect the outfan of the amplifier 41；
First resistor R1, first resistor R1 are connected to second input 412 and the described 3rd of the amplifier 41
Between node N3；
Second resistance R2, second resistance R2 are connected to second input 412 and ground terminal of the amplifier 41.
With continued reference to shown in Fig. 3, the constant-current generating circuit 50 includes：
4th PMOS transistor MP4, the source electrode of the 4th PMOS transistor MP4 connect the secondary nodal point N2, drain electrode
Connect the reference current Iref with grid；
Mirrored transistor string 51, the mirrored transistor string 51 respectively with the secondary nodal point N2, the 3rd node N3 and institute
The grid connection of the 4th PMOS transistor MP4 is stated, the mirrored transistor string 51 includes at least three PMOS transistors of parallel connection,
The source electrode of the transistor of at least three PMOS in parallel is all connected with the secondary nodal point N2, and it is brilliant that grid is all connected with the 4th PMOS
The grid of body pipe MP4, drain electrode are all connected with the 3rd node N3, PMOS transistor in parallel by outside register controlled, from
And control the output current of constant-current generating circuit 50.
Accordingly, the present invention also provides a kind of control method of circuit structure, with reference to shown in Fig. 4, comprises the steps：
First, execution step S1, configures to low pressure difference linear voltage regulator 40 according to the voltage condition of power line 30, choosing
A suitable reference voltage Vref is selected, the size of the reference voltage Vref is 1.2V-1.4V, and reference voltage Vref is by outside
Circuit is provided.By the amplifier 41 inside low pressure difference linear voltage regulator 40, and first resistor R1 and second resistance R2 is negative
Feedback, lower constant voltage Vcp of low pressure difference linear voltage regulator 40 producing ratio power line, 30 voltages, constant voltage Vcp=R1
× (R1+R2)/R2, constant voltage Vcp is supplied to constant-current generating circuit 50 as the outfan of its constant output current,
And as the supply voltage of positive pump circuit 20.
Secondly, execution step S2, when the supply voltage of positive pump circuit 20 is Vcp, the charging and discharging currents of positive pump circuit 20
For Icp, Icp can be with the first electric capacity C1 of the loading condition of positive pump circuit 20 and itself coupling, the charge and discharge of the second electric capacity C2
Electric situation periodically changes, and the charging and discharging currents Icp maximums for making positive pump circuit 20 are Icp_max.
Again, execution step S3, matches somebody with somebody to constant-current generating circuit 50 again according to the current conditions of positive pump circuit 20
When putting, according to the reference current Iref and the electric current Icp for being supplied to positive pump circuit of input, perseverance is caused through mirrored transistor string 51
Determine current generating circuit 50 and produce a constant output current Iconst, the size of the reference current Iref is 10 μ A-20 μ A,
The size of constant output current Iconst is 1mA-2mA.In the present embodiment, constant output current Iconst is greater than and is supplied to
The maximum charging and discharging currents Icp_max of positive pump circuit 20.Part of the constant output current Iconst more than charging and discharging currents Icp
Electric current is residual current Ireg, and residual current Ireg absorbed by low pressure difference linear voltage regulator 40, wherein, first resistor R1, the
One part of current can be consumed on two resistance R2, the size of this portion of electrical current is mainly by Vcp and first resistor R1, second resistance R2
Determining, another part electric current then has the 3rd PMOS transistor MP1 of rectifier tube of inside to absorb the size of resistance value, MP1
The electric current of upper absorption then can change as the charging and discharging currents Icp for being supplied to positive pump circuit 20 changes, therefore, constant current is produced
The constant output current Iconst that raw circuit 50 is provided is held essentially constant, the output voltage that low pressure difference linear voltage regulator 40 is provided
Vcp is also held essentially constant.As Iconst is held essentially constant, power line 30 is supplied to the electric current of secondary nodal point N2
Isupply is also held essentially constant so that positive interference of the pump circuit 20 to the generation of power line 30 is also just significantly reduced, electricity
Source line 30 is not substantially affected by the interference of positive pump circuit 20, low pressure difference linear voltage regulator 40 and constant-current generating circuit 50, from
And do not interfere with the performance of other analog modules 10 yet.
It should be noted that pass through low pressure difference linear voltage regulator 40 and constant-current generating circuit 50 in the present invention can be with
Stablizing for the voltage at secondary nodal point N2 is maintained, so as to relative to positive pump circuit of the prior art, the positive pump circuit of the present invention
The size very little of the decoupling capacitor of middle needs, it might even be possible to ignore, such that it is able to reduce the area of whole circuit, saves into
This.
In sum, in the circuit structure and its control method of present invention offer, low pressure difference linear voltage regulator produces one
Constant voltage, in the positive pump circuit of constant-current generating circuit one ratio of generation, the big constant current of maximum charging and discharging currents is given
Positive pump circuit, is absorbed by low pressure difference linear voltage regulator more than the portion of electrical current of positive pump circuit charging and discharging currents so that the 3rd node
Electric current, voltage constant, the electric current and voltage constant of the secondary nodal point being connected with constant-current generating circuit so as to power line are kept away
Impact of the current ripples to the voltage of power line in positive pump circuit is exempted from.
Obviously, those skilled in the art can carry out the essence of various changes and modification without deviating from the present invention to the present invention
God and scope.So, if these modifications of the present invention and modification belong to the scope of the claims in the present invention and its equivalent technologies
Within, then the present invention is also intended to comprising these changes and modification.
Claims (10)
1. a kind of circuit structure, it is characterised in that including power line, constant-current generating circuit, low pressure difference linear voltage regulator, just
Pump circuit, analog circuit and decoupling capacitor, the analog circuit are connected with the power line with primary nodal point；The constant electricity
The raw circuit of miscarriage is connected with the power line with secondary nodal point, and the input connection one of the constant-current generating circuit is with reference to electricity
Stream, the constant-current generating circuit produce a constant output current in the 3rd node；One end of the decoupling capacitor is connected to
Between the primary nodal point and the secondary nodal point, other end ground connection；The constant-current generating circuit is distinguished with the 3rd node
It is connected with the low pressure difference linear voltage regulator and the positive pump circuit, the input connection one of the low pressure difference linear voltage regulator is joined
Voltage is examined, the 3rd node exports a constant voltage, and the constant voltage is supplied to the constant-current generating circuit and institute
Positive pump circuit is stated, the positive pump circuit has the charging and discharging currents of a change, wherein, the constant output current is filled more than described
The maximum of discharge current, the constant output current are residual current more than the portion of electrical current of the charging and discharging currents, described
Residual current is absorbed by the low pressure difference linear voltage regulator, and power line is supplied to the current constant of the secondary nodal point.
2. circuit structure as claimed in claim 1, it is characterised in that the positive pump circuit includes：
Negative circuit, the input of the negative circuit connect the first clock control signal, and the outfan of the negative circuit connects
Connect second clock control signal；
First nmos pass transistor, the drain electrode of first nmos pass transistor connect the 3rd node, and source electrode is connected with the 5th node
The outfan of the negative circuit is connect, grid connects the input of the negative circuit with fourth node；
First electric capacity, first capacitances in series is between the 5th node and the outfan of the negative circuit；
Second nmos pass transistor, the drain electrode of second nmos pass transistor connect the 3rd node, and source electrode connection is described anti-phase
The input of circuit, grid connect the 5th node；
Second electric capacity, second capacitances in series is between the input of the fourth node and the negative circuit；
First PMOS transistor, the drain electrode of first PMOS transistor connect the fourth node, and source electrode is connected with the 6th node
Positive pump circuit outfan is connect, grid connects the 5th node；
Second PMOS transistor, the drain electrode of second PMOS transistor connect the 5th node, source electrode connection the described 6th
Node, grid connect the fourth node；
3rd electric capacity, one end of the 3rd electric capacity connect the 6th node, other end ground connection.
3. circuit structure as claimed in claim 2, it is characterised in that the frequency of first clock control signal is 20MHz-
200MHz。
4. circuit structure as claimed in claim 1, it is characterised in that the low pressure difference linear voltage regulator includes：
Amplifier, the amplifier include first input end and the second input, the first input end connection institute of the amplifier
State reference voltage；
3rd PMOS transistor, the source electrode of the 3rd PMOS transistor connect the 3rd node, grounded drain, grid connection
The outfan of the amplifier；
First resistor, the first resistor are series between the second input of the amplifier and the 3rd node；
Second resistance, the second resistance are series between the second input of the amplifier and ground terminal.
5. circuit structure as claimed in claim 4, it is characterised in that the size of the reference voltage is 1.2V-1.4V.
6. circuit structure as claimed in claim 1, it is characterised in that the constant-current generating circuit includes：
4th PMOS transistor, the source electrode of the 4th PMOS transistor connect the secondary nodal point, drain and gate connection institute
State reference current；
Mirrored transistor string, the mirrored transistor string are brilliant with the secondary nodal point, the 3rd node and the 4th PMOS respectively
The grid connection of body pipe.
7. circuit structure as claimed in claim 6, it is characterised in that the mirrored transistor string includes at least three of parallel connection
PMOS transistor.
8. circuit structure as claimed in claim 7, it is characterised in that the source electrode of at least three PMOS transistors in parallel connects
The secondary nodal point is connect, grid is all connected with the grid of the 4th PMOS transistor, and drain electrode is all connected with the 3rd node.
9. circuit structure as claimed in claim 5, it is characterised in that the size of the reference current is 10 μ A-20 μ A.
10. a kind of control method of the circuit structure as described in any one in claim 1-9, it is characterised in that include：
The reference voltage is provided to the low pressure difference linear voltage regulator, the 3rd node exports a constant voltage, the perseverance
Determine voltage and be supplied to the constant-current generating circuit and the positive pump circuit, discharge and recharge of the positive pump circuit with a change
Electric current；
The reference current is provided to the constant-current generating circuit, the constant-current generating circuit is produced in the 3rd node
One constant output current, maximum of the constant output current more than the charging and discharging currents；
The constant output current is residual current more than the portion of electrical current of the charging and discharging currents, and the residual current is by described
Low pressure difference linear voltage regulator absorbs, and power line is supplied to the current constant of the secondary nodal point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510231068.5A CN104914914B (en) | 2015-05-07 | 2015-05-07 | Circuit structure and its control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510231068.5A CN104914914B (en) | 2015-05-07 | 2015-05-07 | Circuit structure and its control method |
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| Publication Number | Publication Date |
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| CN104914914A CN104914914A (en) | 2015-09-16 |
| CN104914914B true CN104914914B (en) | 2017-03-29 |
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| KR102392791B1 (en) * | 2015-11-04 | 2022-05-02 | 삼성전자주식회사 | Image sensor, electronic device comprising the same and method of operating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6577514B2 (en) * | 2001-04-05 | 2003-06-10 | Saifun Semiconductors Ltd. | Charge pump with constant boosted output voltage |
| KR100562651B1 (en) * | 2003-10-30 | 2006-03-20 | 주식회사 하이닉스반도체 | Multi stage voltage pump circuit |
| TWI329407B (en) * | 2007-02-16 | 2010-08-21 | Richtek Technology Corp | Charge pump regulator and method for producing a regulated voltage |
| CN101674011B (en) * | 2008-12-16 | 2012-05-30 | 昆山锐芯微电子有限公司 | Charge pump |
| KR20130066266A (en) * | 2011-12-12 | 2013-06-20 | 한국전자통신연구원 | Voltage regulator with improved load regulation and voltage regulating method |
| US8981739B2 (en) * | 2012-09-26 | 2015-03-17 | Nxp B.V. | Low power low dropout linear voltage regulator |
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