CN101674011B - Charge pump - Google Patents
Charge pump Download PDFInfo
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- CN101674011B CN101674011B CN2008101792981A CN200810179298A CN101674011B CN 101674011 B CN101674011 B CN 101674011B CN 2008101792981 A CN2008101792981 A CN 2008101792981A CN 200810179298 A CN200810179298 A CN 200810179298A CN 101674011 B CN101674011 B CN 101674011B
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Abstract
The invention relates to a charge pump. The charge pump comprises a first voltage booster circuit, a second voltage booster circuit, an output circuit, a first comparison circuit, a second comparison circuit and a control circuit, wherein the pump capacitance of the first voltage booster circuit is greater than that of the second voltage booster circuit; the output circuit generates the output voltage of the charge pump according to the boosted voltage output of the first voltage booster circuit or the second voltage booster circuit; the first comparison circuit compares the output voltage of the charge pump with a first reference voltage less than a target voltage; the second comparison circuit compares the output voltage of the charge pump with the target voltage; and the control circuit only switches on the first voltage booster circuit when the output voltage of the charge pump is less than the first reference voltage, switches off the first voltage booster circuit but switches on the second voltage booster circuit when the output voltage of the charge pump is more than the first reference voltage but less than the target voltage, and switches off both the first voltage booster circuit and the second voltage booster circuit when the output voltage of the charge pump is more than the target voltage. The output voltage of the charge pump has fewer ripples.
Description
Technical field
The present invention relates to complementary metal oxide semiconductors (CMOS) (CMOS) imageing sensor, employed charge pump in the cmos image sensor particularly is provided.
Background technology
Cmos image sensor is the semiconductor device that is used for optical imagery is converted to the signal of telecommunication.Its basic functional principle is: the photodiode in the cmos image sensor makes public; Through certain time for exposure; Voltage on the photodiode produces different linear voltage drop with different light rays intensity, and reading circuit subsequently becomes digital signal output with this voltage transitions.
Cmos image sensor with 4 pipe pixel cell structures is an example below, does simple declaration to reading image process.
Fig. 1 is a kind of structure chart of 4 pipe pixel cells.With reference to shown in Figure 1, said 4 pipe pixel cells comprise photodiode PD, the first transistor T1, transistor seconds T2, the 3rd transistor T 3 and the 4th transistor T 4.Photodiode PD plus earth, negative pole link to each other with the source electrode of the 4th transistor T 4; The drain electrode that the source electrode of the first transistor T1 links to each other with the drain electrode of the 4th transistor T 4, the grid of the first transistor T1 receives reset signal (RESET), drain electrode and transistor seconds T2 is connected in supply voltage VDD; The grid of transistor seconds T2 links to each other with the source electrode of the first transistor T1, source electrode links to each other with the drain electrode of the 3rd transistor T 3; The grid of the 3rd transistor T 3 receives row selection signal (ROW_SEL), source electrode links to each other with voltage sampling circuit 10; The grid of the 4th transistor T 4 receives electric charge and shifts drive signal (TX).
Wherein, the effect of the first transistor T1 provides reset function.The effect of transistor seconds T2 is as follower.The effect of the 3rd transistor T 3 is to receive row selection signal, reads with the signal of realizing pixel cell.The effect of the 4th transistor T 4 is as transfer tube.When the first transistor T1 and 4 conductings of the 4th transistor T supply voltage VDD is shifted to photodiode PD, when the 3rd transistor T 3 and 4 conductings of the 4th transistor T the electric charge on the photodiode PD is read out on the electric capacity of voltage sampling circuit 10.
Wherein, make public and export photoreceptor signal and all can use the 4th transistor T 4,, guarantee that the charge transfer process do not suffer a loss so need this transistor to open fully.This just needs to use the burning voltage that is higher than supply voltage to shift drive signal (TX) as the electric charge of importing the 4th transistor T 4 grids, and this voltage generally is to be produced by charge pump.But the ripple of charge pump output voltage can be bigger at present, sometimes up to the 200-300 millivolt.Bigger ripple can influence picture quality, for example makes the ripples line can occur on the image.
Summary of the invention
The problem that the present invention will solve is the bigger problem of voltage ripple that the prior art charge pump produces.
For addressing the above problem, the present invention provides a kind of charge pump, comprising:
First booster circuit and second booster circuit, the pumping electric capacity of said first booster circuit is greater than the pumping electric capacity of second booster circuit;
Output circuit is exported the output voltage that forms charge pump according to boosting of said first booster circuit or second booster circuit;
First comparison circuit, with the output voltage of charge pump with less than first reference voltage of target voltage relatively;
Second comparison circuit is with the output voltage and the target voltage comparison of charge pump;
Control circuit when the output voltage of charge pump during less than first reference voltage, is only opened said first booster circuit; When the output voltage of charge pump greater than first reference voltage during less than target voltage, close said first booster circuit and open said second booster circuit; When the output voltage of charge pump during, close said first booster circuit and said second booster circuit greater than target voltage.
Compared with prior art; Such scheme has the following advantages: when charge pump output voltage is low; The booster circuit that use has big electric capacity carries out boosting of supply voltage fast; At charge pump output voltage during near target voltage, use booster circuit to slow down to the boosting of supply voltage with smaller capacitive, make the ripple of charge pump output voltage reduce.
Description of drawings
Fig. 1 is the cmos image sensor structure chart of a kind of 4 pipe pixel cells of prior art;
Fig. 2 is a kind of execution mode figure of charge pump of the present invention;
Fig. 3 is a kind of enforcement illustration of charge pump of the present invention;
Fig. 4 is the circuit diagram of the comparison circuit of charge pump shown in Figure 3;
Fig. 5 is the enlarged drawing of first booster circuit, second booster circuit and the output circuit of charge pump shown in Figure 3.
Embodiment
Research through to existing charge pump can obtain, and can ceaselessly between big electric capacity, switch in the course of work of existing charge pump, thereby make that the ripple of charge pump output voltage can be bigger.And, can adopt little electric capacity, but, can reduce the efficient of charge pump again if only adopt little electric capacity to realize the boost function of charge pump if want to reduce the ripple of charge pump output voltage.
Based on this, the invention provides a kind of charge pump.With reference to shown in Figure 2, a kind of execution mode of said charge pump comprises: control circuit 1, first booster circuit 2, second booster circuit 3, output circuit 4, first comparison circuit 5, second comparison circuit 6, wherein,
The pumping electric capacity of first booster circuit 2 is greater than the pumping electric capacity of second booster circuit 3;
In the above-mentioned execution mode, said target voltage is the desired value that charge pump boosts to supply voltage, and said first reference voltage is got the magnitude of voltage more approaching with target voltage usually, to keep the speed and the efficient of charge pump.
The charge pump of above-mentioned execution mode, its operation principle is following:
When said charge pump has just been opened and since this moment charge pump output voltage to compare target voltage also less, thereby first comparative result of first comparison circuit 5 will show that the output voltage of said charge pump is less than first reference voltage; Also must there be second comparative result of second comparison circuit 6 to show that the output voltage of said charge pump is less than target voltage.
Thereby; Need boost fast this moment and improve the speed and the efficient of charge pump; Control circuit 1 sends first start signal according to the comparative result of first comparison circuit 5 and second comparison circuit 6 to first booster circuit 2; Control has first booster circuit 2 of big pumping electric capacity opens, and supply voltage is boosted, and export first and boost.Said output circuit 4 boosts according to first and forms the output voltage of charge pump.
Carrying out along with the process of boosting; When rising to, the output voltage of charge pump surpasses first reference voltage but during miss the mark voltage; This moment, first comparative result of first comparison circuit 5 showed; The output voltage of said charge pump is greater than first reference voltage, and second comparative result of second comparison circuit 6 shows, the output voltage of said charge pump is less than target voltage.
Because first reference voltage is near target voltage, thereby can boost fast this moment.Said control circuit 1 sends first shutdown signal according to the comparative result of first comparison circuit 5 and second comparison circuit 6 to first booster circuit 2 with big pumping electric capacity; The booster circuit 2 of winning cuts out; And send second start signal to second booster circuit 3 with less pumping electric capacity; Make second booster circuit 3 open, continue supply voltage is boosted, and export second and boost.Said output circuit 4 boosts according to second and forms the output voltage of charge pump.
Because adopted second booster circuit 3 with less pumping electric capacity to carry out slower boosting this moment, thereby the ripple of charge pump output voltage can reduce.
When rising to above target voltage along with the output voltage of charge pump; This moment, first comparative result of first comparison circuit 5 showed; The output voltage of said charge pump is greater than first reference voltage; And second comparative result of second comparison circuit 6 shows, the output voltage of said charge pump is greater than target voltage.
Thereby this moment, the output voltage of charge pump reached target voltage, did not need to boost again.Control circuit 1 sends second shutdown signal according to the comparative result of first comparison circuit 5 and second comparison circuit 6 to second booster circuit 3 with less pumping electric capacity, makes second booster circuit 3 close.At this moment, first booster circuit 2 and second booster circuit 3 are all closed, and the output voltage of charge pump will no longer raise, and possibly descend along with for example driving electricity consumption or various electric leakage.
And when if the output voltage of charge pump drops to less than target voltage; First comparative result of first comparison circuit 5 will show this moment; The output voltage of said charge pump is greater than first reference voltage; And second comparative result of second comparison circuit 6 shows, the output voltage of said charge pump is less than target voltage.Control circuit 1 will be as above said once more sends second start signal to second booster circuit 3, make second booster circuit 3 open once more, again supply voltage is boosted, and exports second and boost.Said output circuit 4 boosts according to second and forms the output voltage of charge pump.
And when if the output voltage of charge pump sharply drops to less than first reference voltage; First comparative result of first comparison circuit 5 will show this moment; The output voltage of said charge pump is less than first reference voltage; And second comparative result of second comparison circuit 6 shows, the output voltage of said charge pump is also less than target voltage.Control circuit 1 will be as above said once more sends first start signal to first booster circuit 2, and the booster circuit 2 of winning is opened once more, again supply voltage is boosted fast, and exports first and boost.Said output circuit 4 boosts according to first and forms the output voltage of charge pump.Thereby the output voltage of charge pump can be returned near the target voltage fast.
Next; Above-mentioned explanation for another example, control circuit 1 surpasses first reference voltage and during miss the mark voltage, cuts out first booster circuit 2 at charge pump output voltage; Open second booster circuit 3 and carry out slower boosting, make the ripple of charge pump output voltage reduce.
Said process goes round and begins again, thereby makes the output voltage of charge pump can remain on target voltage, or is approximately equal on the voltage level of target voltage.
Shown in Figure 3 for a kind of enforcement illustration of charge pump of the present invention.With reference to shown in Figure 3, said charge pump can comprise:
Through the voltage divider that resistance R 1, R2 constitute, first comparison circuit 5 and second comparison circuit 6 that link to each other with said charge pump output;
The logical circuit 8 that links to each other with the output of first comparison circuit 5 and second comparison circuit 6;
The clock control circuit 7 that links to each other with logical circuit 8;
Link to each other with second booster circuit 3 with first booster circuit 2, be used to form the output circuit 4 of charge pump output voltage;
And the external capacitor CL that links to each other with the charge pump output.
Wherein, because the supply voltage of supplies charges pump work is generally all lower, thereby if will provide first comparison circuit 5 required first reference voltage near target voltage, and the required target voltage of second comparison circuit 6, can compare difficulty.Therefore, can be with the comparison of charge pump output voltage and target voltage, and the comparison of the charge pump output voltage and first reference voltage, carry out scaled down.That is, charge pump output voltage is carried out a certain proportion of dividing potential drop, charge pump output voltage after the dividing potential drop and corresponding less reference voltage are compared.
For example; Hypothetical target voltage is 3.9V; First reference voltage is 3.6V, because these two voltages all are higher than supply voltage, thereby can be through the target voltage and first reference voltage are carried out the scaled down processing; For example get separately 1/3, making the second corresponding reference voltage of the reference voltage of winning is 1.2V; The 3rd reference voltage that target voltage is corresponding is 1.3V.Correspondingly, the charge pump output voltage that compares with second reference voltage and the 3rd reference voltage also need pass through dividing potential drop.Here, charge pump output voltage Vout through the voltage divider formed by resistance R 1, R2 among Fig. 3 through 2 to 1 electric resistance partial pressure after, obtain 1/3 of charge pump output voltage value.Through first comparison circuit 5 charge pump output voltage after the dividing potential drop and second reference voltage are compared the comparative result that acquisition and charge pump output voltage and the first reference voltage comparative result are equal to again; Charge pump output voltage after the dividing potential drop and the 3rd reference voltage are compared the comparative result that acquisition and charge pump output voltage and target voltage comparative result are equal to through second comparison circuit 6.
Said logical circuit 8 forms clock control signal enck0, enck1 according to the comparative result of first comparison circuit, 5 comparative results and second comparison circuit 6.
And said clock control circuit 7 provides a pair of phase place opposite non-overlapping clock to first booster circuit 2 when the clock control signal enck0 of logical circuit 8 formation is " 1 "; When clock control signal enck1 is " 1 ", provide a pair of phase place opposite non-overlapping clock to second booster circuit 3.
Said first booster circuit 2 and second booster circuit 3 are opened or are closed according to the corresponding clock that said clock control circuit 7 provides.
And said output circuit 4 forms the output voltage of charge pump according to the output of boosting of first booster circuit 2 or second booster circuit 3.
Wherein, said first comparison circuit 5 can have identical structure with second comparison circuit 6.For example, be example with said first comparison circuit 5, with reference to shown in Figure 4, said first comparison circuit 5 can comprise:
Source electrode and substrate are connected in PMOS pipe M9 and the M10 of VDDA jointly; The grid of said PMOS pipe M9 links to each other with drain electrode; The drain electrode of said PMOS pipe M9 links to each other with the drain electrode of NMOS pipe M11; The grid of said PMOS pipe M10 links to each other with the grid of PMOS pipe M9, and drain electrode links to each other with the output of said first comparison circuit 5
The grid of said NMOS pipe M11 links to each other with the input of second reference voltage of said first comparison circuit 5; The drain electrode of NMOS pipe M12 links to each other with the output of said first comparison circuit; Grid links to each other with the dividing potential drop input of the charge pump output voltage of said first comparison circuit 5; The substrate of said NMOS pipe M11 and M12 is connected in VSSA jointly; The source electrode of said NMOS pipe M11 and M12 is connected in the drain electrode of NMOS pipe M13 jointly, and the grid of said NMOS pipe M13 links to each other with bias voltage vbias, and source electrode links to each other with VSSA with substrate.
Wherein, said first booster circuit 2 can have identical structure with second booster circuit 3, only is that its pumping capacitance size separately is different, and the pumping electric capacity of said first booster circuit 2 is greater than the pumping electric capacity of second booster circuit 3.
With reference to shown in Figure 5, said first booster circuit 2 and second booster circuit 3 all have symmetrical push-pull configuration, and said first booster circuit 2 comprises:
Drain electrode is connected in NMOS pipe M1 and the M2 of supply voltage VDD jointly.Said NMOS pipe M1 and M2 are in source cross-coupled, and promptly the grid of NMOS pipe M1 links to each other with the source electrode of NMOS pipe M2, and the grid of NMOS pipe M2 links to each other with the source electrode of NMOS pipe M1.The substrate of said NMOS pipe M1 and M2 all is connected to vssd.The end of capacitor C 1 and C2 is connected in the source electrode of NMOS pipe M1 and M2 respectively, and the other end is connected in respectively on the opposite non-overlapping clock of a pair of phase place.
Said second booster circuit 3 comprises:
Drain electrode is connected in NMOS pipe M3 and the M4 of supply voltage VDD jointly.Said NMOS pipe M3 and M4 are in source cross-coupled, and promptly the grid of NMOS pipe M3 links to each other with the source electrode of NMOS pipe M4; The grid of NMOS pipe M4 links to each other with the source electrode of NMOS pipe M3.The substrate of said NMOS pipe M3 and M4 all is connected to vssd.The end of capacitor C 3 and C4 is connected in the source electrode of NMOS pipe M1 and M2 respectively, and the other end is connected in respectively on the opposite non-overlapping clock of a pair of phase place.
Wherein, the structure of said output circuit 4, continue can comprise with reference to shown in Figure 5:
The PMOS pipe M5 and the M6 of source cross-coupled; The grid that is PMOS pipe M5 links to each other with the source electrode of PMOS pipe M6, and the grid of PMOS pipe M6 links to each other with the source electrode of PMOS pipe M5, and the source electrode of PMOS pipe M5 links to each other with the source electrode that NMOS manages M1, M3; The source electrode of PMOS pipe M6 links to each other with the source electrode that NMOS manages M2, M4; The substrate of the drain electrode of PMOS pipe M5 and M6, PMOS pipe M5 and M6 is connected together, and links to each other with the substrate of PMOS pipe M7 and M8
PMOS pipe M7 and M8 are in source cross-coupled; The grid that is PMOS pipe M7 links to each other with the source electrode of PMOS pipe M8; The grid of PMOS pipe M8 links to each other with the source electrode of PMOS pipe M7; The source electrode of PMOS pipe M7 links to each other with the source electrode that NMOS manages M1, M3, and the source electrode of PMOS pipe M8 links to each other with the source electrode that NMOS manages M2, M4, and the drain electrode of PMOS pipe M7 and M8 links to each other as the output of charge pump.
Wherein, The substrate of the drain electrode of PMOS pipe M5 and M6, PMOS pipe M5 and M6 is connected together; And link to each other with the substrate of PMOS pipe M7 and M8, be in order to make the substrate of PMOS pipe M7 and M8 owing to boosting of first booster circuit 2 is under the higher voltage, avoid PMOS to manage M7 and the M8 generation is leaked electricity.
Wherein, said clock control circuit 7 continues can to comprise two branch circuits with reference to shown in Figure 3, and each branch circuit provides first booster circuit 2 and the required clock of second booster circuit 3 respectively.With the branch circuit that first booster circuit 2 is provided is example; It can comprise: two input nand gates that receive clkin and enck0 signal respectively; And two inverter branches that link to each other with NAND gate output, said inverter branch is made up of some inverters, and the inverter number of two inverter branches differs one; In order to forming the opposite non-overlapping clock of a pair of phase place, and offer capacitor C 1 and C2 respectively.
The branch circuit that second booster circuit 3 is provided is similar also, and its difference only is that a wherein end signal of said two input nand gates becomes enck1 by enck0, and the non-overlapping clock that a pair of phase place of its generation is opposite offers capacitor C 3 and C4 respectively.
Below in conjunction with above-mentioned illustrational charge pump construction its course of work is elaborated:
Still continue to use above-mentioned setting to the target voltage and first reference voltage and give an example, promptly hypothetical target voltage is 3.9V, and first reference voltage is 3.6V.And the second corresponding reference voltage of first reference voltage is 1.2V, and the 3rd reference voltage that target voltage is corresponding is 1.3V.
When defining the dividing potential drop of first comparison circuit 5 behind the voltage divider that charge pump output voltage constitutes via resistance R 1, R2 less than second reference voltage, output " 0 "; During greater than second reference voltage, output " 1 ".Correspondingly, the dividing potential drop of second comparison circuit 6 behind the voltage divider that charge pump output voltage constitutes via resistance R 1, R2 be during less than the 3rd reference voltage, output " 0 "; During greater than the 3rd reference voltage, output " 1 ".
Suppose that at first the output voltage of charge pump is very low, for example less than 3.6V.Then the dividing potential drop behind the voltage divider that constitutes via resistance R 1, R2 of the output voltage of said charge pump is less than 1.2V, certainly also less than 1.3V.Then first comparison circuit 5 is to logical circuit 8 outputs " 0 ", and second comparison circuit 6 is to logical circuit 8 outputs " 0 ".
Said logical circuit 8 is in " 0 " that obtains 5 outputs of first comparison circuit, and " 0 " of 6 outputs of second comparison circuit afterwards, and the output voltage of knowing charge pump need boost at this moment less than 3.6V fast.Therefore; The clock control signal enck0 that said logical circuit 8 forms is " 1 "; Enck1 is " 0 ", expression need to open have big pumping electric capacity first booster circuit 2 to boost fast, second booster circuit 3 with less pumping electric capacity does not then need to open.
Said clock control circuit 7 is after the clock control signal enck0 that obtains logical circuit 8 outputs, enck1; According to enck0 is " 1 "; Provide a pair of phase place opposite non-overlapping clock to first booster circuit 2, and be " 0 ", then clock is not provided to second booster circuit 3 according to enck1.
Said first booster circuit 2 just begins supply voltage is boosted after obtaining the opposite non-overlapping clock of a pair of phase place that said clock control circuit 7 provides.Continue with reference to shown in Figure 5; In said first booster circuit 2 by NMOS pipe M1, capacitor C 1 forms first boost that branch circuit and NMOS pipe M2, capacitor C 2 form the second branch circuit basis of boosting be connected to the clock on the capacitor C 1 and be connected to the clock on the capacitor C 2, and the supply voltage VDD that raises in turn.
And in the said output circuit 4; PMOS pipe M7 and M8 manage the transient voltage value that M2 source electrode (b0) is located according to NMOS pipe M1 source electrode (a0) and NMOS; And corresponding unlatching; According to the voltage at a0 or b0 place, the relative size of the relative size of capacitor C 1 and external capacitor CL or capacitor C 2 and external capacitor CL, and the output voltage of formation charge pump.
When rising along with the output voltage of charge pump, reach when surpassing 3.6V and during not to 3.9V, then the dividing potential drop behind the voltage divider that constitutes via resistance R 1, R2 of the output voltage of said charge pump is greater than 1.2V, and less than 1.3V.Then first comparison circuit 5 is to logical circuit 8 outputs " 1 ", and second comparison circuit 6 is to logical circuit 8 outputs " 0 ".
Said logical circuit 8 is in " 1 " that obtains 5 outputs of first comparison circuit, and " 0 " of 6 outputs of second comparison circuit is afterwards, and, less than 3.9V can not need fast boost greater than 3.6V output voltage this moment of knowing charge pump, and the rate of pressure rise that can slow down.Therefore; The clock control signal enck0 that said logical circuit 8 forms is " 0 "; Enck1 is " 1 "; Expression need be closed first booster circuit 2 with big pumping electric capacity and stopped to boost fast, carries out slower boosting and open second booster circuit 3 with less pumping electric capacity, makes the ripple of charge pump output voltage reduce.
Next, said clock control circuit 7 just provides a pair of phase place opposite non-overlapping clock to second booster circuit 3, and stops to first booster circuit 2 clock being provided after obtaining clock control signal enck0 and enck1.
Correspondingly, second booster circuit 3 begins to carry out boosting of supply voltage, and forms the output voltage of charge pump according to its output of boosting by output circuit 4.
When the output voltage along with charge pump further raises, reach when surpassing 3.9V, then the dividing potential drop behind the voltage divider that constitutes via resistance R 1, R2 of the output voltage of said charge pump is greater than 1.3V, obviously also greater than 1.2V.Then first comparison circuit 5 is to logical circuit 8 outputs " 1 ", and second comparison circuit 6 is to logical circuit 8 outputs " 1 ".
Said logical circuit 8 is in " 1 " that obtains 5 outputs of first comparison circuit, and " 1 " of 6 outputs of second comparison circuit afterwards, and the output voltage of knowing charge pump no longer needs charge pump to boost at this moment greater than 3.9V.Therefore, the clock control signal enck0 that said logical circuit 8 forms is " 0 ", and enck1 is " 0 ", and expression will have first booster circuit 2 of big pumping electric capacity and all close with second booster circuit 3 with less pumping electric capacity.
After first booster circuit 2 and second booster circuit 3 are closed; The output voltage of charge pump can descend; When the output voltage of charge pump dropped to less than target voltage, this moment, first comparison circuit 5 was exported " 1 " to logical circuit 8, and second comparison circuit 6 is to logical circuit 8 outputs " 0 ".
Said logical circuit 8 will aforesaid once more formation clock control signal enck0 be " 0 "; Enck1 is " 1 "; Expression needs to open second booster circuit 3 with less pumping electric capacity and carries out slower boosting, and makes the ripple of charge pump output voltage reduce.
And if after first booster circuit 2 and second booster circuit 3 are closed; When the output voltage of charge pump sharply drops to less than first reference voltage; This moment, first comparison circuit 5 was exported " 0 " to logical circuit 8, and second comparison circuit 6 is to logical circuit 8 outputs " 0 ".
Said logical circuit 8 will aforesaid once more formation clock control signal enck0 be " 1 ", and enck1 is " 0 ", and expression needs to open first booster circuit 2 with big pumping electric capacity and boosts fast.Thereby the output voltage of charge pump can be returned near the target voltage fast.
Next; Above-mentioned explanation for another example, logical circuit 8 surpasses first reference voltage and during miss the mark voltage, closes first booster circuit 2 at charge pump output voltage; Open second booster circuit 3 and carry out slower boosting, make the ripple of charge pump output voltage reduce.
Though oneself discloses the present invention as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (9)
1. a charge pump is characterized in that, comprising:
First booster circuit and second booster circuit, the pumping electric capacity of said first booster circuit are greater than the pumping electric capacity of second booster circuit, and said first booster circuit has identical structure with second booster circuit;
Output circuit is exported the output voltage that forms charge pump according to boosting of said first booster circuit or second booster circuit;
First comparison circuit, with the output voltage of charge pump with less than first reference voltage of target voltage relatively;
Second comparison circuit is with the output voltage and the target voltage comparison of charge pump;
Control circuit when the output voltage of charge pump during less than first reference voltage, is only opened said first booster circuit; When the output voltage of charge pump greater than first reference voltage during less than target voltage, close said first booster circuit and open said second booster circuit; When the output voltage of charge pump during, close said first booster circuit and said second booster circuit greater than target voltage;
Said first comparison circuit or second comparison circuit comprise:
Source electrode and substrate are connected in the PMOS pipe and the 2nd PMOS pipe of first voltage jointly; The grid of said PMOS pipe links to each other with drain electrode; The drain electrode of said PMOS pipe links to each other with the drain electrode of NMOS pipe; The grid of said the 2nd PMOS pipe links to each other with the grid of PMOS pipe, and drain electrode links to each other with the output of said first comparison circuit
The grid of said NMOS pipe links to each other with the input of second reference voltage of said first comparison circuit; The ratio of the ratio of said second reference voltage and said first reference voltage and the dividing potential drop of charge pump output voltage and charge pump output voltage is identical; The drain electrode of the 2nd NMOS pipe links to each other with the output of said first comparison circuit; Grid links to each other with the dividing potential drop input of the charge pump output voltage of said first comparison circuit; The substrate of said NMOS pipe and the 2nd NMOS pipe is connected in second voltage jointly; The source electrode of said NMOS pipe and the 2nd NMOS pipe is connected in the drain electrode of the 3rd NMOS pipe jointly, and the grid of said the 3rd NMOS pipe links to each other with bias voltage, and source electrode links to each other with second voltage with substrate.
2. charge pump as claimed in claim 1 is characterized in that, also comprises: voltage divider, and with transferring to said first comparison circuit and second comparison circuit after the said charge pump output voltage dividing potential drop.
3. charge pump as claimed in claim 1 is characterized in that, said control circuit comprises:
Logical circuit links to each other with second comparison circuit with first comparison circuit, and the comparative result according to first comparison circuit and the output of second comparison circuit forms clock control signal;
Corresponding booster circuit is opened or closed to clock control circuit according to said clock control signal.
4. charge pump as claimed in claim 1 is characterized in that, said first booster circuit or second booster circuit comprise:
First branch circuit and second branch circuit that boosts that boosts that links to each other with supply voltage; Said first branch circuit and second branch circuit that boosts that boosts is controlled by first clock and second clock respectively, and said first clock signal and second clock are the opposite non-overlapping clock of a pair of phase place; Wherein, when first clock was first phase place, said first branch circuit that boosts was realized boosting to supply voltage; When second clock was first phase place, said second branch circuit that boosts was realized boosting to supply voltage.
5. charge pump as claimed in claim 4 is characterized in that,
Said output circuit is coupled to said first branch circuit and second branch circuit that boosts that boosts, and forms the output of charge pump according to the output of the branch circuit that boosts that supply voltage is boosted.
6. charge pump as claimed in claim 4 is characterized in that,
Said first branch circuit that boosts comprises supply voltage input, first input end of clock, first control end and first output;
Said second branch circuit that boosts comprises supply voltage input, second clock input, second control end and second output;
Wherein, said first boost branch circuit boost second output of branch circuit of first control end and second link to each other, said second boost branch circuit boost first output of branch circuit of second control end and first link to each other.
7. charge pump as claimed in claim 6 is characterized in that, said output circuit comprises:
First selected cell and second selected cell; Said first selected cell comprises that first selects input, first to select control end and first to select output, and said second selected cell comprises that second selects input, second to select control end and second to select output;
Wherein, said first selects second output that input and said second boosts branch circuit to link to each other, and said first selects first output that control end and said first boosts branch circuit to link to each other;
Said second selects first output that input and said first boosts branch circuit to link to each other, and said second selects second output that control end and said second boosts branch circuit to link to each other;
Said first selects output and second to select output to link to each other.
8. charge pump as claimed in claim 4 is characterized in that, said first booster circuit or second booster circuit comprise:
Said first branch circuit that boosts comprises: the 4th NMOS that drain electrode links to each other with supply voltage manages, and first electric capacity that links to each other with first clock of an end; The other end of said first electric capacity links to each other with the source electrode of said the 4th NMOS pipe;
Said second branch circuit that boosts comprises: the 5th NMOS that drain electrode links to each other with supply voltage manages, and second electric capacity that links to each other with second clock of an end; The other end of said second electric capacity links to each other with the source electrode of said the 5th NMOS pipe,
The grid of said the 4th NMOS pipe links to each other with the source electrode of said the 5th NMOS pipe, and the grid of said the 5th NMOS pipe links to each other with the source electrode of said the 4th NMOS pipe.
9. charge pump as claimed in claim 8 is characterized in that, said output circuit comprises:
The 3rd PMOS pipe and the 4th PMOS pipe; Wherein, the grid of said the 3rd PMOS pipe links to each other with the source electrode of the 4th PMOS pipe, and source electrode links to each other with the source electrode of the 5th NMOS pipe; The grid of said the 4th PMOS pipe links to each other with the source electrode of the 3rd PMOS pipe, and source electrode links to each other with the source electrode of the 4th NMOS pipe; The drain electrode of said the 3rd PMOS pipe and the 4th PMOS pipe links to each other as the output of charge pump.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101792981A CN101674011B (en) | 2008-12-16 | 2008-12-16 | Charge pump |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008101792981A CN101674011B (en) | 2008-12-16 | 2008-12-16 | Charge pump |
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| CN101674011A CN101674011A (en) | 2010-03-17 |
| CN101674011B true CN101674011B (en) | 2012-05-30 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103312162B (en) * | 2012-03-08 | 2016-01-13 | 扬州稻源微电子有限公司 | Voltage-multiplying circuit and comprise its radio frequency identification label chip |
| US20150109500A1 (en) * | 2013-10-18 | 2015-04-23 | Omnivision Technologies, Inc. | Image sensor including spread spectrum charge pump |
| CN103618468B (en) * | 2013-11-11 | 2015-12-23 | 重庆西南集成电路设计有限责任公司 | Form high efficiency rectifier and the rectification unit of RFID |
| CN104914914B (en) * | 2015-05-07 | 2017-03-29 | 豪威科技(上海)有限公司 | Circuit structure and its control method |
| KR20170034578A (en) * | 2015-09-21 | 2017-03-29 | 에스케이하이닉스 주식회사 | Regulator, memory system having the same and operating method thereof |
| CN108075654A (en) * | 2016-11-15 | 2018-05-25 | 合肥科盛微电子科技有限公司 | The supply voltage amplifier of New Charge pump configuration |
| CN108696118B (en) * | 2017-04-07 | 2020-12-08 | 原相科技(槟城)有限公司 | Boosting circuit and method for biasing substrate therein |
| CN108809084B (en) * | 2018-06-14 | 2020-03-06 | 长江存储科技有限责任公司 | Charge pump circuit |
| CN111934542B (en) * | 2019-05-13 | 2021-10-08 | 北京兆易创新科技股份有限公司 | Charge pump voltage stabilizing circuit, voltage stabilizing method and nonvolatile memory |
| CN116137493A (en) * | 2021-11-17 | 2023-05-19 | 科奇芯有限公司 | Charge pump circuit |
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| US20070069801A1 (en) * | 2005-05-20 | 2007-03-29 | Stmicroelectronics S.R.L. | Charge-pump type, voltage-boosting device with reduced ripple, in particular for non-volatile flash memories |
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