CN104851848A - 一种c-sam中接合晶圆的密封结构及其制备方法 - Google Patents

一种c-sam中接合晶圆的密封结构及其制备方法 Download PDF

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Publication number
CN104851848A
CN104851848A CN201410053580.0A CN201410053580A CN104851848A CN 104851848 A CN104851848 A CN 104851848A CN 201410053580 A CN201410053580 A CN 201410053580A CN 104851848 A CN104851848 A CN 104851848A
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China
Prior art keywords
hermetically
projection
sealed construction
bond wafer
wafer
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CN201410053580.0A
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侯元琨
游宽结
华宇
赵月林
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN201410053580.0A priority Critical patent/CN104851848A/zh
Priority to US14/559,197 priority patent/US9653312B2/en
Publication of CN104851848A publication Critical patent/CN104851848A/zh
Priority to US15/482,346 priority patent/US9837287B2/en
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Abstract

本发明涉及一种C-SAM中接合晶圆的密封结构及其制备方法,所述密封结构位于所述接合晶圆的边缘,将位于所述密封结构内侧的所述接合晶圆形成密封区域,以防止C-SAM检测中所述接合晶圆的间隙进水;其中,所述接合晶圆包括相互接合的上部接合晶圆和下部接合晶圆。本发明的优点在于:(1)所述接合晶圆边缘上设置的密封结构可以在C-SAM检测过程中将水封锁在晶圆之外。(2)可以根据预先设定的检测方法选用C-SAM对所述晶圆接合质量进行检测。(3)所述晶圆在C-SAM检测之后不会受到损坏。

Description

一种C-SAM中接合晶圆的密封结构及其制备方法
技术领域
本发明涉及半导体领域,具体地,本发明涉及一种C-SAM中接合晶圆的密封结构及其制备方法。
背景技术
在电子消费领域,多功能设备越来越受到消费者的喜爱,相比于功能简单的设备,多功能设备制作过程将更加复杂,比如需要在电路版上集成多个不同功能的芯片,因而出现了3D集成电路(integrated circuit,IC)技术,3D集成电路(integrated circuit,IC)被定义为一种系统级集成结构,将多个芯片在垂直平面方向堆叠,从而节省空间,各个芯片的边缘部分可以根据需要引出多个引脚,根据需要利用这些引脚,将需要互相连接的芯片通过金属线互联,但是上述方式仍然存在很多不足,比如堆叠芯片数量较多,而且芯片之间的连接关系比较复杂,那么就会需要利用多条金属线,最终的布线方式比较混乱,而且也会导致体积增加。
3D IC是将原裸晶尺寸的处理器晶片、可程式化逻辑闸(FPGA)晶片、记忆体晶片、射频晶片(RF)或光电晶片,打薄之后直接叠合,并透过TSV钻孔连接。在3D IC立体叠合技术,硅通孔(TSV)、中介板(Interposer)等关键技术/封装零组件的协助下,在有限面积内进行最大程度的晶片叠加与整合。
因此,晶圆水平上的晶圆之间的接合(Wafer level Cu-Cu bonding)为3D IC中的一项关键技术,如何有效的在线检测晶圆接合(bonding)的质量和良率显得尤其重要。
近年来,超声波扫描显微镜(C-SAM)已被成功地应用在电子工业,尤其是封装技术研究及实验室之中。由于超音波具有不用拆除组件外部封装之非破坏性检测能力,故C-SAM可以有效的检出IC构装中因水气或热能所造成的破坏如﹕脱层、气孔及裂缝…等。超声波在行经介质时,若遇到不同密度或弹性系数之物质时,即会产生反射回波。而此种反射回波强度会因材料密度不同而有所差异,C-SAM即最利用此特性来检出材料内部的缺陷并依所接收之讯号变化将之成像。因此,只要被检测的IC上表面或内部芯片构装材料的接口有脱层、气孔、裂缝…等缺陷时,即可由C-SAM影像得知缺陷之相对位置。
特别是低熔点接合(Eutectic bond)需要C-SAM来检测接合质量,其中所述低熔点接合(Eutectic bond)的两个晶圆之间具有间隙(gap),如图1所示,第一晶圆101和第二晶圆102接合在一起时,在边缘处形成有间隙10,将所述接合后形成的晶圆放入所述C-SAM中后,水便会进入所述间,10中,从而对检测结果造成干扰。
为了解决上述问题,通常选用强力胶(super glue)涂抹在晶圆的边缘,以防止水进入所述晶圆之间的间隙,如图2所示,其中右侧为左侧图中圆圈部分的放大图,所述方法能够在一定程度上解决该问题,但是也带来很多弊端,例如涂抹强力胶(super glue)会对晶圆造成破坏,在晶圆上形成强力胶区域20,无法去除。
因此,现有技术中选用C-SAM对晶圆接合质量进行检测时,晶圆之间的间隙中会进入水,对检测质量造成影响,而选用强力胶填充所述间隙时会对晶圆造成损害,目前还没有很好的解决办法,成为晶圆接合质量检测中亟需解决的问题。
发明内容
在发明内容部分中引入了一系列简化形式的概念,这将在具体实施方式部分中进一步详细说明。本发明的发明内容部分并不意味着要试图限定出所要求保护的技术方案的关键特征和必要技术特征,更不意味着试图确定所要求保护的技术方案的保护范围。
本发明为了克服目前存在问题,提供了一种C-SAM中接合晶圆的密封结构,所述密封结构位于所述接合晶圆的边缘,将位于所述密封结构内侧的所述接合晶圆形成密封区域,以防止C-SAM检测中所述接合晶圆的间隙进水;
其中,所述接合晶圆包括相互接合的上部接合晶圆和下部接合晶圆。
作为优选,所述密封结构和所述接合晶圆中的金属层选用相同的材料。
作为优选,所述密封结构包括设置于所述上部接合晶圆的第一凸起和设置于所述下部接合晶圆上的第二凸起,所述第一凸起和所述第二凸起之间密封接合为一体。
作为优选,其中所述第一凸起和所述上部接合晶圆表面的金属层具有相同的高度。
作为优选,所述第二凸起和所述下部接合晶圆表面的金属层具有相同的高度。
作为优选,所述密封结构呈环状结构。
作为优选,所述密封结构包括内外嵌套设置的两个环状结构,所述两个环状结构之间相互隔离设置。
本发明还提供了一种C-SAM中接合晶圆的密封结构的制备方法,包括:
提供分离的上部接合晶圆和下部接合晶圆;
在所述上部接合晶圆的边缘和所述下部接合晶圆的边缘形成密封材料层;
在所述密封材料层上形成图案化的掩膜层;
以所述掩膜层为掩膜蚀刻所述密封材料层,以分别在所述上部接合晶圆和所述下部接合晶圆的边缘形成第一凸起和第二凸起;
将所述第一凸起和所述第二凸起接合为一体,以形成所述密封结构,将位于所述密封结构内侧的所述接合晶圆形成密封区域。
作为优选,所述图案化的掩膜层中形成有1:1的所述第一凸起和所述第二凸起。
作为优选,所述第一凸起所选用的材料与所述上部接合晶圆表面的金属层的材料相同。
作为优选,所述第一凸起的高度与所述上部接合晶圆表面金属层的高度相同。
作为优选,所述第二凸起所选用的材料与所述下部接合晶圆表面的金属层的材料相同。
作为优选,所述第二凸起的高度与所述下部接合晶圆表面金属层的高度相同。
作为优选,将所述第一凸起和所述第二凸起接合为一体的同时,所述上部接合晶圆中的其他图案与所述下部接合晶圆中的相应的图案接合为一体,实现所述上部接合晶圆和所述下部接合晶圆的接合。
作为优选,所述第一凸起和所述第二凸起均为环状结构。
作为优选,所述上部接合晶圆上形成有内外嵌套设置的两个环状结构的所述第一凸起,所述两个环状结构的所述第一凸起之间相互隔离设置。
作为优选,所述下部接合晶圆上相应地形成有内外嵌套设置的两个环状结构的所述第二凸起,所述两个环状结构的所述第二凸起之间相互隔离设置。
本发明为了解决现有技术中存在的问题提供了一种C-SAM中接合晶圆的密封结构,所述密封结构设置于所述晶圆的边缘,在C-SAM检测过程中以防止水进入两晶圆之间的间隙中,然后对所述晶圆中所有区域的接合质量进行检测,可以避免进入水后对检测结果造成影响,本发明的优点在于:
(1)所述接合晶圆边缘上设置的密封结构可以在C-SAM检测过程中将水封锁在晶圆之外。
(2)可以根据预先设定的检测方法选用C-SAM对所述晶圆接合质量进行检测。
(3)所述晶圆在C-SAM检测之后不会受到损坏。
附图说明
本发明的下列附图在此作为本发明的一部分用于理解本发明。附图中示出了本发明的实施例及其描述,用来解释本发明的装置及原理。在附图中,
图1为现有技术中上部接合晶圆和下部接合晶圆接合在一起后的结构示意图;
图2为现有技术中上部接合晶圆和下部接合晶圆接合时在边缘涂覆强力胶的结构示意图,右图为左侧图中圆圈部分的局部放大图;
图3为本发明一具体地实施方式中所述密封结构的结构示意图,其中图3a为所述密封结构的俯视图,图3b为图3a沿A-A的剖面示意图;
图4为本发明一具体地实施方式中所述密封结构的制备工艺流程图。
具体实施方式
在下文的描述中,给出了大量具体的细节以便提供对本发明更为彻底的理解。然而,对于本领域技术人员而言显而易见的是,本发明可以无需一个或多个这些细节而得以实施。在其他的例子中,为了避免与本发明发生混淆,对于本领域公知的一些技术特征未进行描述。
为了彻底理解本发明,将在下列的描述中提出详细的描述,以说明本发明所述晶圆接合质量的检测结构及其检测方法。显然,本发明的施行并不限于半导体领域的技术人员所熟习的特殊细节。本发明的较佳实施例详细描述如下,然而除了这些详细描述外,本发明还可以具有其他实施方式。
应予以注意的是,这里所使用的术语仅是为了描述具体实施例,而非意图限制根据本发明的示例性实施例。如在这里所使用的,除非上下文另外明确指出,否则单数形式也意图包括复数形式。此外,还应当理解的是,当在本说明书中使用术语“包含”和/或“包括”时,其指明存在所述特征、整体、步骤、操作、元件和/或组件,但不排除存在或附加一个或多个其他特征、整体、步骤、操作、元件、组件和/或它们的组合。
现在,将参照附图更详细地描述根据本发明的示例性实施例。然而,这些示例性实施例可以多种不同的形式来实施,并且不应当被解释为只限于这里所阐述的实施例。应当理解的是,提供这些实施例是为了使得本发明的公开彻底且完整,并且将这些示例性实施例的构思充分传达给本领域普通技术人员。在附图中,为了清楚起见,夸大了层和区域的厚度,并且使用相同的附图标记表示相同的元件,因而将省略对它们的描述。
本发明为了解决现有技术中存在的问题提供了一种C-SAM中接合晶圆的密封结构,所述C-SAM中接合晶圆的密封结构位于所述接合晶圆的边缘,将位于所述密封结构内侧的所述接合晶圆形成密封区域,以防止C-SAM检测中所述接合晶圆的间隙进水;
其中,所述接合晶圆包括相互接合的上部接合晶圆和下部接合晶圆。
所述密封结构设置于接合晶圆的边缘,所述密封结构为金属密封结构,所述金属密封结构可以接合在一起,位于所述密封结构内的界面是密不透气的(airproof),将所述晶圆放在水中进行C-SAM检测时,水不会进入晶圆中,不会对检测结果造成影响。
此外,本发明还提供了一种所述C-SAM中接合晶圆的密封结构的制备方法,包括:
提供上部接合晶圆和下部接合晶圆;
在所述上部接合晶圆的边缘和所述下部接合晶圆的边缘形成密封材料层;
在所述密封材料层上形成图案化的掩膜层;
以所述掩膜层为掩膜蚀刻所述密封材料层,以分别在所述上部接合晶圆的和所述下部接合晶圆形成第一凸起和第二凸起;
将所述第一凸起和所述第二凸起接合为一体,以形成所述密封结构,将位于所述密封结构内侧的所述接合晶圆形成密封区域。
下面结合附图对本发明所述密封结构以及制备方法作进一步的说明。
实施例1
下面结合附图3a-3b对本发明所述密封结构作进一步的说明,其中,图3为该实施例中所述密封结构的结构示意图,其中图3a为所述密封结构的俯视图,图3b为图3a沿A-A的剖面示意图。
本发明中所述密封结构203位于所述接合晶圆的边缘位置,其中所述接合晶圆包括上部接合晶圆202和下部接合晶圆201,其中所述上部接合晶圆202和下部接合晶圆201接合为一体,形成所述接合晶圆。
作为优选,所述上部接合晶圆202和下部接合晶圆201均为环状结构,如图3a所示,由此位于所述接合晶圆边缘的密封结构203也呈环状结构,但是需要说明的是所述密封结构并不局限于环状结构,所述密封结构还可以设置为不规则的多边形结构或者方形结构,可以根据所述上部接合晶圆202和下部接合晶圆201的形状发生变化。
其中,所述密封结构203设置于所述接合晶圆的边缘,所述密封结构一端连接所述上部接合晶圆202,另一端连接所述下部接合晶圆201,将所述密封结构203的内侧完全包围,形成密封区域,在设置所述密封结构203后,在所述接合晶圆的边缘不会再有液体可以渗入的缝隙,防止在C-SAM检测过程中液体进入接合晶圆的缝隙,对结果造成影响。
其中所述密封结构203包括相互嵌套的两个环状的密封环203a和203b,密封环203a和203b之间相互隔离设置,其中所述密封环203a和203b之间的空腔中还可以形成有其他图案,例如金属层等,并不局限于某一种。
作为优选,其中所述上部接合晶圆202和下部接合晶圆201中还分别形成有其他图案,例如在所述上部接合晶圆202的表面形成有金属层图案或者其他图案,在所述下部接合晶圆201中也形成有金属层图案,同时还形成有和所述上部接合晶圆202中金属层相对应的空腔,所述上部接合晶圆202中的金属层图案和所述下部接合晶圆201表面的金属层接合为一体,实现所述上部接合晶圆202和下部接合晶圆201的接合。
作为优选,所述密封结构203可以通过两部分接合为一体,例如所述密封结构203包括位于所述上部接合晶圆202边缘的第一凸起和位于所述下部接合晶圆201边缘的第二凸起,所述上部接合晶圆202和下部接合晶圆201接合的过程中,所述第一凸起和所述第二凸起接合为一体,形成所述密封结构203,将位于密封结构203界面内侧的区域形成封闭区域,将所述接合晶圆中的缝隙包围在所述密封区域中,防止液体渗入所述缝隙中对检测结果造成影响。
作为优选,所述第一凸起和所述第二凸起和所述上部接合晶圆202、所述下部接合晶圆201表面金属层选用相同的材料,所述金属层材料并不局限于某一种,可以根据实际工艺的需要进行选择。
进一步,所述第一凸起和所述第二凸起和所述上部接合晶圆202、所述下部接合晶圆201中其他图案的高度相同,以保证在上部接合晶圆202、所述下部接合晶圆201接合过程中所述第一凸起和所述第二凸起能够完全接合在一起,形成完全密封的结构。
其中,所述第一凸起和所述第二凸起相对应设置,以保证在所述上部接合晶圆202和所述下部接合晶圆201接合过程中能使所述第一凸起和所述第二凸起充分的接合。
需要说明的是,所述第一凸起和所述第二凸起接合形成所述密封结构203仅仅为形成所述密封结构203的一种优选实施方式,但是并不局限于该实施方式,例如还可以仅在所述上部接合晶圆202上或者仅在所述下部接合晶圆201的边缘上设置凸起,通过所述方式设置时所述凸起的高度要和所述上部接合晶圆202上或者仅在所述下部接合晶圆201接合后两者之间的距离相等,以保证所述凸起和另外一个晶圆的表面相接合,形成所述密封结构。当然还可以有其他的形成方法,只要能够在所述上部接合晶圆202上或者仅在所述下部接合晶圆201之间形成所述密封结构203即可应用于本发明。
实施例2
为了更好地实施本发明,在该实施例中给出了一种所述密封结构203的优选制备方法,包括以下步骤:
首先,执行步骤201,提供上部接合晶圆202和下部接合晶圆201。
具体地,其中所述上部接合晶圆202和下部接合晶圆201中还分别形成有其他图案,例如在所述上部接合晶圆202的表面形成有金属层图案或者其他图案,在所述下部接合晶圆201中也形成有金属层图案,同时还形成有和所述上部接合晶圆202中金属层相对应的空腔,所述上部接合晶圆202中的金属层图案和所述下部接合晶圆201表面的金属层接合为一体,实现所述上部接合晶圆202和下部接合晶圆201的接合。
其中所述上部接合晶圆202和下部接合晶圆201可以为一个半导体器件中的晶圆,还可以为3D集成电路(integrated circuit,IC)中所要集成在一起的晶圆。
作为优选,在该实施例中,在所述下部接合晶圆201中形成有元器件图案,并在所述晶圆的表面形成有用于接合的金属层,其中所述金属层的形成方法可以选用本领域常用方法,例如首先在所述下部接合晶圆201中形成层间介电层,然后图案化形成沟槽,然后在所述沟槽中填充金属材料,形成所述金属层。
其中在所述上部接合晶圆202中形成有金属接合端,其中所述金属接合端可以和所述下部接合晶圆201中的金属层相接合,以实现所述上部接合晶圆202和下部接合晶圆201之间的接合,形成接合晶圆。
执行步骤202,在所述上部接合晶圆202上形成第一凸起,在所述下部接合晶圆201上形成第二凸起。
具体地,在所述上部接合晶圆202上形成密封材料层,其中所述密封材料层可以选用在晶圆接合中常用的接合材料,并不局限于某一种。
作为优选,在该实施例中所述密封材料层选用和所述上部接合晶圆202中金属接合端、所述下部接合晶圆201中金属层选用相同的材料,以保证在所述上部接合晶圆202和下部接合晶圆201接合的工艺条件与所述第一凸起和所述第二凸起接合的工艺条件一致,不需要执行额外的接合,使两个接合过程融合为一体,使工艺过程更加兼容。
然后在所述密封材料层上形成图案化的掩膜层,所述掩膜层可以为图案化的光刻胶层,或者由光刻胶层、底部抗反射层以及有机层形成的掩膜叠层,所述掩膜层中形成有所述第一凸起的图案。以所述掩膜层为掩膜蚀刻所述密封材料层,以将所述第一凸起的图案转移至所述密封材料层中,形成第一凸起,然后去除所述掩膜层。
其中所述第一凸起呈环状结构,位于所述上部接合晶圆202的边缘,作为优选,所述第一凸起的数目可以为两个,具体地为内外相互嵌套的两个环状结构,其中所述两个环状结构相互隔离。形成所述相互嵌套的两个环状结构以确保所述界面内侧的区域能够完全密封,防止液体渗入所述缝隙中。
作为进一步的优选,所述第一凸起的高度和所述上部接合晶圆202中其他图案的高度一致,以保证在接合过程和底部接合晶圆201很好的接合。
其中所述下部接合晶圆201上形成第二凸起的方法和所述上部接合晶圆202上形成第一凸起的方法可以相同或者相似,当然所述下部接合晶圆201上形成第二凸起的方法还可以根据需要进行改变,并不局限于上述示例。
执行步骤203,将所述第一凸起和所述第二凸起接合为一体,以形成所述密封结构,将位于所述密封结构内侧的所述接合晶圆形成密封区域。
具体地,在该步骤中所述上部接合晶圆202和所述下部接合晶圆201上其他金属层同时接合的同时实现所述第一凸起和所述第二凸起的接合,所述第一凸起和所述第二凸起接合为一体,形成所述密封结构203,将位于密封结构203界面内侧的区域形成封闭区域,将所述接合晶圆中的缝隙包围在所述密封区域中,防止液体渗入所述缝隙中对检测结果造成影响。
其中,所述第一凸起和所述第二凸起上下相互对应,以便能够完全接合为一体,形成所述密封结构。
所述第一凸起和所述第二凸起以及所述晶圆之间通过共晶接合或者热键合的方法键合在一起,在该实施例中在该步骤中优选为热键合的方法,在该步骤中用化学清洗试剂进行清洗,清洗过程必须严格遵守操作规范,其中包括对溶液浓度配比、加热时间、冲水时间的控制等,以增强两键合面的亲水性。此外,键合能否实现还取决于晶圆表面的起伏度(也称平整度),通常需在5A以下。在保证以上两个条件的情况下,控制产品需要的工艺温度以保证较大的键合强度。
图4为本发明一具体地实施方式中所述密封结构的制备工艺流程图,具体地包括以下步骤:
步骤201提供分离的上部接合晶圆和下部接合晶圆;
步骤202在所述上部接合晶圆的边缘和所述下部接合晶圆的边缘形成密封材料层;
步骤203在所述密封材料层上形成图案化的掩膜层;
步骤204以所述掩膜层为掩膜蚀刻所述密封材料层,以分别在所述上部接合晶圆和所述下部接合晶圆的边缘形成第一凸起和第二凸起;
步骤205将所述第一凸起和所述第二凸起接合为一体,以形成所述密封结构,将位于所述密封结构内侧的所述接合晶圆形成密封区域。
本发明为了解决现有技术中存在的问题提供了一种C-SAM中接合晶圆的密封结构,所述密封结构设置于所述晶圆的边缘,在C-SAM检测过程中以防止水进入两晶圆之间的间隙中,然后对所述晶圆中所有区域的接合质量进行检测,可以避免进入水后对检测结果造成影响,本发明的优点在于:
(1)所述晶圆边缘上设置的密封结构可以在C-SAM检测过程中将水封锁在晶圆之外。
(2)可以根据预先设定的检测方法选用C-SAM对所述晶圆接合质量进行检测。
(3)所述晶圆在C-SAM检测之后不会受到损坏。
本发明已经通过上述实施例进行了说明,但应当理解的是,上述实施例只是用于举例和说明的目的,而非意在将本发明限制于所描述的实施例范围内。此外本领域技术人员可以理解的是,本发明并不局限于上述实施例,根据本发明的教导还可以做出更多种的变型和修改,这些变型和修改均落在本发明所要求保护的范围以内。本发明的保护范围由附属的权利要求书及其等效范围所界定。

Claims (17)

1.一种C-SAM中接合晶圆的密封结构,所述密封结构位于所述接合晶圆的边缘,将位于所述密封结构内侧的所述接合晶圆形成密封区域,以防止C-SAM检测中所述接合晶圆的间隙进水;
其中,所述接合晶圆包括相互接合的上部接合晶圆和下部接合晶圆。
2.根据权利要求1所述的密封结构,其特征在于,所述密封结构和所述接合晶圆中的金属层选用相同的材料。
3.根据权利要求1所述的密封结构,其特征在于,所述密封结构包括设置于所述上部接合晶圆的第一凸起和设置于所述下部接合晶圆上的第二凸起,所述第一凸起和所述第二凸起之间密封接合为一体。
4.根据权利要求1所述的密封结构,其特征在于,其中所述第一凸起和所述上部接合晶圆表面的金属层具有相同的高度。
5.根据权利要求1所述的密封结构,其特征在于,所述第二凸起和所述下部接合晶圆表面的金属层具有相同的高度。
6.根据权利要求1所述的密封结构,其特征在于,所述密封结构呈环状结构。
7.根据权利要求1或6所述的密封结构,其特征在于,所述密封结构包括内外嵌套设置的两个环状结构,所述两个环状结构之间相互隔离设置。
8.一种C-SAM中接合晶圆的密封结构的制备方法,包括:
提供分离的上部接合晶圆和下部接合晶圆;
在所述上部接合晶圆的边缘和所述下部接合晶圆的边缘形成密封材料层;
在所述密封材料层上形成图案化的掩膜层;
以所述掩膜层为掩膜蚀刻所述密封材料层,以分别在所述上部接合晶圆和所述下部接合晶圆的边缘形成第一凸起和第二凸起;
将所述第一凸起和所述第二凸起接合为一体,以形成所述密封结构,将位于所述密封结构内侧的所述接合晶圆形成密封区域。
9.根据权利要求8所述的方法,其特征在于,所述图案化的掩膜层中形成有1:1的所述第一凸起和所述第二凸起。
10.根据权利要求8所述的方法,其特征在于,所述第一凸起所选用的材料与所述上部接合晶圆表面的金属层的材料相同。
11.根据权利要求8所述的方法,其特征在于,所述第一凸起的高度与所述上部接合晶圆表面金属层的高度相同。
12.根据权利要求8所述的方法,其特征在于,所述第二凸起所选用的材料与所述下部接合晶圆表面的金属层的材料相同。
13.根据权利要求8所述的方法,其特征在于,所述第二凸起的高度与所述下部接合晶圆表面金属层的高度相同。
14.根据权利要求8所述的方法,其特征在于,将所述第一凸起和所述第二凸起接合为一体的同时,所述上部接合晶圆中的其他图案与所述下部接合晶圆中的相应的图案接合为一体,实现所述上部接合晶圆和所述下部接合晶圆的接合。
15.根据权利要求8所述的方法,其特征在于,所述第一凸起和所述第二凸起均为环状结构。
16.根据权利要求15所述的方法,其特征在于,所述上部接合晶圆上形成有内外嵌套设置的两个环状结构的所述第一凸起,所述两个环状结构的所述第一凸起之间相互隔离设置。
17.根据权利要求16所述的方法,其特征在于,所述下部接合晶圆上相应地形成有内外嵌套设置的两个环状结构的所述第二凸起,所述两个环状结构的所述第二凸起之间相互隔离设置。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108122823A (zh) * 2016-11-30 2018-06-05 中芯国际集成电路制造(上海)有限公司 晶圆键合方法及晶圆键合结构

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109920787B (zh) * 2017-12-12 2021-05-25 中芯国际集成电路制造(北京)有限公司 互连结构的设计方法、装置及制造方法
CN115404470B (zh) * 2022-08-24 2023-06-30 江苏天芯微半导体设备有限公司 一种密封内衬、半导体设备平台及维护方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020000646A1 (en) * 2000-02-02 2002-01-03 Raytheon Company, A Delware Corporation Vacuum package fabrication of integrated circuit components
CN1825604A (zh) * 2005-02-21 2006-08-30 华宸科技股份有限公司 感测器封装结构、感测器封装制程、感测器模组及其制造方法
JP2008288497A (ja) * 2007-05-21 2008-11-27 Toshiba Corp 微小電気機械装置
US20090029500A1 (en) * 2004-05-27 2009-01-29 Chang-Feng Wan Hermetic pacakging and method of manufacture and use therefore
CN101552263A (zh) * 2009-05-18 2009-10-07 中国电子科技集团公司第十三研究所 芯片圆片级封装及其封装方法
CN102111116A (zh) * 2010-11-24 2011-06-29 张�浩 整合的晶圆级别封装体
US20120074555A1 (en) * 2010-09-29 2012-03-29 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Semiconductor package including cap

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040259325A1 (en) * 2003-06-19 2004-12-23 Qing Gan Wafer level chip scale hermetic package
KR100831405B1 (ko) * 2006-10-02 2008-05-21 (주) 파이오닉스 웨이퍼 본딩 패키징 방법
DE102007060632A1 (de) * 2007-12-17 2009-06-18 Robert Bosch Gmbh Verfahren zum Herstellen eines Kappenwafers für einen Sensor
US8975105B2 (en) * 2011-06-20 2015-03-10 Raytheon Company Hermetically sealed wafer packages
US8736045B1 (en) * 2012-11-02 2014-05-27 Raytheon Company Integrated bondline spacers for wafer level packaged circuit devices

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020000646A1 (en) * 2000-02-02 2002-01-03 Raytheon Company, A Delware Corporation Vacuum package fabrication of integrated circuit components
US20090029500A1 (en) * 2004-05-27 2009-01-29 Chang-Feng Wan Hermetic pacakging and method of manufacture and use therefore
CN1825604A (zh) * 2005-02-21 2006-08-30 华宸科技股份有限公司 感测器封装结构、感测器封装制程、感测器模组及其制造方法
JP2008288497A (ja) * 2007-05-21 2008-11-27 Toshiba Corp 微小電気機械装置
CN101552263A (zh) * 2009-05-18 2009-10-07 中国电子科技集团公司第十三研究所 芯片圆片级封装及其封装方法
US20120074555A1 (en) * 2010-09-29 2012-03-29 Avago Technologies Wireless Ip (Singapore) Pte. Ltd. Semiconductor package including cap
CN102111116A (zh) * 2010-11-24 2011-06-29 张�浩 整合的晶圆级别封装体

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108122823A (zh) * 2016-11-30 2018-06-05 中芯国际集成电路制造(上海)有限公司 晶圆键合方法及晶圆键合结构

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