CN104769704A - Method for processing semiconductor wafer - Google Patents
Method for processing semiconductor wafer Download PDFInfo
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- CN104769704A CN104769704A CN201480002327.0A CN201480002327A CN104769704A CN 104769704 A CN104769704 A CN 104769704A CN 201480002327 A CN201480002327 A CN 201480002327A CN 104769704 A CN104769704 A CN 104769704A
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- wafer
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- ripple
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02013—Grinding, lapping
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B27/00—Other grinding machines or devices
- B24B27/06—Grinders for cutting-off
- B24B27/0633—Grinders for cutting-off using a cutting wire
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
- B24B37/07—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
- B24B37/08—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for double side lapping
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
- B24B37/07—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
- B24B37/10—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for single side lapping
- B24B37/105—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for single side lapping the workpieces or work carriers being actively moved by a drive, e.g. in a combined rotary and translatory movement
- B24B37/107—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for single side lapping the workpieces or work carriers being actively moved by a drive, e.g. in a combined rotary and translatory movement in a rotary movement only, about an axis being stationary during lapping
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B7/00—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
- B24B7/20—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground
- B24B7/22—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
- B24B7/228—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain for grinding thin, brittle parts, e.g. semiconductors, wafers
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B28—WORKING CEMENT, CLAY, OR STONE
- B28D—WORKING STONE OR STONE-LIKE MATERIALS
- B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
- B28D5/04—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by tools other than rotary type, e.g. reciprocating tools
- B28D5/045—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor by tools other than rotary type, e.g. reciprocating tools by cutting with wires or closed-loop blades
Abstract
A method for processing a wafer in which: a wafer is obtained by slicing a semiconductor monocrystal ingot using a wire saw apparatus; one surface of the wafer is ground flat using, as a reference surface, a flat surface obtained by applying a curable material to the entirety of the other surface of the wafer; and the other surface of the wafer is ground flat using, as a reference surface, the one surface of the wafer that has been ground flat; wherein both surfaces of the wafer are flattened at the same time immediately after the wafer is sliced.
Description
Technical field
The present invention relates to the processing method of semiconductor wafer, particularly the surface of semiconductor wafer is carried out to the processing method of planarization.Further, this international application requires priority based on No. 029719th, the Japan's patent application (Patent 2013 – 029719) applied on February 19th, 2013, and the full content of Patent 2013 – 029719 is incorporated in this international application.
Background technology
Always, about semiconductor wafer, in order to utilize photomechanical process to make small pattern, require the planarization on the surface of wafer.Especially, the external waviness being called as " nanotopography (nanotopography) " has the composition of wavelength X=0.2 ~ 20mm and PV value (Peak to Valley value: peak-to-valley value) is the ripple of less than 0.1 ~ 0.2 μm, recently, propose for by reducing the technology that this nanotopography makes the flatness of semiconductor wafer improve.As the processing method for flattening of such wafer, disclose the processing method (such as, patent documentation 1) comprising following operation: by from the first surface attracting holding of wafer after ingot section after grinding is carried out in second face of horizontal holding surface to wafer of scratch diskette (chuck table), second of wafer attracting holding is carried out a grinding process of grinding at the first surface of above-mentioned horizontal holding surface to wafer; Then the resin working procedure of coating on second whole surface of a grinding process resin cover wafers; And then this resin working procedure of coating using second of wafer as datum level and attracting holding in above-mentioned horizontal holding surface, grinding is carried out to the first surface of wafer and after removing resin, carry out the operation of grinding using the first surface of wafer as second face of datum level to wafer.
Prior art document
Patent documentation
Patent documentation 1: Japanese Unexamined Patent Publication 2011 – No. 249652 publications (claim 1, paragraph [0008], [0028], Fig. 2).
Summary of the invention
The problem that invention will solve
In a grinding process shown in above-mentioned patent documentation 1, in order to remove distortion composition during section, wafer suction is remained in holding surface, thus, under the state of the smooth datum level after having elaborated the large ripple forcibly corrected and produce in slicing process, carry out the grinding of the wafer surface of side, non-adsorbed face.Therefore, when carrying out grinding under the state in wafer strain and discharge attracting holding after the grinding, the ripple not being implemented the wafer surface of the adsorption plane side of grinding process gets back to the state before adsorbing maintenance, this ripple is transferred to the wafer surface of the side, non-adsorbed face be flattened by grinding, as a result, the major part of ripple remains in wafer surface.
In the past, even if remain ripple in wafer surface, owing to carrying out grinding process in order to remove ripple under the state utilizing the resin being coated on wafer surface in resin working procedure of coating meticulously to manufacture smooth datum level afterwards, so, about the surface state of the wafer before resin working procedure of coating, be not regarded as problem.But, according to the experiment of the present inventors, recognize: even if carry out the such process (resin stickup grinding) being combined with resin coating process and grinding process recorded in patent documentation 1, the ripple of the wafer surface before resin working procedure of coating is large, the nanotopography quality of the wafer surface after mirror ultrafinish process neither be sufficient.
In addition, when utilizing Linear cut (wire saw) to cut into slices to single crystal rod in slicing process, it is usual while line (wire) the row supply in reciprocating comprises the slurry (working fluid) of floating outstanding abrasive particle while multiple semiconductor wafer is processed in the cut-out of semiconductor ingot, but, if be used in the bonded-abrasive line that outer peripheral face is fixed with abrasive particle, then compared with using the situation of floating outstanding abrasive particle, single crystal rod can be cut off at high speed.But recognize: when using bonded-abrasive line, processing infringement becomes large, the ripple that wafer surface after severance produces is also very large, therefore, there is the problem that nanotopography worsens more.
The object of the invention is to, by being carried out by the wafer alleviated the semiconductor wafer that flat surface grinding manufactures nanotopography excellent (being worth little) to ripple in a grinding process in secondary grinding process.
For solving the scheme of problem
The present inventors carry out to reach above-mentioned purpose wholwe-hearted discuss as a result, recognize and carry out the surface state (size of ripple) of the wafer before flat surface grinding according to coating soft material and the nanotopography quality comparison of semiconductor wafer that finally obtains is comparatively large and complete the present invention.Particularly, be, soft material is applied to carry out flat surface grinding after the ripple elements that the while that carry out grinding after just section, Double face grinding etc. not having datum level two-sided, planarization process relaxes in specific wavelength region may (10 ~ 100mm) in advance, thus, removing section wave pattern improves the level of quality of the nanotopography of wafer.
First viewpoint of the present invention is, wherein, is provided with following operation: slicing process, uses wire-electrode cutting device cut into slices to semiconductor single crystalline ingot and obtain the wafer of thin round plate shape; Two-sided planarization process operation, carries out planarization process to the two-sided of the wafer after slicing process simultaneously; Overlay formation process, forms smooth overlay to the overall coating curing material in a face of the wafer after two-sided planarization process operation; First flat surface grinding operation, is placed in platform in the mode that the wafer after planarization face is connected to the datum level of the platform of grinding attachment by wafer, then utilizes grinding attachment another face to wafer to carry out flat surface grinding; Overlay removal step, the overlay after a face removing flat surface grinding operation of wafer; And the second flat surface grinding operation, wafer is placed in platform by the mode being connected to the datum level of the platform of grinding attachment with another face being removed the wafer after overlay, then utilizes grinding attachment to carry out flat surface grinding to wafer face.
Second viewpoint of the present invention is the invention based on the first viewpoint, and wherein, wire-electrode cutting device adopts the slicing mode employing bonded-abrasive line.
3rd viewpoint of the present invention is the invention based on the first viewpoint, wherein, adopts two-sided lapping process or Double face grinding process in two-sided planarization process operation.
4th viewpoint of the present invention is the invention based on the first viewpoint, and the thickness being coated on the overlay of described wafer surface in described overlay formation process is 10 ~ 40 μm.
5th viewpoint of the present invention is the invention based on the first viewpoint, and when carrying out frequency resolution to the apparent height of the described wafer after two-sided planarization process operation, the amplitude of the ripple in the wavelength region may of below 100mm is the scope of less than 1.0 μm.
6th viewpoint of the present invention is the invention based on the second viewpoint, and when carrying out frequency resolution to the apparent height of the described wafer after two-sided planarization process operation, the amplitude of the ripple in the wavelength region may of below 100mm is the scope of less than 1.0 μm.
7th viewpoint of the present invention is the invention based on the 3rd viewpoint, and when carrying out frequency resolution to the apparent height of the described wafer after two-sided planarization process operation, the amplitude of the ripple in the wavelength region may of below 100mm is the scope of less than 1.0 μm.
8th viewpoint of the present invention is the invention based on the 4th viewpoint, and when carrying out frequency resolution to the apparent height of the described wafer after two-sided planarization process operation, the amplitude of the ripple in the wavelength region may of below 100mm is the scope of less than 1.0 μm.
Invention effect
According to the processing method of semiconductor wafer of the present invention, by carrying out planarization process to the two-sided of wafer after section simultaneously, thus the ripple of the wave-length coverage of nanotopography quality being given to impact can be reduced as much as possible, can providing of the superior semiconductor wafer of nanotopography quality be carried out.
Especially, though at the wire-electrode cutting device of use bonded-abrasive mode and cut-off ripple large wafer, also can reduce ripple as much as possible, can providing of the superior semiconductor wafer of nanotopography quality be carried out.
Accompanying drawing explanation
Fig. 1 is the figure of the outline operation of wafer processing method for illustration of embodiments of the present invention.
Fig. 2 is the schematic diagram of an example of the state from the wafer the wafer of wafer after flat surface grinding after section that embodiments of the present invention are shown and the device used each operation.
Fig. 3 is the schematic diagram of the state of the wafer illustrated in each operation of embodiments of the invention.
Fig. 4 is the schematic diagram of the state of the wafer illustrated in each operation of comparative example 1.
Fig. 5 is the nanotopography after the mirror ultrafinish of embodiment and comparative example 1,2.
Fig. 6 is the figure of the nanotopography after the mirror ultrafinish that embodiment and comparative example 1,2 be shown.
Fig. 7 is the figure of the frequency resolution result before the mirror ultrafinish that embodiment and comparative example 1,2 be shown.
Fig. 8 is the figure of the frequency resolution result after the mirror ultrafinish that embodiment and comparative example 1,2 be shown.
Embodiment
Then illustrate for implementing mode of the present invention based on accompanying drawing.
The present invention is the improvement utilizing following operation processing semiconductor wafer the surface of semiconductor wafer to be carried out to the processing method of planarization as shown in Fig. 1 (a) ~ (f): use wire-electrode cutting device cut into slices to semiconductor single crystalline ingot and obtain the slicing process of the wafer of thin round plate shape; Simultaneously to the two-sided two-sided planarization process operation of carrying out planarization process of the wafer after slicing process; The overall coating curing material in a face of the wafer after two-sided planarization process operation is formed to the overlay formation process of smooth overlay; In the mode that the wafer after planarization face is connected to the datum level of the platform of grinding attachment, wafer is placed in platform, then utilizes grinding attachment another face to wafer to carry out the first flat surface grinding operation of flat surface grinding; From the overlay removal step of the overlay after a face removing flat surface grinding operation of wafer; And in the mode that another face being removed the wafer after overlay is connected to the datum level of the platform of grinding attachment, wafer is placed in platform, then utilize grinding attachment to carry out the second flat surface grinding operation of flat surface grinding to wafer face.Although further, do not illustrate the operation of the outer rim to semiconductor wafer being carried out chamfering especially, the operation of chamfering is carrying out all can to which operation during after (f) from after Fig. 1 (a).
The characteristic structure of tool of the present invention is, is provided with the two-sided planarization process operation of simultaneously two surfaces of the wafer after slicing process being carried out to planarization process as shown in Fig. 1 (a) ~ (c) before overlay formation process.The planarization process while of not there is datum level two-sided by implementing before overlay formation process, thus remove the surperficial male portion of wafer two simultaneously, alleviate the ripple elements of the wavelength region may of below 100mm as much as possible.Thereby, it is possible to make the nanotopography characteristic of wafer surface improve, the thickness being coated on the overlay of wafer surface in overlay formation process also can be alleviated.
Embodiments of the present invention are explained with reference to Fig. 2.The state of the wafer 200 after firm section has been shown in Fig. 2 (a).Not shown known multi-wire saw (multi-wire saw) device can be used in a slice once to manufacture multiple wafer 200 from ingot.In Multi-wire cutting device, cross over the line being provided with multiple guide reel to the groove that line guides and being wound with many superfine steel wires for the roller making line rotate.Make roller High Rotation Speed, cut-off thing be pressed into the many lines exposed between guide reel and roller cut-off thing is cut into multiple devices.In cutting on line device, there are bonded-abrasive mode and floating outstanding abrasive particle mode according to the using method of the abrasive particle for cutting off.In bonded-abrasive mode, will the steel wire of the attachments such as diamond (diamond) abrasive particle be made to be used as line by evaporation etc.In floating outstanding abrasive particle mode, to line water be mixed with abrasive particle and finish slurry while use.About bonded-abrasive mode, because adhesion has the line of abrasive particle self to cut off cut-off thing, so break time is short and productivity ratio is superior.In addition, owing to not using slurry, so, do not need the discarded slurry being mixed with the chip after cut-out, therefore, genial and economical to environment.Use which kind of mode to be all possible in the present invention, but, preferably in environment, the favourable bonded-abrasive mode of economic aspect.Have again, when using bonded-abrasive Linear cut, the processing infringement that wafer surface is given is become large, the ripple that wafer surface after severance produces also becomes large, therefore, there is the problem that nanotopography worsens more, but, the processing method of the application of the invention, thus the semiconductor wafer that can manufacture nanotopography excellent (being worth little).
The state of the wafer 200 after the firm section cut off by bonded-abrasive Linear cut shown in Fig. 2 (a).In wafer 200 after section, produce the concavo-convex ripple 202, bending 203 that machining deformation (processing disturbed zone) 201, cyclic fluctuation are such because Linear cut cuts off processing.Conveniently, the upper surface bending Fig. 2 (a) of the convex side of 203 as wafer 200 is set to first surface 204, the lower surface bending Fig. 2 (a) of the concave side of 203 as wafer 200 is set to the second face 205.
Fig. 2 (b) shows the figure of an example of the lapping device 210 used in the grinding (lapping) of two-sided planarization process.The wafer 200 being arranged on processing carrier 211 is polished 2 platform clampings of device 210, while the slurry 214 comprising abrasive particle to be supplied between upper mounting plate 212 and lower platform 213 and to carry out pressurization while the axle 215,216 making to be arranged on the top of upper mounting plate 212 and the bottom of lower platform 213 rotates respectively in opposite direction with lower platform, thus, the abrasive particle utilizing slurry 214 to comprise carries out planarization process to first surface 204 and the second face 205 simultaneously.
After milling, wafer 200 is taken off from platform, take off from processing carrier 211.
About the wafer 200 through grinding step (two-sided planarization process), again planarization is carried out to the two-sided of wafer 200 by flat surface grinding operation (the first flat surface grinding and the second flat surface grinding) afterwards, therefore, about the processing capacity to wafer 200 (allowance) in grinding step, do not need to implement until by the planarization process of whole for the machining deformation 201 of the wafer 200 produced in slicing process removing, obviously known according to the embodiment described later, as long as become the mode of less than 1.0 μm to implement milled processed with the amplitude of the ripple in the wavelength region may of below the 100mm when carrying out frequency resolution to the apparent height of the wafer 200 after grinding.
Further, two-sided while planarization process be not limited to above-mentioned milled processed.Although be not particularly illustrated, but, also can use wafer 200 is assemblied in processing carrier 211 and be arranged on this wafer 200 upper and lower flat surface grinding grinding tool simultaneously to two surfaces of wafer 200 carry out grinding known Double face grinding process, when the upper and lower platform assembling of lapping device 210 comprise bonded-abrasive pad and in use or do not use when slurry 214 and utilize bonded-abrasive two surfaces of wafer 200 to be carried out to the known bonded-abrasive polishing process of grinding simultaneously.
At an example of the maintenance used in overlay formation process shown in Fig. 2 (c), press device 220.First, keep, press device 220 the flat board 222 of high planarization is fallen the curable material 221 becoming overlay.On the other hand, about wafer 200, by first surface 204 attracting holding of wafer 200 at holding unit 223 by presenting a theatrical performance as the last item on a programme 224, make by present a theatrical performance as the last item on a programme 224 move to below the second face 205 of wafer 200 is pressed into curable material 221.Afterwards, remove by present a theatrical performance as the last item on a programme 224 pressure, not make curable material 221 solidify the state that bending 203, the ripple 202 that remain in wafer 200 give strain in the second face 205 of wafer 200.Utilize this operation, the face of the curable material 221 contacted with dull and stereotyped 222 becomes by the face of high planarization, can using the first surface 205 of wafer 200 as the datum level 225 during grinding.
About the method at wafer 200 coating curing material 221, by to be made as upper surface in the second face 205 of wafer 200 curable material 221 drop on the second face 205 and rotate wafer 200 and curable material 221 be diffused into the spin-coating method on the second whole surface, face 205 or arrange half tone (screen) film in the second face 205 and curable material 221 be loaded in the method for the screen painting using scraper plate (squeegee) to fill on half tone film, and then utilize electrojet deposit (electric spray deposition) method the method etc. that the second whole surface, face 205 is sprayed is applied after applicator surface is contacted, press on by outside the method on the flat board 222 of high planarization, be not limited to said method, the one side of applications exploiting curable material 221 pairs of wafers 200 can also carry out the method for high planarization.About curable material 221, due to the soft material such as the preferred heat-curing resin in aspect, thermal reversibility resin, photoresist of the easy stripping after processing.Especially, photoresist due to the aspect not applying the stress caused by heat be also preferred.In the present embodiment, as curable material 221, use the resin utilizing UV to solidify.In addition, as the material of other concrete curable material 221, synthetic rubber, sticker (wax etc.) etc. can be enumerated.
About the thickness of curable material 221 being coated on wafer 200, the male portion on wafer 200 surface is larger (ripple elements of the wavelength region may of below 100mm is larger), then the more necessary thickness of the curable material 221 being coated on wafer 200 that makes increases, in the known scope being usually set in 50 ~ 150 μm, but, curable material 221 is high prices, there is use quantitative change due to curable material 221 many and cause the problem of the rising of manufacturing cost.
In the present invention, the planarization process while of not having datum level two-sided owing to implementing before overlay formation process, so the surperficial male portion of wafer 200 two is simultaneously removed, and the ripple elements of the wavelength region may of below 100mm is alleviated.Consequently, the thickness of the curable material 221 being coated on wafer 200 can be reduced, in the present case, the thickness of curable material 221 can be set in the scope of 10 ~ 40 μm.Further, when the thickness of curable material 221 is less than 10 μm, be subject to the impact of the male portion on wafer 200 surface, nanotopography deterioration.
At an example of the plane grinding apparatus 230 used in the first flat surface grinding operation shown in Fig. 2 (d).First, the datum level 225 of the curable material 221 made in overlay planarization process is arranged and attracting holding in plane grinding apparatus 230 vacuum work dish 231 by the datum level 232 of high planarization.Then, the platform 234 grinding tool 233 being arranged on a face is provided with at the upper surface of set wafer 200.Then, the first surface 204 of wafer 200 contacts with grinding tool 233, the axle 235 on the top of platform 234 rotates with the axle 236 of the bottom being arranged on vacuum work dish 231, the contact point rotating contact of the first surface 204 of grinding tool 233 and wafer 200, thus, grinding is carried out to the first surface 204 of wafer 200 and high planarization is carried out to first surface 204.
Overlay removal step shown in Fig. 2 (e).The curable material 221 of first surface 204 coated by the second face 205 of the wafer 200 of high planarization of wafer 200 the first flat surface grinding operation is peeled from wafer 200.Removing as the curable material 221 of overlay also can use solvent chemically to remove.
An example of the second flat surface grinding operation shown in Fig. 2 (f).The device of flat surface grinding is the device identical with the plane grinding apparatus 230 used in the first flat surface grinding operation.Using in the first flat surface grinding operation by the first surface 204 of the wafer 200 of high planarization as datum level 251, arrange and attracting holding at vacuum work dish 231 by the datum level 232 of high planarization.In the same manner as the first flat surface grinding operation, grinding is carried out until by high planarization to the second face 205 of wafer 200.As shown in Fig. 2 (g), wafer 200 two-sided all by high planarization.
Embodiment
Then, embodiments of the invention are explained together with comparative example.Further, about the wafer 200 for embodiment, comparative example 1,2, use bonded-abrasive mode wire-electrode cutting device wafer 200 from the diameter 300mm of silicon single crystal ingot under identical conditions.
< embodiment >
Embodiments of the invention shown in Figure 3.The manufacturing procedure of embodiment is described based on Fig. 3.By to wafer 200(Fig. 3 (a) after section) grind the two-sided of simultaneously grinding wafer 200, alleviate ripple 202(Fig. 3 (b)).UV curable resin 321 is coated on ripple 202 by the second face 205 of the wafer 200 after alleviating, using the face of the resin after the solidification of thickness 35 μm as datum level 225(Fig. 3 (c)).Flat surface grinding is carried out until ripple 202 disappears (until face of dotted line 331) (Fig. 3 (d)) as the first surface 204 of datum level 225 to the wafer 200 be attracted to maintain in the face of resin.Then, peel resin (Fig. 3 (e)), the first surface 204 of the wafer 200 after flat surface grinding is carried out flat surface grinding until the face (Fig. 3 (f)) of dotted line 351 as second face 205 of datum level 251 to the wafer 200 be attracted to maintain.Terminate whole operation, obtain the two-sided all by the wafer 200 of high planarization of wafer.Using wafer 200(Fig. 3 (g) of this wafer 200 as embodiment).
< comparative example 1>
Comparative example 1 shown in Figure 4.The manufacturing procedure of comparative example 1 is described based on accompanying drawing.UV curable resin 321 is coated on wafer 200(Fig. 4 (a) after section) the second face 205, using the face of the resin after the solidification of thickness 70 μm as datum level 225(Fig. 4 (b)).Flat surface grinding is carried out until the face (Fig. 4 (c)) of dotted line 421 as the first surface 204 of datum level 225 to the wafer 200 be attracted to maintain in the face of resin.Peel resin (Fig. 4 (d)), the first surface 204 of wafer 200 is carried out flat surface grinding until the face (Fig. 4 (e)) of dotted line 451 as second face 205 of datum level 251 to the wafer 200 be attracted to maintain.Using wafer 200(Fig. 4 (f) of the wafer 200 of this state as comparative example 1).
< comparative example 2>
About comparative example 2, using the wafer 200 of the wafer 200 after the grinding shown in Fig. 3 (b) of embodiment as comparative example 2.
< evaluation test 1>
What kind of impact is the surface configuration having investigated each wafer 200 obtained in embodiment and comparative example 1,2 give to the nanotopography in the wafer surface after the mirror ultrafinish process carried out afterwards.Particularly, first, each use double-side polishing apparatus for each wafer 200 obtained in embodiment and comparative example 1,2 is used as common mirror ultrafinish process to the rough lapping process that identical conditions is implemented on the surface of each wafer and the back side, afterwards, use single-sided grinding device to implement the fine finishining milled processed of identical conditions to each wafer surface, make the surface of each wafer 200 by the wafer after mirror ultrafinish.Fig. 5 is the nanotopography figure using the flatness determinator (KLA Tencor company: Wafersight2) of optical interference formula each wafer surface after mirror ultrafinish to be measured to height distribution (difference of height) of each wafer surface, is the measurement result of each wafer after mirror ultrafinish process is being carried out to filtering process to the figure after carrying out graphic by the measurement result of deep or light Color pair nanotopography after removing long wavelength's composition.Fig. 5 (d) is the figure of the difference of height representing the nanotopography shown in Fig. 5 (a) ~ (c), and dense color height is lower, and the denseest part is from centre-height – 20nm, and weak color height is higher, and the lightest part is from centre-height+20nm.Difference of height from minimum altitude to maximum height is 40nm.Measure further, the mensuration of nanotopography is arbitrary 3 of the outer rim of fixed wafer.Therefore, in nanotopography figure, make wafer under non-adsorbed state, indicate the difference of height on surface.
The result of embodiment shown in Fig. 5 (a).For roughly uniform concentration, known whole surperficial difference of height is few.Its reason can be considered, even if peel resin after the first surface 204 first surface 204 of wafer 200 being carried out to grinding and wafer 200 becomes high tabular surface, also the ripple 202 of particularly below the 50mm of below wave-length coverage 100mm is alleviated by grinding, therefore, the first surface 204 of wafer 200 maintains high tabular surface, even if the first surface 204 of wafer 200 is adsorbed as datum level 251 and carries out flat surface grinding to the second face 205 of wafer 200, also strain is not applied to wafer 200 when adsorbing the first surface 204 of wafer 200, therefore, second face 205 of the wafer 200 after the absorption release of the first surface 204 of wafer 200 does not produce ripple 202.
The result of comparative example 1 shown in Fig. 5 (b).The middle body of Fig. 5 (b) by some planarizations, but, remain ripple 202.Its reason is taken into account, although in Fig. 4 (c) after the firm first surface 204 to wafer 200 carries out flat surface grinding the first surface 204 of wafer 200 by high planarization, but, be applied to the stress relieved caused by ripple 202 of first surface 204 and the equilibrium of forces of answering caused with the ripple 202 by the second face 205 remaining in wafer 200 after peeling resin is disintegrated, therefore, first surface 204 deforms.And can consider, when the first surface 204 of wafer 200 is adsorbed as datum level 251, because absorption applies strain to wafer 200, even if carry out flat surface grinding to the second face 205 afterwards and become by the face of high planarization, when from absorption releasing wafer 200, the strain caused by absorption of the first surface 204 of wafer 200 is released and occurs ripple 202 in the second face 205 of wafer 200.
The result of comparative example 2 is shown in fig. 5 (c).Ripple 202 is remained in entirety.
< evaluation test 2>
What kind of the nanotopography of surface configuration on the wafer surface after mirror ultrafinish process investigating each wafer 200 in the same manner as evaluation test 1 give affects.In this test, manufacture multiple and embodiment, comparative example 1,2 the same terms wafer 200 respectively, for each execution and the mirror ultrafinish process (using the fine finishining milled processed of the rough lapping process+use single-sided grinding device of double-side polishing apparatus) of evaluation test 1 the same terms of the plurality of wafer 200, make the surface of each wafer 200 by the wafer after mirror ultrafinish.Fig. 6 uses the flatness determinator (KLA Tencor company: Wafersight2) of optical interference formula measure the nanotopography of each wafer surface to each wafer surface after mirror ultrafinish and represent the figure in each chart.Particularly, be to mirror ultrafinish after each wafer surface calculate maximum PV value according to each position (site) split with the border circular areas of diameter 2mm and by the maximum PV value representatively figure that draws of value in each maximum PV value calculated of each position.
Obviously known according to Fig. 6, difference of height is the scope of 5.4 ~ 7.2nm in an embodiment, is the scope of 9.0 ~ 10.7nm in comparative example 1, is the scope of 9.8 ~ 13.0nm in comparative example 2.The nanotopography that the wafer of embodiment can obtain surface integral is the face that the height of below 8nm is smooth.
< evaluation test 3>
Then, frequency resolution is carried out to the apparent height of each wafer 200 implemented before mirror ultrafinish process, the amplitude of the wavelength of investigation ripple elements.Its result shown in Figure 7.
Fig. 7 shows and uses the shape measuring apparatus (limited company KOBELCO scientific research: SBW) of electrostatic capacitance mode to the wafer (A) after the section shown in Fig. 3 (a), at the wafer (B) having carried out resin stickup grinding (comparative example 1) after section shown in Fig. 4 (f), the wafer (C) of (comparative example 2) after the grinding shown in Fig. 3 (b), and shown in Fig. 3 (g) carried out after grinding each of wafer (D) that resin pastes grinding (embodiment) carry out the frequency resolution of wafer surface height after result.In analytic method, in wafer surface elevation measurement data, cut away short wavelength's periodic component to bring more than the wavelength of 100mm less than 10mm, long wavelength's periodic component and carry out bandpass filtering treatment, ask for the amplitude of the wavelength of the ripple elements in the wave-length coverage of 10mm ~ 100mm.
Obviously known according to Fig. 7, the amplitude of maximum 1.7 μm is observed and the amplitude generation area observed more than 1 μm in wafer (A) after section, correspondingly, after milled processed (comparative example 2) wafer (C) in, also even if be 0.4 μm maximum and be the amplitude of less than 1 μm in the wave-length coverage of whole below 100mm, the known milled processed that can utilize significantly reduces amplitude.In addition, the known resin that carried out after grinding pastes the wafer (D) of grinding (embodiment) compared with having carried out resin and paste the wafer (B) of grinding (comparative example 1) after section, and amplitude is lowered further.
< evaluation test 4>
Then, after the mirror ultrafinish process that each execution for each wafer 200 is same with the mirror ultrafinish process carried out in evaluation test 1, frequency resolution is carried out to the apparent height of each wafer 200 after mirror ultrafinish, the amplitude of the wavelength of investigation ripple elements.Its result shown in Figure 8.
Fig. 8 shows and uses the shape measuring apparatus (KLA Tencor company: Wafersight2) of optical interference formula to carrying out the wafer (B) that grinding (comparative example 1) pasted by resin shown in Fig. 4 (f) after section, the wafer (C) of (comparative example 2) after the grinding shown in Fig. 3 (b), and shown in Fig. 3 (g) carried out after grinding each of wafer (D) that resin pastes grinding (embodiment) carry out mirror ultrafinish after wafer surface height frequency resolution after result.In analytic method, by long wavelength's periodic component of the gaussian filtering process excision ripple of cutoff 20mm in wafer surface elevation measurement data, Fourier transform is carried out to filtered wafer surface height, asks for the amplitude of the wavelength of the ripple elements in the wave-length coverage of below 100mm.
Obviously known according to Fig. 8, when having carried out resin after being used in grinding and having pasted wafer (D) of grinding (embodiment), in the result of the frequency resolution of the wafer surface after mirror ultrafinish process, the amplitude of the ripple of the wave-length coverage of 10 ~ 100mm is extremely good in below 0.4nm, on the other hand, observe when having carried out resin after being used in section and having pasted wafer (B) of grinding (comparative example 1) amplitude being 1.7nm to the maximum, observe when wafer (C) of (comparative example 2) after using milled processed the amplitude being 2nm to the maximum.
Utilizability in industry
The processing method of semiconductor wafer of the present invention can be used in the operation to the surface of the wafer after the section of the ingot such as silicon, gallium being carried out planarization.
The explanation of Reference numeral
200 wafers
221 curable material
232 datum levels.
Claims (8)
1. a processing method for semiconductor wafer, is characterized in that, comprises:
Slicing process, uses wire-electrode cutting device cut into slices to semiconductor single crystalline ingot and obtain the wafer of thin round plate shape;
Two-sided planarization process operation, carries out planarization process to the two-sided of the described wafer after described slicing process simultaneously;
Overlay formation process, forms smooth overlay to the overall coating curing material in a face of the described wafer after described two-sided planarization process operation;
First flat surface grinding operation, is placed in described in the mode that the wafer after described planarization face is connected to the datum level of the platform of grinding attachment by described wafer, then utilizes described grinding attachment another face to described wafer to carry out flat surface grinding;
Overlay removal step, removes the described overlay after described flat surface grinding operation from a face of described wafer; And
Second flat surface grinding operation, described wafer is placed in described by the mode being connected to the datum level of the platform of described grinding attachment with another face of the described wafer after being removed described overlay, then utilizes described grinding attachment to carry out flat surface grinding to described wafer face.
2. the processing method of semiconductor wafer according to claim 1, is characterized in that, described wire-electrode cutting device is the slicing mode employing bonded-abrasive line.
3. the processing method of semiconductor wafer according to claim 1, is characterized in that, described two-sided planarization process operation is two-sided lapping process or Double face grinding process.
4. the processing method of semiconductor wafer according to claim 1, is characterized in that, the thickness being coated on the overlay of described wafer surface in described overlay formation process is 10 ~ 40 μm.
5. the processing method of semiconductor wafer according to claim 1, it is characterized in that, when carrying out frequency resolution to the apparent height of the described wafer after described two-sided planarization process operation, the amplitude of the ripple in the wavelength region may of below 100mm is the scope of less than 1.0 μm.
6. the processing method of semiconductor wafer according to claim 2, it is characterized in that, when carrying out frequency resolution to the apparent height of the described wafer after described two-sided planarization process operation, the amplitude of the ripple in the wavelength region may of below 100mm is the scope of less than 1.0 μm.
7. the processing method of semiconductor wafer according to claim 3, it is characterized in that, when carrying out frequency resolution to the apparent height of the described wafer after described two-sided planarization process operation, the amplitude of the ripple in the wavelength region may of below 100mm is the scope of less than 1.0 μm.
8. the processing method of semiconductor wafer according to claim 4, it is characterized in that, when carrying out frequency resolution to the apparent height of the described wafer after described two-sided planarization process operation, the amplitude of the ripple in the wavelength region may of below 100mm is the scope of less than 1.0 μm.
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| PCT/JP2014/052540 WO2014129304A1 (en) | 2013-02-19 | 2014-02-04 | Method for processing semiconductor wafer |
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| Publication number | Publication date |
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| US9881783B2 (en) | 2018-01-30 |
| DE112014000276B4 (en) | 2022-03-31 |
| JPWO2014129304A1 (en) | 2017-02-02 |
| KR101638888B1 (en) | 2016-07-12 |
| US20150303049A1 (en) | 2015-10-22 |
| DE112014000276T5 (en) | 2015-10-15 |
| TWI515783B (en) | 2016-01-01 |
| TW201436018A (en) | 2014-09-16 |
| KR20150038541A (en) | 2015-04-08 |
| JP6187579B2 (en) | 2017-08-30 |
| WO2014129304A1 (en) | 2014-08-28 |
| CN104769704B (en) | 2017-10-13 |
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