JP4420023B2 - Semiconductor wafer measurement method, manufacturing process management method, and semiconductor wafer manufacturing method - Google Patents

Description

The present invention particularly relates to a method for measuring nanotopography of a semiconductor wafer, a method for managing a semiconductor wafer manufacturing process based on a result of the measurement, and a method for manufacturing a semiconductor wafer using the management method. .

  In general, a method for manufacturing a semiconductor wafer such as a silicon wafer includes a slicing process in which a single crystal ingot is sliced to be processed into a thin disc-shaped wafer, and a chamfering that chamfers the outer periphery to prevent the wafer from cracking or chipping. Process, lapping process to flatten the wafer, etching process to remove those processing distortions remaining on the wafer surface, polishing process to mirror the wafer surface, and contamination of abrasives and foreign matters adhering to the polishing process It has a washing process to remove things. In addition to these processes, processes such as heat treatment and grinding may be added as necessary, the process order may be changed, and the same process may be performed multiple times.

  In recent years, with high integration of semiconductor devices, processes such as STI (shallow trench isolation) have been adopted as fine device technology. Therefore, in order to form a circuit wiring pattern on the surface of a silicon wafer, an insulating film having a flatter and uniform thickness is required. For example, a method of flattening an insulating film by CMP (Chemical Mechanical Polishing) is a semiconductor device manufacturing method. Used in the process.

Conventionally, a minute uneven shape (hereinafter referred to as waviness) on the surface of a semiconductor wafer did not particularly affect the device manufacturing process. However, in STI, since the convex portion is selectively polished by CMP, there arises a problem that the thickness of the insulating film becomes non-uniform due to the waviness.
The swell is expressed using a parameter called nanotopography. Nanotopography is an index representing the flatness of the wafer surface, and represents waviness of the non-adsorbed wafer surface in a spatial wavelength region of 0.1 mm to several tens of mm.

  Nanotopography is generally measured by devices such as ADE Nanomapper, KLA Tencor NanoPro, Raytex Dynasearch, etc., but these devices are optical and use the surface reflection of the object to be measured. Therefore, the target wafer needs to be in a mirror state where the surface reflectance is high to some extent.

  Therefore, for wafers with low-reflectivity surfaces, such as sliced wafers and ground wafers, that have undergone an intermediate process in the wafer manufacturing method, the values measured by nanotopography with these measuring devices are low in accuracy and reliable. There wasn't.

  Recently, as a factor in the intermediate process of the wafer manufacturing method that deteriorates nanotopography, undulations appearing in the wire traveling direction when slicing a single crystal ingot with a wire saw, or ring-like undulations appearing in the double-head grinding process Etc. are mentioned.

As a manufacturing method for reducing such waviness, it has been proposed to perform a double-head grinding step, a double-side lapping step, and a double-side polishing step after slicing (see, for example, JP-A-2002-124490).
In this invention, the strained layer and macro waviness components formed on the surface at the time of wafer cutting are removed in the double-head grinding process, the flatness of the wafer is improved, and then double-sided lapping is performed. It is disclosed that the minute waviness of the surface generated in the process can be removed.

However, the size of the swell generated during slicing may vary greatly depending on the performance of the cutting device used, the wire specifications, and abnormalities such as cutting conditions and wire breakage during cutting.
Similarly, the size of the undulation generated in the double-head grinding process may vary depending on the relative positional relationship between the grindstone and the wafer and the sharpness of the grindstone.

Residual waviness generated on the wafer surface due to these factors is difficult to remove in the final mirror polishing process, so it appeared at the intermediate stage of the wafer manufacturing method such as the slicing process and double-head grinding process. Although it was necessary to monitor and manage the size of the undulation, the conventional measurement method using optical surface reflection has a problem that the undulation cannot be detected as described above.

  The present invention has been made in view of such problems, and nanotopography is measured even for a wafer having a low surface reflectance after an intermediate step of a semiconductor wafer manufacturing method, such as a slicing step or a grinding step. It aims at providing the measuring method which can be performed. Furthermore, the present invention provides a semiconductor wafer manufacturing process management method for managing intermediate processes such as a slicing process, a lapping process, a grinding process, and an etching process using this measuring method, and a semiconductor wafer manufacturing method using this management method. It is aimed at.

  The present invention has been made to solve the above problems, and provides a method for measuring a semiconductor wafer, wherein the nanotopography of a semiconductor wafer is measured using a capacitance type shape measuring apparatus. .

  The surface of the wafer manufactured through the slicing process, lapping process, grinding process, etching process, etc., which are intermediate processes of the semiconductor wafer manufacturing method, has low reflectivity, and an optical shape measuring device can measure with high accuracy. difficult. However, since the capacitance type shape measuring apparatus does not use optical surface reflection, nanotopography can be accurately measured on a wafer having such a low surface reflectance.

  As described above, it is preferable to perform band pass filtering on the Warp data obtained by measuring the semiconductor wafer using the capacitance type shape measuring apparatus.

  Furthermore, it is preferable that the Warp data is subjected to bandpass filtering by cutting off a wavelength band of at least a short wavelength side period of 1 mm or less and a long wavelength side period of 50 mm or more.

  If, for example, the surface of the wafer after the intermediate process in the semiconductor wafer manufacturing process is measured by such a method, nanotopography having a higher correlation with the surface state of the mirror-polished wafer after the final process can be evaluated.

  Using the semiconductor wafer measurement method described above, a semiconductor wafer that has undergone a semiconductor wafer manufacturing process is measured, and the manufacturing process is managed based on a result of the measurement. Provide a method.

  In addition, a semiconductor wafer manufacturing process management method is characterized in that the manufacturing process of the semiconductor wafer to be managed is one or more of a slicing process, a lapping process, a grinding process, and an etching process. To do.

  By using the measurement method of the present invention, it is possible to monitor the nanotopography of a wafer even with a low surface reflectance. Based on the measurement results, it is possible to quickly grasp abnormalities in the manufacturing process, etc. It can lead to improvement of the graphic.

  A semiconductor wafer manufacturing method using the semiconductor wafer manufacturing process management method is provided.

  According to the semiconductor wafer manufacturing method using the semiconductor wafer manufacturing process management method, a semiconductor wafer with improved nanotopography can be manufactured by grasping abnormalities in the manufacturing process at an early stage, thereby improving yield. it can.

As described above, according to the present invention, even in a semiconductor wafer having a low surface reflectance, it is possible to measure the remaining undulation and monitor the nanotopography. At this point, the semiconductor wafer manufacturing process can be managed to improve nanotopography, reduce manufacturing loss due to abnormal manufacturing processes, and improve yield, thus enabling efficient semiconductor wafer manufacturing. Become.

The wafer shape measured by the measuring method of the present invention. (A) Cross-sectional shape data, (b) Three-dimensional shape data. It is the schematic which shows the principle of the measuring method using an electrostatic capacitance type shape measuring apparatus. It is sectional drawing which shows the outline of the measuring method using the electrostatic capacitance type shape measuring apparatus. It is the figure which showed three methods as an extrapolation interpolation method in measurement data processing. Warp data obtained by measuring the wafer shape using a capacitance type shape measuring device. (A) Cross-sectional shape data, (b) Three-dimensional shape data. It is the data which measured the wafer shape after double-sided polishing process by Nanomapper. It is the schematic which shows the structure principle of a Michelson interferometer. It is the schematic which shows the measuring method of Nanomapper. It is the graph which investigated the correlation contribution rate of the data of the measurement by this invention which changed the short wavelength side period and the long wavelength side period of the cutoff wavelength band, and the data measured by Nanomapper. It is the graph which investigated the correlation contribution rate of the measurement data by this invention which fixed the short wavelength side period of the cutoff wavelength zone | band, and changed the long wavelength side period, and the data measured by Nanomapper. It is the graph which investigated the correlation contribution rate of the measurement data by this invention which fixed the long wavelength side period of the cutoff wavelength zone | band, and changed the short wavelength side period, and the data measured by Nanomapper. (A) Wafer shape measured by the measuring method of the present invention. (B) Wafer shape measured by Nanomapper. (A) The wafer shape which measured the same wafer with the measuring method of this invention, and Nanomapper. (B) A graph showing the correlation between the data of (a).

Hereinafter, although this invention is demonstrated in detail, this invention is not limited to these.
The present inventor wants to detect the waviness detected in the semiconductor wafer after the mirror polishing process, which is the final process of the semiconductor wafer manufacturing method, at the time after the intermediate process, for example, double-headed grinding. If the long-period component and the short-period component are removed from the Warp data obtained by measuring the surface of the wafer or the like after the process using a capacitance type shape measuring apparatus with a band-pass filter, the swell (nanotopography) The present invention has been completed.
Further, it was found that the value of nanotopography obtained from the shape data of the wafer surface after the intermediate process obtained as described above substantially coincides with the nanotopography of the wafer subjected to mirror polishing. .

FIG. 2 shows the principle of a measuring method using a capacitance type shape measuring apparatus.
In general, capacitance-type shape measurement is performed based on the thickness of an object to be measured. The probe 1 and the object to be measured (silicon wafer) 2 form a capacitance, and the capacitance changes with a change in the distance D. The capacitance-voltage conversion circuit outputs a voltage proportional to D and measures the displacement. Further, as shown in FIG. 3, when the probe 1 of the displacement meter is fixed to both sides of the object to be measured 2 at a known distance c and the surface displacements a and b are measured, the wafer thickness t can be expressed by the equation t = c− It is obtained by (a + b).

  In the present invention, the analysis is performed using the surface displacement a or b instead of using the wafer thickness t. This is because a parameter called nanotopography is measured with reference to the surface of the silicon wafer. Data obtained by measuring the surface displacement a or b is called Warp data.

  For the Warp data, it is preferable to execute spatial bandpass filtering by specifying three parameters of a short wavelength side period, a long wavelength side period, and a shape extrapolation method.

For the wavelength band with a short wavelength side period of 1 mm or less, the influence of the grinding streak is great, and the grinding streak is removed by the final mirror polishing step, so it is not necessary for evaluation of the remaining waviness after the mirror polishing step. Therefore, it is preferable to cut off a wavelength band having a short wavelength side period of 1 mm or less.
The wavelength band having a long wavelength side period of 50 mm or more is not a measurement object of nanotopography. Therefore, it is preferable to cut off a wavelength band having a long wavelength side period of 50 mm or more.
The extrapolation method extrapolates the outer shape of the wafer where no data exists, and as shown in FIG. 4, there are three types of linear interpolation (Linear), line symmetry (Mirror), and point symmetry (Point). There is an interpolation method. Generally, line symmetry is adopted.

  Here, the example which measured the wafer surface after a double-head grinding process using the shape measuring apparatus by the electrostatic capacitance system by Kobelco Kaken company is shown in FIG. 1, FIG. The sample wafer used is a single crystal silicon wafer having a diameter of 300 mm manufactured by the CZ method. FIG. 5 shows Warp data corresponding to the surface displacement a. FIG. 1 shows an example of measurement based on the Warp data, in which a wavelength band with a short wavelength side period of 3 mm or less and a long wavelength side period of 50 mm or more is cut off, bandpass filtered, and line symmetric extrapolation is performed. It is.

As described above, comparing the Warp data with the data obtained by bandpass filtering the Warp data, it can be seen that the inflection point is emphasized in the latter, and the waviness on the wafer surface is simulated well.
Further, FIG. 6 shows a map of nanotopography measured by an optical measuring device Nanomapper after performing double-side polishing on this wafer.
When the contribution rate, which is the square of the correlation coefficient, was investigated for the measurement results of FIG. 5 and FIG. 6, it was found that there was a good correlation with a contribution rate of 0.6. Further, when the contribution rate was similarly investigated for the measurement result of FIG. 1 and the measurement result of FIG. 6, it was found that there was a very good correlation with a contribution rate of 0.7.

  Moreover, the figure shows the data obtained by bandpass filtering Warp data obtained by measuring the wafer after the double-head grinding process using a capacitance-type shape measuring device using a single crystal silicon wafer having a diameter of 300 mm manufactured by the CZ method as a sample wafer. FIG. 12 (b) shows data measured by Nanomapper on a mirror wafer obtained by sequentially processing the wafer in the subsequent steps of a surface grinding process, an etching process, and a double-side polishing process. Comparing FIG. 12 (a) and FIG. 12 (b), the wafer shape data obtained by measuring the wafer after the double-head grinding process by the measurement method of the present invention and the wafer after the final process were measured by Nanomapper. It can be seen that there is a good correlation with the wafer shape data.

  As described above, the data obtained by measuring the wafer after the intermediate process of the semiconductor wafer manufacturing method by the inspection using the measuring method of the present invention is obtained by using the optical measuring device for the wafer after mirror polishing. Since it coincides with the measured nanotopography data, the nanotopography of the wafer surface after the final mirror polishing step can be predicted by performing the measurement of the present invention after the intermediate step.

  A method for managing the manufacturing process of the semiconductor wafer using the measurement method will be described. In this management method, a wafer is extracted according to a set standard, and the wafer is measured using the measurement method. When the measurement result exceeds a set pass / fail standard value, feedforward and feedback are performed to the manufacturing process.

(Sampling measurement)
In general, the sampling measurement is performed for one lot (= ingot unit) of about 100 to 250 silicon wafers. In the case of a wafer after the slicing process, the wafer is extracted from the three cutting positions K, C, and P. In the case of the wafer after the double-head grinding process, 1 to 3 wafers are extracted from 25 to 50 wafers. The wafer is measured using the above measurement method.

(Defect judgment)
Based on the obtained measurement result, the wafer pass / fail standard value is set to 1.5 μm or less, and the wafer is judged to be defective. As a result of the sampling measurement, if the total number exceeds the acceptance / rejection reference value, the lot is determined to be defective (lot out) and fed back to the manufacturing process. Even when a defective product is generated, if at least one sheet is determined to pass, feedback to the manufacturing process and feedforward to the final inspection process are performed.

(Feedback to manufacturing process)
As an example, a case where the measurement result is fed back to the slicing process and the double-head grinding process will be described.
The condition for the slicing process cannot be basically adjusted, and analysis is performed for improvement. Analyzes by layer the materials such as slice machines, wires, main rollers, etc. where defects occurred.
The double-head grinding process is adjusted until it reaches a reference value by shifting (adjusting the position of the grindstone on the grindstone axis relative to the wafer) and tilting (adjusting the inclination of the grindstone surface relative to the wafer surface). In some cases, the left and right flow rate of the static pressure pad holding the wafer is adjusted. If it still cannot be adjusted within the range, replace the carrier and grindstone.

(Feed forward to final inspection process)
When nanotopography is set as a required item of a product, the total number of wafers is measured and selected in a final inspection process using Nanomapper after the mirror polishing process of the final process. When nanotopography is not set in the requirement item of the product, only 25 sheets are measured per lot, and feedback is made to the process.

If such a management method is followed, the slicing process, lapping process, grinding process, etching process, etc., which are intermediate processes of the semiconductor wafer manufacturing method, can be managed, and early measures such as reviewing and improving manufacturing conditions are possible. become.
Furthermore, the quality of the wafer can be managed in an intermediate process before the mirror polishing process, so that product loss can be reduced and yield can be improved.

  If a semiconductor wafer is manufactured by using the above-described semiconductor wafer manufacturing process management method, a semiconductor wafer with improved nanotopography can be manufactured by grasping abnormalities in the manufacturing process at an early stage. Manufacture is possible.

  Here, the Nanomapper manufactured by ADE, which is generally used for the measurement of the nanotopography of the mirror wafer, will be briefly described. Nanomapper uses a Michelson interferometer, and the configuration of the Michelson interferometer is shown in FIG. First, the light emitted from the light source 3 becomes parallel light by the collimator lens 4 and is divided into two optical paths (amplitude division) by the half mirror 8. Each of the two light beams is reflected by the reference mirror 10 and the object to be measured 2 (referred to here as a silicon wafer), is returned to the original optical path and is superimposed by the half mirror 8, and is interfered by the CCD camera 6. An image (FIG. 6) is captured. One reference mirror 10 is a flat surface (reference surface) polished with high accuracy, and the shape of the test surface of the other (measurement object 2) is measured. The silicon wafer in-plane data captured by the above interferometer is subjected to noise removal and other processing, then the window size determined by the setting is moved within the wafer plane, and the PV value in the window (maximum value-minimum value) ) Is replaced with the center value of the window to obtain nanotopography data.

  The window size is generally 0.5 mm to 10 mm, and a measurement example is shown in FIG. The selection of the window size 11 depends on the wafer standard of the customer (device manufacturer). However, in the management of nanotopography in the intermediate process, which is the object of the present invention, experience is considered in consideration of the correction by mirror finishing in the polishing process. In particular, the window size 11 is often 10 mm.

  Next, the optimum cut-off wavelength band for bandpass filtering in the present invention was examined. A single crystal silicon wafer having a diameter of 300 mm manufactured by the CZ method was used as a sample. The 25 wafers after the double-head grinding process were measured by bandpass filtering using the measurement method of the present invention with different combinations of the short wavelength side period and the long wavelength side period cut off wavelength bands. The mirror wafer obtained by sequentially processing in the surface grinding step, the etching step, and the double-side polishing step was measured with the Nanomapper (window size: 10 mm), and the correlation was investigated by making the PV values of the two correspond one-to-one. The correlation was compared with the contribution rate (the square of the correlation coefficient).

  As a result, the combination that cuts off the wavelength band of 1 mm or less in the short wavelength side period (high pass filter) and cuts off the wavelength band of 50 mm or more in the long wavelength side period (low pass filter) has the highest contribution ratio of 0.73. It was found that there was a correlation (FIG. 9). Moreover, the combination which cuts off the wavelength band of 3 mm or less in the short wavelength side period (high pass filter) and cuts off the wavelength band of 50 mm or more in the long wavelength side period (low pass filter) has a contribution ratio of 0.65, and then It was found that there was a high correlation, and it was possible to narrow down the rough wavelength band for favorable bandpass filtering. From this result, it can be seen that the shape component on the short period side of 1 mm or less is easily removed by the double-side polishing step after double-head grinding, and the shape component on the long period side remains as it is.

  Based on this result, the range of each preferable cutoff wavelength band was investigated regarding the short wavelength side period and the long wavelength side period. First, the wavelength of the short wavelength side period (high pass filter) is fixed to the optimum 1 mm, and the wavelength of the long wavelength side period (low pass filter) is subjected to bandpass filtering in 8 conditions in the range of 30 mm to 80 mm. The correlation was investigated (Fig. 10). As a result, the wavelength range of 40 mm to 60 mm with a long wavelength side period (low-pass filter) with a contribution ratio of 0.5 or more is a preferable range, and further, the range of 45 mm to 55 mm with a contribution ratio of 0.6 or more is more preferable. I found out. Next, the wavelength of the long wavelength side period (low pass filter) is fixed to the optimum 50 mm, and the wavelength of the short wavelength side period (high pass filter) is subjected to 7 conditions and band pass filtering in the range of 0.1 mm to 4 mm, The correlation was investigated in the same manner as above (FIG. 11). As a result, the wavelength range of 0.1 mm to 3 mm with a short wavelength side period (high pass filter) with a contribution ratio of 0.5 or more is a preferable range, and the range of 1 mm to 3 mm with a contribution ratio of 0.6 or more is more preferable. I found out.

From the above results, for the Warp data obtained by measuring a semiconductor wafer using a capacitance type shape measuring device, the wavelength band with a short wavelength side period of 1 mm or less and a long wavelength side period of 50 mm or more is cut off. It was found that the measurement method using bandpass filtering is optimal.

  Examples of the present invention will be described below, but the present invention is not limited thereto.

Hereinafter, the present invention will be specifically described by way of examples.
Example 1
When processing Warp data obtained by measuring a wafer using a capacitance-type shape measuring apparatus, an optimum combination of cutoff wavelength bands with a short wavelength side period of 1 mm or less and a long wavelength side period of 50 mm or more is used. An experiment was conducted to confirm the effectiveness of the measuring method of the present invention.
A single crystal silicon wafer having a diameter of 300 mm manufactured by the CZ method was used as a sample wafer. The wafer after the double-head grinding process was measured with a capacitance-type shape measuring device, the obtained warp data was subjected to the bandpass filtering of the optimum value, and the result of the wafer cross-section measurement was shown in FIG. Shown in Then, for the mirror surface wafer obtained by sequentially processing the wafer in the subsequent steps of the surface grinding step, the etching step, and the double-side polishing step, the result of measuring the wafer cross section with Nanomapper is shown in FIG. 12 (b). Show. When comparing FIGS. 12A and 12B, it was confirmed that almost the same wafer shape was shown and a good correlation was obtained.

From the above results, the wafer shape obtained by applying the optimum bandpass filtering to the Warp data obtained from the wafer after the double-head grinding process using the capacitance type shape measuring device, and the wafer on both sides It was found that the wafer shapes measured by Nanomapper after polishing were in good agreement. Therefore, if the measurement method of the present invention is used, it is possible to predict the nanotopography of the wafer surface after the final mirror polishing process in the intermediate process of the semiconductor wafer manufacturing method. It was confirmed that it contributed to the management of the intermediate process of the manufacturing method.

(Example 2)
A single crystal silicon wafer having a diameter of 300 mm manufactured by the CZ method was used as a sample wafer. About 25 mirror wafers, wafer shape obtained by applying the above bandpass filtering to the Warp data obtained by measuring with a capacitance type shape measuring device, and wafer obtained by measurement using Nanomapper Comparison with the shape was performed. As shown in FIG. 13 (a), the PV values of the shape of the central portion of the wafer measured by each measurement method were made to correspond one-to-one, and the correlation was investigated and compared. As a result, as shown in FIG. 13B, a very good correlation with a contribution rate of 0.90 was obtained.

From the above results, in the shape data measurement of the mirror wafer, the shape data obtained by the measurement method of the present invention almost coincided with the shape data obtained by the optical measuring device. Therefore, it was confirmed that the measurement method of the present invention is also effective for a mirror surface wafer.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and this embodiment has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present embodiment. It is included in the technical scope of the invention.

Claims (4)

Nanotopography of a semiconductor wafer is measured using a capacitance-type shape measuring device, and for the obtained Warp data, the wavelength band of at least a short wavelength side period of 1 mm or less and a long wavelength side period of 50 mm or more is cut off. Bandpass filtering . A method for measuring a semiconductor wafer. A method for measuring a semiconductor wafer according to claim 1, wherein a semiconductor wafer that has undergone a semiconductor wafer manufacturing process is measured, and the manufacturing process is managed based on a result of the measurement. Management method of manufacturing process. 3. The semiconductor wafer manufacturing process according to claim 2 , wherein the semiconductor wafer manufacturing process to be managed is one or more of a slicing process, a lapping process, a grinding process, and an etching process. Management method. The method of manufacturing a semiconductor wafer using the management method of the process of manufacturing the semiconductor wafer according to claim 2 or claim 3.

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