CN104752198B - Substrate lithographic method - Google Patents

Substrate lithographic method Download PDF

Info

Publication number
CN104752198B
CN104752198B CN201310738381.9A CN201310738381A CN104752198B CN 104752198 B CN104752198 B CN 104752198B CN 201310738381 A CN201310738381 A CN 201310738381A CN 104752198 B CN104752198 B CN 104752198B
Authority
CN
China
Prior art keywords
substrate
etch step
main etch
etching
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310738381.9A
Other languages
Chinese (zh)
Other versions
CN104752198A (en
Inventor
田成益
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing North Microelectronics Co Ltd
Original Assignee
Beijing North Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing North Microelectronics Co Ltd filed Critical Beijing North Microelectronics Co Ltd
Priority to CN201310738381.9A priority Critical patent/CN104752198B/en
Publication of CN104752198A publication Critical patent/CN104752198A/en
Application granted granted Critical
Publication of CN104752198B publication Critical patent/CN104752198B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The substrate lithographic method that the present invention is provided, it comprises the following steps:First main etch step, the etching selection ratio for improving mask, wherein, etching gas are used as using inert gas;Second main etch step, mask pattern is modified by using relative superiority or inferiority power and the base width of substrate is adjusted;3rd main etch step, by the way that lower power is reduced into lowest power value by default peak power value by pre-defined rule within the predetermined process time of this step, to reduce flex point height;4th main etch step, the etching selection ratio of substrate is improved by using low power;Over etching step, substrate pattern is modified by using relative superiority or inferiority power.The substrate lithographic method that the present invention is provided, it can not only realize that the mask for different-shape obtains preferable substrate pattern, and can increase process window, so as to obtain preferably etching height and base width by adjusting parameters.

Description

Substrate lithographic method
Technical field
The present invention relates to microelectronics technology, more particularly to a kind of substrate lithographic method.
Background technology
PSS(Patterned Sapp Substrates, graphical sapphire substrate)Technology is one generally used at present Plant and improve GaN(Gallium nitride)The method of the light extraction efficiency of base LED component.During PSS techniques are carried out, it is generally in substrate Upper growth dry etching mask, and mask is carved by figure using photoetching process;Then using ICP technologies etching substrate table Face, to form the figure of needs, then removes mask, and using growing GaN film on the substrate surface of epitaxy technique after etching. The light-out effect of LED component, section shape can be influenceed due to etching the substrate pattern obtained and etching height using ICP technologies It is approximately that the substrate pattern of quadrantal (spherical) triangle is used with superior light extraction efficiency by increasing producer.In addition, in order to enter One step improves light-out effect, and while the substrate pattern for obtaining quadrantal (spherical) triangle is met, higher etching is pursued by many producers Highly.
At present, inductively coupled plasma is being used(Inductively Coupled Plasma, hereinafter referred to as ICP)If For when being performed etching to substrate surface, generally using BCl3(Boron chloride)As etching gas, and PSS etching technics includes two Step, i.e.,:Main etch step and over etching step.Wherein, main etch step is used for the etch rate for controlling technique and etching is selected Ratio is selected, to obtain required Sidewall Height and base width.Its typical technological parameter is:The chamber pressure of reaction chamber is 2 ~5mT;Upper power is 1000~2500W;Lower power is 100~700W;BCl3Flow be 60~200sccm;Process time For 15~40min.Over etching step is used to adjust substrate pattern, is mainly used in modifying the sidewall profile of substrate.Its typical work Skill parameter is:The chamber pressure of reaction chamber is 1.5~3mT;Upper power is 1000~2500W;Lower power is 500~800W; BCl3Flow be 60~100sccm;Process time is 10~20min.Using above-mentioned technological parameter obtain substrate pattern such as Shown in Fig. 1, as seen from the figure, the substrate side wall obtained using above-mentioned substrate lithographic method(The hypotenuse of quadrantal (spherical) triangle)It is rounder and more smooth, It is not smooth enough.Although the modification dynamics to substrate pattern can be increased using the process time of extension over etching step, to obtain The etch topography of quadrantal (spherical) triangle is obtained, still, this can not only make Sidewall Height(That is, etching height)Reduce with base width, and And process efficiency can be also reduced, cause production capacity to decline.
Therefore, in the prior art, it is proposed that a kind of substrate lithographic method, main etch step is further separated into three points by it Step, and by each substep mutually compensate for obtain preferable substrate pattern to realize.Specifically, the substrate lithographic method is used BCl3And H2Mixed gas be used as etching gas;Also, in main etch step, the first substep:Using higher upper power and The shorter process time(1~3min), for modifying mask(Such as photoresist);Second substep:In the starting stage using higher Lower power, and lower power is gradually reduced by the way of linear reduction with the increase of process time, to reduce as much as possible The height of flex point, while ensureing higher etch rate.Second substep is when above-mentioned flex point just starts to occur or will appear from Terminate, start simultaneously at the substep of progress the 3rd, the 3rd substep:Using relatively low lower power, to increase etching selection ratio.In over etching In step, substrate pattern is modified using relatively low lower power, so as to obtain the substrate of the more straight quadrantal (spherical) triangle of hypotenuse Pattern.
Although above-mentioned substrate lithographic method can obtain quadrantal (spherical) triangle by carrying out the modification of multiple substeps to substrate Substrate pattern, still, it is inevitably present problems with actual applications, i.e.,:The substrate lithographic method has to Ask the pattern of mask to obtain preferable substrate pattern for trapezoid, and be directed to the mask of other patterns because its debugging window is non- It is often small and can not often obtain the substrate pattern of quadrantal (spherical) triangle.If for example, using mask pattern as shown in Figure 2 A, through the base As shown in Figure 2 B, as seen from the figure, the substrate side wall of acquisition is asymmetric, on the side wall on the left side for the substrate pattern that piece lithographic method is obtained It is clearly present turning.In addition, the substrate lithographic method is very limited to the adjustable range of the base width of substrate, it is difficult to improve bottom Hem width degree.
The content of the invention
It is contemplated that at least solving one of technical problem present in prior art, it is proposed that a kind of substrate etching side Method, it can not only realize that the mask for different-shape obtains preferable substrate pattern, and can increase process window, So as to obtain preferably etching height and base width by adjusting parameters.
To realize that the purpose of the present invention provides a kind of substrate lithographic method, comprise the following steps:
First main etch step, the etching selection ratio for improving mask, wherein, etching gas is used as using inert gas Body;
Second main etch step, mask pattern is modified by using relative superiority or inferiority power and the base width of substrate is adjusted;
3rd main etch step, by within the predetermined process time of this step by pre-defined rule will under power by default Peak power value is reduced to lowest power value, to reduce flex point height;
4th main etch step, the etching selection ratio of substrate is improved by using low power;
Over etching step, substrate pattern is modified by using relative superiority or inferiority power.
It is preferred that, in second, third and the 4th main etch step, the etching gas bag being passed through into reaction chamber Include BCl3Or BCl3And CHF3Mixed gas or BCl3And H2Mixed gas or BCl3、CHF3And H2Gaseous mixture Body.
It is preferred that, in first main etch step, the inert gas includes argon gas, helium or nitrogen.
It is preferred that, in first main etch step, the span of process time is in 1~3min.
It is preferred that, in second main etch step, the span of the lower power is in 400~600W.
It is preferred that, in second main etch step, the span of process time is in 3~6min.
It is preferred that, in the 3rd main etch step, the pre-defined rule is:In the predetermined process time of this step It is interior, lower power is reduced to lowest power value by default peak power value by the relation of piecewise function or linear function.
It is preferred that, the span of the peak power value is in 350~450W;The span of the lowest power value exists 200~300W.
It is preferred that, just occurred in the flex point or stopped the 3rd main etch step when will occur, start simultaneously at into Row the 4th main etch step.
It is preferred that, in the 4th main etch step, the lower power span is in 100~200W.
The invention has the advantages that:
The substrate lithographic method that the present invention is provided, its by the way that main etch step is further divided into four substeps, this each Substep is by cooperating, i.e., by adjusting the parameters such as the upper power in each substep, lower power and process time, to regulate and control Pattern, etching height and the base width of substrate, this can not only realize that the mask for different-shape is obtained preferably Substrate pattern, and can increase process window, so as to obtained by adjusting parameters preferably etching height and Base width.
Brief description of the drawings
Fig. 1 is the scanning electron microscope (SEM) photograph of the substrate pattern obtained using a kind of existing substrate lithographic method etching substrate;
The scanning electron microscope (SEM) photograph for the mask pattern that Fig. 2A is used by existing another substrate lithographic method;
Fig. 2 B are the substrate pattern obtained for the mask pattern in Fig. 2A through existing another substrate lithographic method Scanning electron microscope (SEM) photograph;
The FB(flow block) for the substrate lithographic method that Fig. 3 provides for the present invention;
Fig. 4 A are the illustraton of model of the theoretical substrate pattern obtained through the second main etch step;
Fig. 4 B are the scanning electron microscope (SEM) photograph of the actual substrate pattern obtained through the second main etch step;
Fig. 5 A are the illustraton of model of the theoretical substrate pattern obtained through the 3rd main etch step;
Fig. 5 B are the scanning electron microscope (SEM) photograph of the actual substrate pattern obtained through the 3rd main etch step;
Fig. 6 A are the illustraton of model of the theoretical substrate pattern obtained through the 4th main etch step;
Fig. 6 B are the scanning electron microscope (SEM) photograph of the actual substrate pattern obtained through the 4th main etch step;
Fig. 7 A are the illustraton of model of the theoretical substrate pattern obtained by etch step;And
Fig. 7 B are the scanning electron microscope (SEM) photograph of the actual substrate pattern obtained by etch step.
Embodiment
To make those skilled in the art more fully understand technical scheme, come below in conjunction with the accompanying drawings to the present invention The substrate lithographic method of offer is described in detail.
In following first to fourth main etch steps, substrate is etched using following processes, and is only the technique used Parameter is different.Etching substrate detailed process be, i.e.,:Etching gas are passed through to reaction chamber, and open excitation power supply(For example penetrate Frequency power), excitation power supply is applied with power to reaction chamber, so that the etching gas in reaction chamber excite to form plasma Body;Open grid bias power supply(Wherein, the first main etch step can keep grid bias power supply to close), under grid bias power supply applies to substrate Power, so that plasma etching substrate, until etching predetermined etching depth to substrate.Technological parameter mainly includes etching gas Species and flow, upper power, lower power, process atmospheric pressures(That is, the chamber pressure of reaction chamber)And etch period etc..This Outside, the detailed process of over etching step and above-mentioned main etch step are similar, are also only that used technological parameter is different, to rise To the effect of modification substrate pattern.
Fig. 3 is the FB(flow block) of substrate lithographic method provided in an embodiment of the present invention.Referring to Fig. 3, the substrate etching side Method comprises the following steps:
First main etch step, the etching selection ratio for improving mask, wherein, etching gas is used as using inert gas Body;
Second main etch step, mask pattern is modified by using relative superiority or inferiority power and the base width of substrate is adjusted;
3rd main etch step, by within the predetermined process time of this step by pre-defined rule will under power by default Peak power value is reduced to lowest power value, to reduce flex point height;
4th main etch step, the etching selection ratio of substrate is improved by using low power;
Over etching step, substrate pattern is modified by using relative superiority or inferiority power.
By the way that main etch step is further divided into four substeps, i.e.,:Above-mentioned first to fourth main etch step, this each Substep is by cooperating, i.e., by adjusting the parameters such as the upper power in each substep, lower power and process time, to regulate and control Pattern, etching height and the base width of substrate, this can not only realize that the mask for different-shape is obtained preferably Substrate pattern, and can increase process window, so as to obtained by adjusting parameters preferably etching height and Base width.
The function and parameter to above-mentioned first to fourth main etch step and over etching step are described in detail below.
Specifically, in the first main etch step, inert gas includes argon gas, helium or nitrogen.Due to by indifferent gas The plasma of body formation can radiate characteristic ray, and this can improve the etching selection ratio of mask, so as to be follow-up acquisition The pattern and raising etching efficiency of quadrantal (spherical) triangle lay the first stone.It is preferred that, the span of process time is in 1~3min. In addition, in this step, employing higher chamber pressure, and remain off grid bias power supply, so that the pattern of mask Keep constant with size, i.e. in first main etch step, be only the etching selection ratio for playing a part of improving mask, and Mask is not performed etching.It is preferred that, the span of chamber pressure is in 15~25mT;The span of lower power is 250 ~350W;The span of the flow of inert gas is in 45~55sccm.
In the second main etch step, mask pattern is modified by using higher lower power and the bottom of substrate is adjusted Hem width degree.It is preferred that, the span of lower power is in 400~600W;The span of process time is in 3~6min;Upper power Span in 1400~2400W;The etching gas being passed through into reaction chamber include BCl3Or BCl3And CHF3It is mixed Close gas or BCl3And H2Mixed gas or BCl3、CHF3And H2Mixed gas, wherein, BCl3And CHF3Mixing Gas is used as etching gas best results, it is preferred that BCl3Flow span in 60~200sccm;CHF3Flow Span is in 5~100sccm;The span of chamber pressure is in 1.5~5mT.As illustrated in figures 4 a and 4b, it is respectively through second The illustraton of model and the scanning electron microscope (SEM) photograph of actual substrate pattern for the theoretical substrate pattern that main etch step is obtained.Comparison diagram 4A and 4B can Know, the actual substrate pattern obtained is consistent with the model of theoretical substrate pattern.
In the 3rd main etch step, by within the predetermined process time of this step by pre-defined rule will under power by pre- If peak power value be reduced to lowest power value, come reduce flex point height.So-called flex point, refers to the increasing with etch period Plus, two relative side walls of mask on substrate surface can cross-direction shrinkage toward each other, cause the width of mask to become narrow gradually, this So that substrate side wall occurs flex point because of the cross-direction shrinkage of mask, and if make mask premature contraction, flex point height reduction can be made. By the way that by pre-defined rule gradually or the lower power of time segment reduction, flex point height can be gradually lowered, so as to etch shape Into more smooth substrate side wall(That is, the hypotenuse of the quadrantal (spherical) triangle of formation is more straight).In addition, by by pre-defined rule gradually or point The lower power of period reduction, can also effectively adjust Sidewall Height and base width, so that the two meets technological requirement.
It is preferred that, above-mentioned pre-defined rule is specifically as follows:Within the predetermined process time of this step, by piecewise function or Lower power is reduced to lowest power value by the relation of linear function by default peak power value.It is preferred that, peak power value Span is in 350~450W;The span of the lowest power value is in 200~300W.For example, the predetermined technique of this step Time is 7.5min, and the peak power value of lower power is 500W, and lowest power value is 250W, and carries out the 3rd main etch step certainly It has been started that, often once descend power by 1.5min reductions, co-falling is low four times.It is preferred that, lower power is reduced to by 500W for the first time 400W;350W is reduced to by 400W for the second time;Third time is reduced to 300W by 350W;4th time 250W is reduced to by 300W.Need It is noted that be reduced to by lower power by default peak power value during the entire process of lowest power value, chamber pressure, The technological parameters such as upper power, the flow of etching gas keep constant.It is preferred that, the etching gas that the 3rd main etch step is used The span of the technological parameter such as the species and flow of body, chamber pressure and upper power can be with above-mentioned second main etch step Span is identical, and description is not repeated herein.As shown in Figure 5 A and 5B, it is respectively the theory through the acquisition of the 3rd main etch step The illustraton of model of substrate pattern and the scanning electron microscope (SEM) photograph of actual substrate pattern.Knowable to comparison diagram 5A and 5B, the actual substrate shape obtained Looks are consistent with the model of theoretical substrate pattern.
4th main etch step can reduce the energetic ion of physical etchings effect by using relatively low substrate bias power Bombardment to channel bottom, so as to reduce the groove in channel bottom formation, and then can improve substrate channel bottom Planarization.In addition, the 4th main etch step can also improve the etching selection ratio of substrate by using relatively low lower power, from And height can be etched with Effective Regulation.It is preferred that, the span of lower power is in 100~200W.As shown in Figure 6 A and 6B, respectively For the illustraton of model and the scanning electron microscope (SEM) photograph of actual substrate pattern of the theoretical substrate pattern obtained through the 4th main etch step.Comparison diagram 6A and 6B understands that the actual substrate pattern obtained is consistent with the model of theoretical substrate pattern.
It should be noted that being found through experiments that, the process time of the second main etch step is longer, then the etching obtained is high Degree and base width will be smaller, therefore, and the second main etch step should coordinate with the 4th main etch step to be carried out, i.e.,:If second The process time of main etch step is longer, then can suitably extend the process time of the 4th main etch step, and reduces the 4th The lower power of main etch step, to guarantee etching height and the base width needed for obtaining.Further, it is also possible to according to through 2nd, the process time of etching height the 4th main etch step of setting obtained after the 3rd main etch step etching and lower power, To guarantee etching height and the base width needed for obtaining.It is preferred that, the value of the process time of the 4th main etch step Scope is in 8~12min.
In addition, the species and flow of the etching gas that the 4th main etch step is used, chamber pressure and upper power etc. The span of technological parameter can be identical with the span of second, third above-mentioned main etch step, and description is not repeated herein.
In over etching step, etching gas include BCl3, it is preferred that over etching step is used relative to main etch step Higher lower power, for playing a part of modifying substrate pattern, i.e. regulation trenched side-wall pattern and angle of inclination, to obtain Preferable substrate pattern.Preferably, the technological parameter of over etching step is:BCl3Flow span 50~ 70sccm;The scope of the chamber pressure of reaction chamber is in 1.5~4mT;The span of the upper power of excitation power supply output is 1800 ~2200W;The scope of the lower power of grid bias power supply output is in 600~800W;The span of etch period is in 7~10min.As schemed It is respectively the illustraton of model of theoretical substrate pattern and sweeping for actual substrate pattern obtained through the 4th main etch step shown in 7A and 7B Retouch electron microscope.Comparison diagram 7A and 7B understand that the actual substrate pattern obtained is consistent with the model of theoretical substrate pattern.
It is understood that the principle that embodiment of above is intended to be merely illustrative of the present and the exemplary implementation that uses Mode, but the invention is not limited in this.For those skilled in the art, the essence of the present invention is not being departed from In the case of refreshing and essence, various changes and modifications can be made therein, and these variations and modifications are also considered as protection scope of the present invention.

Claims (6)

1. a kind of substrate lithographic method, it is characterised in that comprise the following steps:
First main etch step, the etching selection ratio for improving mask, wherein, etching gas are used as using inert gas;
Second main etch step, mask pattern is modified by using relative superiority or inferiority power and the base width of substrate is adjusted, described The span of lower power is in 400~600W;
3rd main etch step, by within the predetermined process time of this step by pre-defined rule will under power by default highest Performance number is reduced to lowest power value, and to reduce flex point height, the pre-defined rule is:In the predetermined process time of this step It is interior, lower power is reduced to lowest power value by default peak power value by the relation of piecewise function or linear function;Institute The span of peak power value is stated in 350~450W, the span of the lowest power value is in 200~300W;It is described to turn Point refer to two relative side walls of the mask on increase with etch period, substrate surface can cross-direction shrinkage toward each other, lead The width of mask is caused to become narrow gradually so that substrate side wall occurs the flex point because of the cross-direction shrinkage of mask;
4th main etch step, the etching selection ratio of substrate, the lower power span are improved by using low power In 100~200W;
Over etching step, substrate pattern is modified by using relative superiority or inferiority power.
2. substrate lithographic method as claimed in claim 1, it is characterised in that walked in described second, third with the 4th main etching In rapid, the etching gas being passed through into reaction chamber include BCl3Or BCl3And CHF3Mixed gas or BCl3And H2's Mixed gas or BCl3、CHF3And H2Mixed gas.
3. substrate lithographic method as claimed in claim 1, it is characterised in that described lazy in first main etch step Property gas include argon gas, helium or nitrogen.
4. substrate lithographic method as claimed in claim 1, it is characterised in that in first main etch step, during technique Between span in 1~3min.
5. substrate lithographic method as claimed in claim 1, it is characterised in that in second main etch step, during technique Between span in 3~6min.
6. substrate lithographic method as claimed in claim 1, it is characterised in that stop when the flex point just occurs or will occurred Only the 3rd main etch step, starts simultaneously at progress the 4th main etch step.
CN201310738381.9A 2013-12-29 2013-12-29 Substrate lithographic method Active CN104752198B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310738381.9A CN104752198B (en) 2013-12-29 2013-12-29 Substrate lithographic method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310738381.9A CN104752198B (en) 2013-12-29 2013-12-29 Substrate lithographic method

Publications (2)

Publication Number Publication Date
CN104752198A CN104752198A (en) 2015-07-01
CN104752198B true CN104752198B (en) 2017-07-21

Family

ID=53591710

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310738381.9A Active CN104752198B (en) 2013-12-29 2013-12-29 Substrate lithographic method

Country Status (1)

Country Link
CN (1) CN104752198B (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106495087B (en) * 2015-09-08 2020-04-28 北京北方华创微电子装备有限公司 Etching method of silicon dioxide substrate
CN106571295B (en) * 2015-10-10 2020-03-31 北京北方华创微电子装备有限公司 Method for manufacturing patterned sapphire substrate
CN108321261B (en) * 2018-01-05 2020-10-30 东莞市中图半导体科技有限公司 Preparation method of graphical sapphire substrate
CN110867503B (en) * 2018-08-28 2021-06-08 北京北方华创微电子装备有限公司 Manufacturing method of patterned substrate, patterned substrate and light emitting diode
CN111863591A (en) * 2019-04-28 2020-10-30 北京北方华创微电子装备有限公司 Pre-cleaning method
CN115881533A (en) * 2021-08-12 2023-03-31 江苏鲁汶仪器股份有限公司 Etching method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1797716A (en) * 2004-12-22 2006-07-05 联华电子股份有限公司 Plasma etching method of reducing generation of fine dust
CN101111929A (en) * 2005-01-28 2008-01-23 株式会社爱发科 Capacitance element manufacturing method and etching method
US7446050B2 (en) * 2003-08-04 2008-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Etching and plasma treatment process to improve a gate profile
CN101355050A (en) * 2007-07-24 2009-01-28 台湾积体电路制造股份有限公司 Novel ladder poly etching back process for word line poly planarization
CN103311092A (en) * 2012-03-12 2013-09-18 中芯国际集成电路制造(上海)有限公司 Method for etching grooves

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7446050B2 (en) * 2003-08-04 2008-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Etching and plasma treatment process to improve a gate profile
CN1797716A (en) * 2004-12-22 2006-07-05 联华电子股份有限公司 Plasma etching method of reducing generation of fine dust
CN101111929A (en) * 2005-01-28 2008-01-23 株式会社爱发科 Capacitance element manufacturing method and etching method
CN101355050A (en) * 2007-07-24 2009-01-28 台湾积体电路制造股份有限公司 Novel ladder poly etching back process for word line poly planarization
CN103311092A (en) * 2012-03-12 2013-09-18 中芯国际集成电路制造(上海)有限公司 Method for etching grooves

Also Published As

Publication number Publication date
CN104752198A (en) 2015-07-01

Similar Documents

Publication Publication Date Title
CN104752198B (en) Substrate lithographic method
CN105514243B (en) A kind of method of patterned substrate
Zhou et al. Dry etching characteristics of GaN using Cl2/BCl3 inductively coupled plasmas
CN102931071B (en) Method and device for patterning sapphire substrate
EP3836195A1 (en) Method, substrate and apparatus
CN103915330A (en) Substrate etching method
EP2022106A2 (en) Methods for minimizing mask undercuts and notches for plasma processing system
CN106571295B (en) Method for manufacturing patterned sapphire substrate
CN104952788B (en) A kind of inclined hole lithographic method
CN104752190B (en) Substrate lithographic method
CN104253035A (en) Substrate etching method
CN105355538A (en) Etching method
TW201421567A (en) Substrate etching method
CN100397587C (en) Silicon gate etching process capable of avoiding microtrench phenomenon
CN105513942A (en) Etching method
CN104752159B (en) Substrate lithographic method
CN104253017B (en) Substrate lithographic method
CN105336602A (en) Method of making polycrystalline silicon etch sidewall angle
CN105720003B (en) Deep silicon hole lithographic method
CN111725063A (en) Etching method of semiconductor substrate
CN110867503B (en) Manufacturing method of patterned substrate, patterned substrate and light emitting diode
CN106711033A (en) Substrate etching method
TWI532095B (en) Wafer etching method
CN104064648A (en) Etching method for III-family compound substrate
CN103887375B (en) A kind of PSS patterned substrate lithographic method

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: 100176 Beijing economic and Technological Development Zone, Wenchang Road, No. 8, No.

Patentee after: Beijing North China microelectronics equipment Co Ltd

Address before: 100176 Beijing economic and Technological Development Zone, Wenchang Road, No. 8, No.

Patentee before: Beifang Microelectronic Base Equipment Proces Research Center Co., Ltd., Beijing