CN111725063A - Etching method of semiconductor substrate - Google Patents

Etching method of semiconductor substrate Download PDF

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Publication number
CN111725063A
CN111725063A CN202010567655.2A CN202010567655A CN111725063A CN 111725063 A CN111725063 A CN 111725063A CN 202010567655 A CN202010567655 A CN 202010567655A CN 111725063 A CN111725063 A CN 111725063A
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Prior art keywords
etching
semiconductor substrate
mask pattern
pattern
substrate
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CN202010567655.2A
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CN111725063B (en
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张君
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Beijing Naura Microelectronics Equipment Co Ltd
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Beijing Naura Microelectronics Equipment Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The embodiment of the invention provides an etching method of a semiconductor substrate, which comprises the following steps: etching the mask pattern covered on the semiconductor substrate by adjusting the designated process parameters so that the transverse shrinkage rate of the mask pattern is greater than that of the semiconductor substrate; and etching the semiconductor substrate covered with the etched mask pattern to obtain a substrate pattern with a desired morphology. According to the etching method of the semiconductor substrate provided by the embodiment of the invention, the platform can be prevented from appearing on the top of the cross-sectional morphology of the substrate pattern, and the substrate pattern with the expected morphology can be obtained, so that the process window of the semiconductor substrate can be enlarged, and the process requirements can be met.

Description

Etching method of semiconductor substrate
Technical Field
The invention relates to the technical field of microelectronics, in particular to an etching method of a semiconductor substrate.
Background
The PSS (Patterned sapphire Substrates) technology is a method for improving the light extraction efficiency of GaN (gallium nitride) -based LED devices, which is commonly used at present. At present, SiO appears on the market successively2PSS composite substrate with SiO conical pattern2+Al2O3Composite structures, i.e. with the upper part of the triangular cross-section of the conical pattern being SiO2Layer, height typically 1.87 μm, with the lower part of the triangular cross-section being Al2O3Layers, typically 200nm to 400nm in height.
The basic process for manufacturing the composite substrate comprises the following steps: first, on a sapphire planar substrate (i.e., Al)2O3Substrate) is coated with a layer of SiO2A layer; then, photoetching and plasma etching methods are adopted to etch SiO2The layer is etched to form a conical pattern (triangular in axial cross-section). During the etching process, due to SiO2The etch selectivity of the layer to the photoresist mask was about 1.1, while Al2O3The etch selectivity of the layer to the photoresist mask is about 0.9, i.e., SiO2The etch selectivity of the layer to the photoresist mask is relatively high, which results in the photoresist mask etching SiO2Transverse shrinkage speed ratio in etching Al2O3The slow lateral shrinkage rate of the layer often causes a plateau on top of the cross-sectional profile of the finally obtained substrate pattern, as shown in region a in fig. 1, resulting in SiO2The process window of the layer is small and cannot meet the process requirements.
Disclosure of Invention
The embodiment of the invention aims to solve at least one of the technical problems in the prior art, and provides an etching method of a semiconductor substrate, which can avoid the top of the cross-sectional morphology of a substrate graph from appearing a platform, thereby enlarging the process window of the semiconductor substrate and meeting the process requirements.
To achieve the object of the embodiments of the present invention, there is provided a method for etching a semiconductor substrate, including:
etching a mask pattern covered on a semiconductor substrate by adjusting specified process parameters so that the transverse shrinkage rate of the mask pattern is greater than that of the semiconductor substrate;
and etching the semiconductor substrate covered with the etched mask pattern to obtain a substrate pattern with a desired morphology.
Optionally, the specified process parameter includes a reaction pressure;
the etching of the mask pattern on the semiconductor substrate by adjusting the designated process parameters comprises:
and increasing the reaction pressure, and etching the mask pattern.
Optionally, the reaction pressure is in the range of 5mT to 50 mT.
Optionally, the designated process parameters further include an etching gas having an etching rate for the mask pattern greater than an etching rate for the semiconductor substrate.
Optionally, the etching the mask pattern on the semiconductor substrate by adjusting the designated process parameter includes:
and adding at least one of argon and nitrogen in the semiconductor chamber, and etching the mask pattern.
Optionally, the specified process parameter further includes bias power;
the etching of the mask pattern on the semiconductor substrate by adjusting the designated process parameters further comprises:
and increasing the bias power and etching the mask pattern.
Optionally, the bias power has a value range of 800W to 1200W.
Optionally, before the etching the mask pattern on the semiconductor substrate by adjusting the designated process parameter, the method further includes:
and setting the process time for etching the mask pattern according to the transverse section width of the mask pattern before etching.
Optionally, the semiconductor substrate includes an alumina substrate and a silicon dioxide layer disposed on the alumina substrate; the mask pattern is formed on the silicon dioxide layer and is made of photoresist; alternatively, the first and second electrodes may be,
the semiconductor substrate comprises a silicon dioxide substrate; the mask pattern is formed on the silicon dioxide substrate and is made of photoresist.
Optionally, the etching the semiconductor substrate covered with the etched mask pattern includes:
etching the semiconductor substrate to obtain a first pattern, wherein the etching height of the first pattern reaches a target etching height;
and etching the first pattern to obtain the substrate pattern with the expected morphology by modifying the cross-sectional morphology of the first pattern.
The embodiment of the invention has the following beneficial effects:
according to the semiconductor substrate etching method provided by the embodiment of the invention, a step of etching the mask pattern is added before etching the semiconductor substrate, and the step etches the mask pattern covered on the semiconductor substrate by adjusting the designated process parameters, so that the transverse shrinkage rate of the mask pattern is greater than that of the semiconductor substrate, the problem of slow transverse shrinkage rate of the mask during subsequent etching of the semiconductor substrate can be solved, and therefore, a platform is prevented from appearing at the top of the cross-sectional morphology of the substrate pattern due to the slow transverse shrinkage rate of the mask pattern, the substrate pattern with the expected morphology can be obtained, the process window of the semiconductor substrate can be enlarged, and the process requirements can be met.
Drawings
FIG. 1 is a scanning electron microscope image of a triangular cross-sectional profile of a composite substrate obtained by a conventional etching method;
FIG. 2 is a flow chart of a method for etching a semiconductor substrate according to an embodiment of the present invention;
fig. 3 is a process diagram of a method for etching a semiconductor substrate according to an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the following describes in detail an etching method of a semiconductor substrate according to an embodiment of the present invention with reference to the accompanying drawings.
Referring to fig. 2, the method for etching a semiconductor substrate according to the present embodiment includes:
s1, etching the mask pattern covered on the semiconductor substrate by adjusting the designated process parameters, so that the lateral shrinkage rate of the mask pattern is greater than that of the semiconductor substrate;
and S2, etching the semiconductor substrate covered with the etched mask pattern to obtain a substrate pattern with a desired appearance.
The above steps S1 and S2 both use the following etching process to etch the mask pattern and the semiconductor substrate, respectively, and are different from each other in the process parameters. Specifically, the etching process is as follows: introducing etching gas into the semiconductor cavity, and starting an excitation power supply (such as a radio frequency power supply) and a bias power supply, wherein the excitation power supply applies excitation power to the upper electrode to excite the etching gas in the semiconductor cavity to form plasma; the bias power supply applies bias power to the lower electrode to attract the plasma to etch the mask pattern or the semiconductor substrate. The process parameters of the etching process mainly include the type and flow rate of the etching gas, the excitation power, the bias power, the reaction pressure (i.e., the chamber pressure of the semiconductor chamber), the process duration, and the like.
Before the above step S1 is performed, an entire layer of a mask is first formed on a semiconductor substrate, and then the entire layer of the mask is etched using a photolithography process to form a mask pattern. As shown in FIG. 3 (1), a mask pattern 1 is obtained by a photolithography process, and the cross-sectional shape of the mask pattern 1 is approximately a square, and the side length D (width and height) of the square is, for example, 2.0 to 2.1 μm.
In the above step S1, the mask pattern is etched by adjusting the designated process parameters so that the lateral shrinkage rate of the mask pattern is greater than the lateral shrinkage rate of the semiconductor substrate. As shown in fig. 3 (2), in step S1, an etched mask pattern 1a is obtained, and the lateral width of the mask pattern 1a is narrowed in the X direction, that is, referred to as lateral shrinkage. The lateral width of the mask pattern 1a after etching is smaller than the side length D of the square cross section of the mask pattern 1 before etching. Therefore, the mask pattern is etched in advance in the X direction before the step S2 is performed, so that when the semiconductor substrate is etched in the step S2, the problem that the transverse shrinkage rate of the mask is slow can be solved, a platform is prevented from appearing on the top of the cross-sectional morphology of the substrate pattern due to the fact that the transverse shrinkage rate of the mask pattern is slow, the process window of the semiconductor substrate can be enlarged, and the process requirements are met.
In some embodiments, the specified process parameter comprises a reaction pressure. In this case, the above step S1 includes:
and increasing the reaction pressure and etching the mask pattern.
The higher the reaction pressure is, the faster the transverse shrinkage rate of the mask pattern is; otherwise, the slower. In this regard, in step S1, by setting a high reaction pressure to etch the mask pattern, it is possible to achieve a lateral contraction rate of the mask pattern that is greater than the lateral contraction rate of the semiconductor substrate.
Optionally, in step S1, the reaction pressure ranges from 5mT to 50 mT. By setting the reaction pressure within the range, on one hand, the transverse shrinkage rate of the mask pattern can be effectively improved; on the other hand, the phenomenon that the etching height of the mask pattern is excessively sacrificed due to the overhigh longitudinal etching rate of the mask pattern caused by overhigh reaction pressure can be avoided.
On the basis of adjusting the reaction pressure, the lateral shrinkage rate of the mask pattern can be further improved by combining the adjustment of other specified process parameters. For example, the specified process parameters further include an etching gas having an etching rate for the mask pattern greater than an etching rate for the semiconductor substrate, and for example, the step S1 includes:
at least one of argon and nitrogen is added to the semiconductor chamber and the mask pattern is etched. The etching gas can be ionized to form heavy ions so as to achieve the purpose of enhancing the physical bombardment effect, and on the basis, the transverse etching rate can be effectively improved by combining the action of high reaction pressure. Of course, in practical applications, other etching gases having an etching rate for the mask pattern greater than that for the semiconductor substrate may be used.
As another example, the specified process parameters may also include bias power. In this case, the above step S1 includes:
and increasing the bias power and etching the mask pattern.
The higher the bias power is, the faster the lateral shrinkage rate of the mask pattern is; otherwise, the slower. Accordingly, in step S1, the mask pattern is etched by setting a high bias power while setting a high reaction pressure, so that the lateral shrinkage rate of the mask pattern can be further increased.
Optionally, in step S1, the bias power has a value range of 800W to 1200W. By setting the bias power within this range, the lateral contraction rate of the mask pattern can be effectively increased.
Before performing step S1, the method further includes: the process duration for etching the mask pattern (i.e., the above-described step S1) may be set according to the width of the lateral cross section of the mask pattern before etching (e.g., the side length D of the square cross section of the above-described mask pattern 1). Specifically, the larger the width of the transverse cross section of the mask pattern is, the longer the process duration of the step S1 is increased; conversely, the smaller the lateral cross-sectional width of the mask pattern is, the shorter the process duration of the step S1 is. For example, if the width of the lateral cross section of the mask pattern is in the range of 2 μm to 2.1 μm, the process time for etching the mask pattern is in the range of 2min to 5 min.
In this embodiment, the mask pattern may be etched according to a set process duration.
The etching method of the semiconductor substrate provided by the embodiment of the invention can be applied to various different semiconductor substrates, for example, the semiconductor substrate is a composite substrate, and the semiconductor substrate comprises an alumina substrate (Al)2O3Substrate) and a silicon dioxide layer (SiO) provided on the alumina substrate2A layer); the mask pattern 1a is formed on the silicon dioxide layer and is made of photoresist. As another example, the semiconductor substrate includes a silicon oxide substrate on which a mask pattern is formed and is made using photoresist.
It should be noted that, for the composite substrate or the silicon dioxide substrate, in the step S1, at least one of argon and nitrogen may be used as an etching gas, and taking argon as an example, argon ions formed by argon can etch the mask pattern made of the photoresist faster, and etch the silicon dioxide layer slower, so as to achieve the purpose of increasing the lateral shrinkage rate of the mask pattern.
Optionally, the step S2 further includes:
s21, etching the semiconductor substrate to obtain a first pattern, wherein the etching height of the first pattern reaches a target etching height;
and S22, etching the first pattern to obtain a substrate pattern with a desired profile by modifying the cross-sectional profile of the first pattern.
The specific processes of step S21 and step S22 are similar to the etching process of step S1, and only the process parameters are different.
As shown in fig. 3 (3), the first pattern 2 of the semiconductor substrate and the mask pattern 1b, both of which have an isosceles trapezoid cross-sectional shape, are obtained through the above step S21. The step S21 is to increase the etching height in the Y direction to make the etching height of the first pattern 2 reach the target etching height, so as to meet the process requirement.
As shown in fig. 3 (4), the final pattern of the semiconductor substrate having a triangular cross-sectional profile is obtained through the above-described step S22, and for the composite substrate, the upper portion of the triangle is the silicon dioxide layer 2a and the lower portion is the alumina substrate 3.
In practical applications, the process parameters adopted in step S22 are different from the process parameters adopted in step S21, and the differences at least include: different etch gas flow rates and/or bias powers are used. Specifically, the flow rate of the etching gas used in step S22 is smaller than the flow rate of the etching gas used in step S21; the bias power used in step S22 is higher than the bias power used in step S21, so that step S22 can be used to modify the profile of the semiconductor substrate, for example, to adjust the sidewall profile and the tilt angle of the substrate pattern.
Optionally, the etching gas used in step S21 and step S22 both include boron chloride. In addition, the bias power adopted in the step S21 has the value range of 500W-800W, the reaction pressure of 2.6mT and the etching gas flow of 120 sccm; the bias power used in step S22 is 800W, the reaction pressure is 2.6mT, and the flow rate of the etching gas is 60 sccm.
It should be noted that the step S2 is not limited to the solution provided in this embodiment, and in practical application, can be freely set according to specific needs.
In summary, in the semiconductor substrate etching method provided in the embodiments of the present invention, a step of etching a mask pattern is added before etching a semiconductor substrate, and in the step, a specified process parameter is adjusted to etch the mask pattern covering the semiconductor substrate, so that a lateral shrinkage rate of the mask pattern is greater than a lateral shrinkage rate of the semiconductor substrate, and a problem that the lateral shrinkage rate of the mask is slow in a subsequent semiconductor substrate etching process can be solved, thereby avoiding a platform appearing on a top of a cross-sectional profile of the substrate pattern due to the slow lateral shrinkage rate of the mask pattern, that is, obtaining the substrate pattern with a desired profile, further increasing a process window of the semiconductor substrate, and satisfying process requirements.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.

Claims (10)

1. A method for etching a semiconductor substrate, comprising:
etching a mask pattern covered on a semiconductor substrate by adjusting specified process parameters so that the transverse shrinkage rate of the mask pattern is greater than that of the semiconductor substrate;
and etching the semiconductor substrate covered with the etched mask pattern to obtain a substrate pattern with a desired morphology.
2. The method of etching a semiconductor substrate according to claim 1, wherein the specified process parameter includes a reaction pressure;
the etching of the mask pattern on the semiconductor substrate by adjusting the designated process parameters comprises:
and increasing the reaction pressure, and etching the mask pattern.
3. The method for etching a semiconductor substrate according to claim 2, wherein the reaction pressure is in a range of 5mT to 50 mT.
4. The method of etching a semiconductor substrate according to claim 2, wherein the specified process parameters further include an etching gas having an etching rate for the mask pattern that is greater than an etching rate for the semiconductor substrate.
5. The method for etching a semiconductor substrate according to claim 4, wherein the etching of the mask pattern on the semiconductor substrate by adjusting the designated process parameters comprises:
and adding at least one of argon and nitrogen in the semiconductor chamber, and etching the mask pattern.
6. The method of etching a semiconductor substrate according to claim 2, wherein the specified process parameters further include bias power;
the etching of the mask pattern on the semiconductor substrate by adjusting the designated process parameters further comprises:
and increasing the bias power and etching the mask pattern.
7. The method for etching a semiconductor substrate according to claim 6, wherein the bias power has a value in a range of 800W to 1200W.
8. The method for etching a semiconductor substrate according to claim 1, wherein before the etching the mask pattern on the semiconductor substrate by adjusting the designated process parameter, further comprising:
and setting the process time for etching the mask pattern according to the transverse section width of the mask pattern before etching.
9. The method for etching a semiconductor substrate according to claim 1 or 5, wherein the semiconductor substrate comprises an alumina substrate and a silicon dioxide layer provided on the alumina substrate; the mask pattern is formed on the silicon dioxide layer and is made of photoresist; alternatively, the first and second electrodes may be,
the semiconductor substrate comprises a silicon dioxide substrate; the mask pattern is formed on the silicon dioxide substrate and is made of photoresist.
10. The method for etching a semiconductor substrate according to any one of claims 1 to 8, wherein the etching of the semiconductor substrate covered with the etched mask pattern comprises:
etching the semiconductor substrate to obtain a first pattern, wherein the etching height of the first pattern reaches a target etching height;
and etching the first pattern to obtain the substrate pattern with the expected morphology by modifying the cross-sectional morphology of the first pattern.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023015762A1 (en) * 2021-08-12 2023-02-16 江苏鲁汶仪器有限公司 Etching method

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CN102201512A (en) * 2011-04-22 2011-09-28 东莞市中镓半导体科技有限公司 Patterned structure substrate
CN104752190A (en) * 2013-12-26 2015-07-01 北京北方微电子基地设备工艺研究中心有限责任公司 Substrate etching method
JP2016012664A (en) * 2014-06-30 2016-01-21 豊田合成株式会社 Sapphire substrate manufacturing method and group iii nitride semiconductor light emitting element manufacturing method
CN105336659A (en) * 2014-07-14 2016-02-17 北京北方微电子基地设备工艺研究中心有限责任公司 Isolation groove etching method of GaN-based LED chip
CN105513942A (en) * 2014-09-22 2016-04-20 北京北方微电子基地设备工艺研究中心有限责任公司 Etching method
CN110649134A (en) * 2018-06-26 2020-01-03 北京北方华创微电子装备有限公司 Manufacturing method of patterned substrate, patterned substrate and light emitting diode
CN110867503A (en) * 2018-08-28 2020-03-06 北京北方华创微电子装备有限公司 Manufacturing method of patterned substrate, patterned substrate and light emitting diode

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Publication number Priority date Publication date Assignee Title
US4293375A (en) * 1976-02-07 1981-10-06 U.S. Philips Corporation Method of manufacturing a device and device manufactured according to the method
CN102201512A (en) * 2011-04-22 2011-09-28 东莞市中镓半导体科技有限公司 Patterned structure substrate
CN104752190A (en) * 2013-12-26 2015-07-01 北京北方微电子基地设备工艺研究中心有限责任公司 Substrate etching method
JP2016012664A (en) * 2014-06-30 2016-01-21 豊田合成株式会社 Sapphire substrate manufacturing method and group iii nitride semiconductor light emitting element manufacturing method
CN105336659A (en) * 2014-07-14 2016-02-17 北京北方微电子基地设备工艺研究中心有限责任公司 Isolation groove etching method of GaN-based LED chip
CN105513942A (en) * 2014-09-22 2016-04-20 北京北方微电子基地设备工艺研究中心有限责任公司 Etching method
CN110649134A (en) * 2018-06-26 2020-01-03 北京北方华创微电子装备有限公司 Manufacturing method of patterned substrate, patterned substrate and light emitting diode
CN110867503A (en) * 2018-08-28 2020-03-06 北京北方华创微电子装备有限公司 Manufacturing method of patterned substrate, patterned substrate and light emitting diode

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023015762A1 (en) * 2021-08-12 2023-02-16 江苏鲁汶仪器有限公司 Etching method

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