JP2016012664A - Sapphire substrate manufacturing method and group iii nitride semiconductor light emitting element manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sapphire substrate manufacturing method and a group III nitride semiconductor light emitting element manufacturing method, which can form a resist of a favorable shape to form a fine convexoconcave shape with high accuracy.SOLUTION: A sapphire substrate manufacturing method comprises a first resist pattern formation process, a second resist pattern formation process and a sapphire wafer etching process. The second resist pattern formation process includes: a first resist etching process (S210) of etching a resist R1 in a first period T1 by supplying a Clgas to a resist R1; a plasma irradiation process (S220) of irradiating a plasmatized Ar gas on the resist R1 in a second period T2; and a second resist etching process (S230) of etching the resist R1 in a third period T3 by supplying a Clgas to the resist R1 to form a resist R2.

Description

  The technical field of the present specification relates to a method for manufacturing a sapphire substrate and a method for manufacturing a group III nitride semiconductor light emitting device, in which fine concavo-convex processing is performed on a sapphire wafer.

  A sapphire substrate used for a group III nitride semiconductor light emitting device or the like may be subjected to fine unevenness on its surface. This is for efficiently extracting light emitted from the light emitting layer of the group III nitride semiconductor to the outside.

  An etching technique may be used to apply a fine unevenness to the sapphire substrate. Etching includes dry etching and wet etching. For example, Patent Document 1 describes a technique for forming irregularities on a substrate by using a chlorine-based gas, a fluorine-based gas, an argon gas, or the like after forming a mask on the substrate (see Patent Document 1). Paragraph [0021] etc.).

JP 2008-177528 A

  When etching is performed using such a highly reactive gas, the resist may be asymmetrically cut. The present inventors came to consider the reason as follows. The etching gas collides with the resist surface and charges the resist surface. However, a part of the resist is strongly charged and the rest of the resist is not so strongly charged. This charge distribution is asymmetric with respect to the surface of the sapphire wafer. By this asymmetric charging, an asymmetric electric field is formed near the surface of the sapphire wafer. Under the influence of this electric field, the resist has a portion where the amount of etching gas which is struck per unit area is large and a portion where the amount is small. As a result, the shape of the resist is asymmetric. Such a tendency is particularly remarkable in the vicinity of the outer edge portion of the wafer.

  The shape of the resist also affects the shape of the sapphire wafer that is the subject of the original etching. That is, when the resist shape is asymmetrically distorted, the uneven shape of the sapphire wafer is also asymmetrically distorted. In the case where a semiconductor layer is formed on a sapphire substrate whose concavo-convex shape is distorted as described above, the crystallinity of the semiconductor layer is not so good. Therefore, it is preferable to form a resist having a suitable shape before etching the sapphire wafer.

  The technique of this specification has been made to solve the problems of the conventional techniques described above. That is, the object is to provide a method for manufacturing a sapphire substrate and a method for manufacturing a group III nitride semiconductor light-emitting device capable of forming a finely-shaped uneven shape with high accuracy by forming a resist having a suitable shape.

  A method for manufacturing a sapphire substrate in a first aspect includes a first resist pattern forming step of forming a first resist pattern on a first surface of a sapphire wafer by photolithography, and etching the first resist pattern. A second resist pattern forming step for forming the second resist pattern, and a sapphire wafer etching step for etching the first surface of the sapphire wafer on which the second resist pattern is formed. The second resist pattern forming step includes supplying a chlorine-based gas to the first resist pattern and etching the first resist pattern in the first period, and following the first period. In the second period, a plasma irradiation step of irradiating the first resist pattern with a plasma-like rare gas, and supplying a chlorine-based gas to the first resist pattern in the third period following the second period And a second resist etching step for forming a second resist pattern by etching the first resist pattern.

  In this sapphire substrate manufacturing method, a frustum-shaped first resist pattern is formed by photolithography, and the resist pattern is etched to obtain a second conical-shaped resist pattern. The side surface of the resist after exposure and development is generally substantially perpendicular to the first surface of the sapphire wafer. Therefore, the inclination of the side surface of the resist is changed by the resist etching process. In this resist etching process, the resist is cut to the order of 1 μm. Therefore, non-uniform charge distribution tends to occur in the resist while the resist is being shaved. In this sapphire substrate manufacturing method, the resist is removed by a plasma irradiation process. Thereby, a resist pattern having a shape suitable for etching a sapphire wafer can be formed. Since the resist pattern is formed with high accuracy, a fine uneven shape can be formed with high accuracy on the sapphire substrate.

  In the method for manufacturing a sapphire substrate in the second aspect, the first resist etching step and the second resist etching step are steps for adjusting the shape of the first resist pattern to the shape of the second resist pattern. And a plasma irradiation process is implemented in the middle of preparing the shape of the 1st resist pattern.

  In the method for manufacturing a sapphire substrate in the third aspect, the first resist pattern has a first intersecting surface that intersects the first surface of the sapphire wafer. The second resist pattern has a second intersecting surface that intersects the first surface of the sapphire wafer. The angle formed by the first intersecting surface and the first surface is in the range of 75 ° to 90 °. The angle formed by the second intersecting surface and the first surface is in the range of 45 ° to 65 °.

  In the sapphire substrate manufacturing method according to the fourth aspect, the first resist pattern has a first intersecting surface that intersects the first surface of the sapphire wafer. The second resist pattern has a second intersecting surface that intersects the first surface of the sapphire wafer. The angle formed by the second intersecting surface and the first surface is 10 ° or more smaller than the angle formed by the first intersecting surface and the first surface.

  In the sapphire substrate manufacturing method according to the fifth aspect, the shape of the first resist pattern is a truncated cone shape or a polygonal truncated cone shape. The shape of the second resist pattern is a conical shape or a polygonal pyramid shape.

  In the sapphire substrate manufacturing method according to the sixth aspect, the supply of the rare gas is started at the start of the plasma irradiation process, and the supply of the rare gas is stopped at the end of the plasma irradiation process.

  According to a seventh aspect of the present invention, there is provided a group III nitride semiconductor light emitting device comprising: a sapphire substrate manufacturing process for manufacturing a sapphire substrate by the above-described sapphire substrate manufacturing method; A semiconductor layer forming step of forming, and an electrode forming step of forming an electrode on the group III nitride semiconductor layer.

  In the present specification, there are provided a method for manufacturing a sapphire substrate and a method for manufacturing a group III nitride semiconductor light-emitting device capable of forming a resist with a suitable shape to form a fine concavo-convex shape with high accuracy.

It is a front view which shows the sapphire substrate in 1st Embodiment. It is a top view which shows a part of sapphire substrate in 1st Embodiment. It is a fragmentary sectional view which shows the III-III cross section of FIG. It is a figure which shows schematic structure of the etching apparatus in 1st Embodiment. It is a process table | surface which shows the manufacturing process of the sapphire substrate in 1st Embodiment. It is a timing chart explaining the resist etching process in 1st Embodiment. It is a figure (the 1) for demonstrating the manufacturing method of the sapphire substrate in 1st Embodiment. It is FIG. (2) for demonstrating the manufacturing method of the sapphire substrate in 1st Embodiment. It is FIG. (3) for demonstrating the manufacturing method of the sapphire substrate in 1st Embodiment. It is FIG. (4) for demonstrating the manufacturing method of the sapphire substrate in 1st Embodiment. It is FIG. (5) for demonstrating the manufacturing method of the sapphire substrate in 1st Embodiment. It is a figure for demonstrating the resist etching process in 1st Embodiment. It is a graph which shows the irradiation time dependence of the surface height at the time of implementing an argon plasma irradiation process. It is a graph which shows the irradiation frequency dependence of the surface height at the time of implementing an argon plasma irradiation process. It is a figure which shows schematic structure of the group III nitride semiconductor light-emitting device in 2nd Embodiment.

  Hereinafter, specific embodiments will be described with reference to the drawings, taking a sapphire substrate and a semiconductor light emitting element as examples. However, the technique of this specification is not limited to the following embodiment. Moreover, the thickness and uneven shape of the sapphire substrate, which will be described later, are drawn relatively large compared to the actual size.

(First embodiment)
1. Sapphire Substrate FIG. 1 is a front view showing a sapphire substrate 100 manufactured by the method for manufacturing a sapphire substrate of this embodiment. The sapphire substrate 100 has a first surface 100a, a second surface 100b, and a convex portion 110. The first surface 100 a has a large number of convex portions 110. The first surface 100a is a semiconductor layer forming surface for forming a semiconductor layer. The first surface 100a is a c-plane of sapphire. The second surface 100b is a surface opposite to the first surface 100a. No convex portion is formed on the second surface 100b.

  FIG. 2 is a partial plan view of the sapphire substrate 100 as seen from the first surface 100a side. As shown in FIG. 2, the convex part 110 has a conical shape. The convex portion 110 has a top portion 111, a conical surface 112, and a bottom portion 113. The bottom 113 is a portion that forms a boundary between the first surface 100 a of the sapphire substrate 100 and the conical surface 112. The bottom 113 has an annular shape. Moreover, the convex part 110 is arrange | positioned in the honeycomb form on the 1st surface 100a. That is, when the top portions 111 of the plurality of convex portions 110 are virtually connected by a line, the top portions 111 are arranged at the positions of the apex and center of the regular hexagon.

  FIG. 3 is a cross-sectional view partially showing a III-III cross section of FIG. As shown in FIG. 3, the pitch interval X1 of the convex portions 110 is in the range of 2 μm to 10 μm. The pitch interval X1 is a distance between the top portions 111 of the adjacent convex portions 110. The maximum diameter X2 of the convex portion 110 is in the range of 1 μm to 5 μm. The maximum diameter X2 of the convex portion 110 is the diameter of the bottom portion 113. The height H1 of the convex portion 110 is in the range of 1 μm to 5 μm. The height H <b> 1 of the convex portion 110 is a distance between the first surface 100 a and the top portion 111. These numerical ranges are only a guide and numerical values other than those described above may be used.

2. Etching Apparatus FIG. 4 is a diagram showing a schematic configuration of an etching apparatus 1000 used for etching according to the present embodiment. As shown in FIG. 4, the etching apparatus 1000 includes a chamber 1100, an antenna 1200, a first high-frequency power source 1300, a first matching unit 1310, a lower electrode 1400, a tray 1410, and a second high-frequency power source. 1500, a second matching unit 1510, a gas inlet 1610, a gas outlet 1620, a first gas supply unit 1710, a second gas supply unit 1720, a third gas supply unit 1730, And a fourth gas supply unit 1740.

  The chamber 1100 is a reaction chamber for performing etching. The antenna 1200 is an electrode for generating plasma in the plasma generation unit PG1 inside the chamber 1100. The first high frequency power source 1300 is for applying a high frequency voltage to the antenna 1200. This frequency is, for example, 13.56 MHz. The first matching unit 1310 is disposed between the first high-frequency power source 1300 and the antenna 1200.

  A tray 1410 is disposed on the lower electrode 1400. The tray 1410 is a mounting table for mounting the wafer W1 to be etched. The lower electrode 1400 is for drawing the plasma generated in the plasma generation unit PG1 into the wafer W1. The second high frequency power supply 1500 is for applying a high frequency voltage to the lower electrode 1400. The second matching unit 1510 is disposed between the second high frequency power supply 1500 and the lower electrode 1400.

The gas inlet 1610 is for allowing an etching gas to flow into the chamber 1100. A number of gas inlets 1610 are provided in order to send the etching gas uniformly into the chamber 1100. The gas exhaust port 1620 is for exhausting the gas inside the chamber 1100 to the outside of the chamber 1100. The first gas supply unit 1710 is for supplying Cl ₂ gas. The second gas supply unit 1720 is for supplying Ar gas. The third gas supply unit 1730 is for supplying HBr gas. The fourth gas supply unit 1740 is for supplying BCl ₃ gas.

3. Outline of Method for Manufacturing Sapphire Substrate Here, an overview of a method for manufacturing a sapphire substrate will be described. FIG. 5 is a process chart showing an overall image of a method for manufacturing a sapphire substrate. As shown in FIG. 5, the manufacturing process of the sapphire substrate of this embodiment includes a first resist pattern forming process (S100), a second resist pattern forming process (S200), and a sapphire wafer etching process (S300). Have.

  Thus, the manufacturing method of the sapphire substrate of this embodiment is divided into the process of forming a resist and the process of etching a sapphire wafer. Etching is also performed in the step of forming a resist. Therefore, the manufacturing method of the sapphire substrate of this embodiment has both the process of etching a resist, and the process of etching a sapphire wafer.

  The first resist pattern forming step is a step of forming a first resist pattern on the first surface of the sapphire wafer by photolithography. The second resist pattern forming step is a step of forming the second resist pattern by etching the first resist pattern. The sapphire wafer etching step is a step of etching the first surface of the sapphire wafer on which the second resist pattern is formed. As described above, in the present embodiment, a resist is formed in a shape suitable for the sapphire wafer by the first resist pattern forming step and the second resist pattern forming step. And a fine uneven | corrugated shape is formed in a sapphire wafer by a sapphire wafer etching process.

4). As shown in FIG. 5, the second resist pattern forming step (S200) includes a first resist etching step (S210), an argon plasma irradiation step (S220), and a second resist etching step (S200). S230). This second resist pattern forming step is a step of adjusting the shape of the resist formed in the first resist pattern forming step (S100). As will be described later, the resist that has been in the shape of a frustum is shaped into a cone shape.

4-1. Timing Chart FIG. 6 is a timing chart for explaining the resist etching method of this embodiment. As shown in FIG. 6, the first resist etching step (S210) is performed in the first period T1. The argon plasma irradiation step (S220) is performed in the second period T2. The second resist etching step (S230) is performed in the third period T3. Note that the second period T2 is a period subsequent to the first period T1. The third period T3 is a period subsequent to the second period T2.

5. Manufacturing method of sapphire substrate 5-1. Substrate Preparation Step First, as shown in FIG. 7, a wafer W1 is prepared. The wafer W1 is a sapphire wafer that has not yet been formed with uneven shapes. As shown in FIG. 7, the wafer W1 has a first surface W1a and a second surface W1b. Wafer W1 is c-plane sapphire. The first surface W1a is a c-plane. The second surface W1b is a surface on the opposite side of the first surface W1a.

5-2. First resist pattern forming step (S100)
Next, as shown in FIG. 8, a resist R0 having a uniform thickness is applied to the first surface W1a of the wafer W1. The resist R0 is a known photoresist. Therefore, the surface R0a of the resist R0 is exposed on the opposite side of the second surface W1b of the wafer W1. In this state, the wafer W1 is pre-baked.

  Next, the resist R0 is exposed. Then, the resist R0 is developed. Thereby, as shown in FIG. 9, a pattern of the resist R1 is formed on the first surface W1a of the wafer W1. The resist R1 is a first resist pattern formed by exposure and development. The resist R1 is disposed at a position corresponding to the top 111 of FIG. That is, the resist R1 is located at the apex and center of the regular hexagon.

  The shape of the resist R1 is a frustum shape. For example, it has a truncated cone shape or a polygonal truncated cone shape. The resist R1 has an inclined surface R1a and a surface R1b. The surface R1b of the resist R1 is a flat surface that is substantially parallel to the first surface W1a of the wafer W1. In the case of using a photolithography technique for removing the exposed portion, the flat surface R1b necessarily remains.

As shown in FIG. 9, the inclined surface R1a of the resist R1 is an intersecting surface that intersects the first surface W1a of the wafer W1. When the resist R1 has a polygonal frustum shape, the inclined surface R1a is one of the inclined surfaces of the polygonal frustum shape. When the resist R1 has a truncated cone shape, the inclined surface R1a is an inclined surface having a truncated cone shape. An angle θ1 formed by the inclined surface R1a of the resist R1 and the first surface W1a of the wafer W1 is in the range of 75 ° to 85 °. That is, the following equation holds.
75 ° ≦ θ1 ≦ 85 °

5-3. Second resist pattern forming step (S200)
Next, by etching the resist R1, the shape of the resist R1 is adjusted to the shape of the resist R2 having a conical shape or a polygonal pyramid shape. Then, the flat surface R1b of the resist R1 is lost. For this purpose, the etching apparatus 1000 shown in FIG. 4 is used.

5-3-1. First resist etching step (S210)
Here, as shown in FIG. 6, the first resist etching step (S210) is performed in the first period T1. In this step, the first gas supply unit 1710 supplies Cl ₂ gas. Further, the second gas supply unit 1720 does not supply Ar gas. The power of the antenna 1200 is set to 600W. The bias power of the lower electrode 1400 is set to 1800W. In this way, the plasma-based chlorine-based gas is supplied to the sapphire wafer W1 and the resist R1, and the resist R1 is etched. The internal pressure of the etching apparatus 1000 in this step is in the range of 0.1 Pa to 2.0 Pa. This numerical range is an example, and other numerical values may be used.

5-3-2. Argon plasma irradiation process (S220)
Next, an argon plasma irradiation step (S220) is performed in the second period T2. In this step, the first gas supply unit 1710 does not supply the Cl ₂ gas. The second gas supply unit 1720 supplies Ar gas. The power of the antenna 1200 is set to 300W. The bias power of the lower electrode 1400 is set to 0W. That is, the supply of bias power is stopped. Therefore, the argon ions reach the resist R1 without being accelerated by the lower electrode 1400. In this way, the resist R1 is irradiated with positively charged argon ions. In this way, the sapphire wafer W1 and the resist R1 are irradiated with the rare gas that has been converted into plasma. Then, the resist R1 is etched. The internal pressure of the etching apparatus 1000 in this step is in the range of 0.5 Pa to 10.0 Pa. This numerical range is an example, and other numerical values may be used.

At the start of the argon plasma irradiation process, the second gas supply unit 1720 starts supplying argon gas. At the end of the argon plasma irradiation process, the second gas supply unit 1720 stops supplying argon gas. That is, argon gas is not supplied in the first resist etching step and the second resist etching step. By stopping the supply of the argon gas in this way, it is possible to relatively increase the supply amount of the Cl ₂ gas supplied into the chamber 1100 that keeps the internal pressure constant. That is, the etching rate in the first resist etching step and the second resist etching step can be increased.

5-3-3. Second resist etching step (S230)
Next, a second resist etching step (S230) is performed in the third period T3. In this step, the same conditions as in the first resist etching step are applied. That is, the first gas supply unit 1710 supplies Cl ₂ gas. Further, the second gas supply unit 1720 does not supply Ar gas. The power of the antenna 1200 is set to 600W. The bias power of the lower electrode 1400 is set to 1800W. In this way, the plasma-generated chlorine-based gas is supplied to the sapphire wafer W1 and the resist R1, and the resist R1 is etched to form the resist R2. The internal pressure of the etching apparatus 1000 in this step is in the range of 0.1 Pa to 2.0 Pa. This numerical range is an example, and other numerical values may be used.

  Thereby, as shown in FIG. 10, a resist R2 is formed. The resist R2 is a second resist pattern formed by etching the resist R1. The shape of the resist R2 is a cone shape. For example, it has a conical shape or a polygonal pyramid shape. Further, the first surface W1a of the wafer W1 remains in the place where the resist R1 is present, and is slightly shaved in the place where the resist R1 is not exposed. However, since the amount to be cut here is very small, the surface exposed after being cut is also referred to as the first surface W1c.

  The resist R2 has an inclined surface R2a. As described above, the flat surface R1b disappears in the resist R2. As shown in FIG. 10, the inclined surface R2a of the resist R2 is an intersecting surface that intersects the first surface W1a of the wafer W1. In addition, the inclined surface R2a also intersects the first surface W1c. When the resist R2 has a polygonal pyramid shape, the inclined surface R2a is one of the inclined surfaces having a polygonal pyramid shape. When the resist R2 has a conical shape, the inclined surface R2a is a conical inclined surface.

An angle θ2 formed by the inclined surface R2a of the resist R2 and the first surface W1a of the wafer W1 is not less than 45 ° and not more than 65 °. That is, the following equation holds.
45 ° ≦ θ2 ≦ 65 °
The angle θ2 is more preferably in the range of 50 ° to 60 °.

Further, the angle θ2 of the resist R2 is smaller than the angle θ1 in the resist R1. That is, the following equation holds.
θ2 <θ1

Further, the angle θ2 is smaller than the angle θ1 by 10 ° or more. That is, the following equation holds.
θ1 − θ2 ≧ 10 °
Further, the angle θ2 may be smaller than the angle θ1 by 20 ° or more.

  Thus, the first resist etching step (S210) and the second resist etching step (S230) are steps for adjusting the shape of the resist R1 formed by a known photolithography technique to the shape of the resist R2. In the second resist pattern forming step (S200), the etching of the resist R1 is interrupted while the shape of the resist R1 is being adjusted, and the argon plasma irradiation step (S220) is performed. As a result, the resist R1 is neutralized as will be described later.

  The shape of the resist R1 is changed to the resist R2 by etching. For the sake of convenience, it will be referred to as a resist R1 during the preparation of this shape, that is, during the etching.

5-4. Sapphire wafer etching process (S300)
Subsequently, the wafer W1 on which the second resist pattern is formed is etched. At that time, the second gas supply unit 1720 supplies Ar gas. The third gas supply unit 1730 supplies HBr gas. The fourth gas supply unit 1740 supplies BCl ₃ gas. The power of the antenna is 600W. The power of the bias is 1800W. The internal pressure of the etching apparatus 1000 in this step is in the range of 0.1 Pa to 2.0 Pa. This numerical range is an example, and other numerical values may be used.

  Thereby, as shown in FIG. 11, the wafer W1 is etched. Of course, the resist R2 is etched to become the resist R3. At this stage, the wafer W1 has a first surface 100a and an inclined surface W1d. Also, as shown in FIG. 11, the first surface W1a and the resist R3 remain slightly on the wafer W1. However, in practice, the first surface W1a and the resist R3 are very small. Therefore, after removing the resist R3, the sapphire substrate 100 shown in FIG. 1 is manufactured.

5-5. Resist Removal Step Then, the resist R3 is removed from the wafer W1 in FIG. 11 and the wafer W1 is cleaned. Thereby, the sapphire substrate 100 shown in FIG. 1 is manufactured.

6). Effects of the etching method of the present embodiment Here, the effects of the etching method of the present embodiment will be described. FIG. 12 is a conceptual diagram showing the time lapse of the resist in the resist etching process. The horizontal direction in FIG. 12 shows the passage of time. That is, the time advances from the left side to the right side of FIG. The upper part of FIG. 12 shows a case where an argon plasma irradiation process is performed. The lower part of FIG. 12 shows a case where the argon plasma irradiation process is not performed.

6-1. First example (with argon plasma irradiation process)
The upper part of FIG. 12 shows a case where the first resist etching step (S210), the argon plasma irradiation step (S220), and the second resist etching step (S230) are performed. In the first resist etching step, the resist R1 has an asymmetric charge distribution due to Cl 2 ⁻ ions. Next, the resist R1 is irradiated with Ar ⁺ ions by an argon plasma irradiation step (S220). Thereby, the surface of the resist R1 is neutralized. Then, the non-uniform charge distribution due to the asymmetric charging of the resist R1 is eliminated. In the second resist etching step, the resist R2 is formed in a substantially symmetrical shape.

6-2. Second example (without argon plasma irradiation process)
The lower part of FIG. 12 shows a case where the resist etching process is performed for a time T0 without performing the argon plasma irradiation process. As shown in the lower part of FIG. 12, in this case, the resist R1 is not neutralized during the etching. For this reason, the asymmetric charge distribution in the resist is not canceled halfway. As a result, Cl ^- ions are distributed asymmetrically under the influence of the electric field formed by the asymmetric charge distribution.

7). Experiment 7-1. Discharge Time FIG. 13 is a graph showing the surface roughness of the height of the resist R1 with respect to the time when the argon plasma irradiation process is performed. The horizontal axis in FIG. 13 represents the argon plasma irradiation time. The vertical axis in FIG. 13 represents the surface roughness of the resist R1. As shown in FIG. 13, when there is no argon plasma irradiation, the surface roughness σ of the resist R1 is about 0.017 μm. As the argon plasma is irradiated, the surface roughness σ of the resist R1 decreases. When the irradiation time is 80 seconds or longer, the surface roughness σ of the resist R1 is about 0.009 μm. Therefore, the second time T2 for performing the argon plasma irradiation process is preferably 80 seconds or more.

7-2. Number of Discharges FIG. 14 is a graph showing the surface roughness of the height of the resist R1 with respect to the number of times the argon plasma irradiation process is performed. The horizontal axis in FIG. 14 represents the number of times of argon plasma irradiation. The vertical axis in FIG. 14 represents the surface roughness of the resist R1. The plasma irradiation time per time is 120 seconds. Moreover, the number of times of plasma irradiation means that the resist etching process is interrupted twice and the argon plasma is irradiated. In this case, the resist etching process is performed three times.

  As shown in FIG. 14, when the argon plasma irradiation process is performed once, the surface roughness σ of the resist R1 is about 0.09 μm. Even if the argon plasma irradiation process is performed many times, the surface roughness σ of the resist R1 hardly changes. Therefore, the number of times of performing the argon plasma irradiation process may be one or more. In other words, if the plasma irradiation time per time is sufficient, the number of executions is not relevant.

7-3. Uneven shape In the above experiment, the surface roughness of the resist R1 was examined. In this experiment, the presence or absence of the argon plasma irradiation process was compared with the sample in which the sapphire wafer was etched. As a result, the surface roughness of the height of the sapphire substrate subjected to the argon plasma irradiation process was about 0.08 μm. The surface roughness of the height of the sapphire substrate that was not subjected to the argon plasma irradiation step was about 0.16 μm. Thus, the processing accuracy of the uneven shape of the sapphire substrate is higher when the argon plasma irradiation process is performed.

8). Modification 8-1. Plasma Irradiation Process In this embodiment, an argon plasma irradiation process for irradiating argon plasma is performed between the first resist etching process and the second resist etching process. However, the plasma is not limited to argon plasma. That is, any rare gas of He, Ne, Kr, Xe, and Rn may be used instead of Ar.

8-2. Etching Gas for Resist Etching Step A chlorine-based gas can be used as an etching gas for etching the resist R1. For _{example, Cl 2, SiCl 4, BCl} 3, etc. CCl ₄ and the like. However, it is better to use different gases for the etching gas for etching the resist R1 and the etching gas for etching the wafer W1. This is because in the first resist etching step (S210) and the second resist etching step (S230), the resist R1 can be etched under the condition that the first surface W1a of the wafer W1 is not etched so much.

8-3. Resist Pattern Shape and Arrangement In this embodiment, the resist shape is a truncated cone shape or a polygonal truncated cone shape. However, the resist shape may be a cylindrical shape or a polygonal column shape. An angle θ1 formed by the inclined surface R1a of the resist R1 and the first surface W1a of the wafer W1 is in the range of 75 ° to 90 °. That is, the following equation holds.
75 ° ≦ θ1 ≦ 90 °

  Further, the resist is arranged in a honeycomb shape arranged at the apex and center of the hexagon. However, the arrangement may be different from the honeycomb shape.

8-4. Crystal plane of sapphire In this embodiment, c-plane sapphire is used as the wafer W1. However, you may use the sapphire wafer which has other crystal planes, such as a surface sapphire.

9. Summary of this Embodiment As described above in detail, the method for manufacturing a sapphire substrate according to this embodiment includes a first resist pattern forming step for forming a first resist pattern by a photolithography technique, and a first resist. A second resist pattern forming step of etching the pattern to form a second resist pattern. The second resist pattern forming step includes a plasma irradiation step for discharging the charged resist. In this manufacturing method, it is possible to suppress the formation of an asymmetric resist pattern due to the resist being charged during the etching. Therefore, a resist pattern having excellent symmetry can be formed. Thereby, the processing precision of the uneven | corrugated shape in the sapphire substrate manufactured is high.

(Second Embodiment)
A second embodiment will be described. In the present embodiment, a semiconductor light emitting device is manufactured using the sapphire substrate manufactured by the method for manufacturing a sapphire substrate of the first embodiment. Here, a manufacturing method of a group III nitride semiconductor light emitting device will be described as an example.

1. 1. Manufacturing method of semiconductor light emitting device 1-1. First, the sapphire substrate 100 is manufactured using the method for manufacturing a sapphire substrate described in the first embodiment.

1-2. Next, as shown in FIG. 15, a group III nitride semiconductor layer is formed on the first surface 100a of the sapphire substrate 100 by MOCVD. Here, from the first surface 100a of the sapphire substrate 100, the buffer layer 120, the n-type contact layer 130, the n-type ESD layer 140, the n-type superlattice layer 150, the light emitting layer 160, the p-type superlattice layer 170, and the p-type contact. The layers 180 are formed in this order.

1-3. Electrode forming step Then, a part of the n-type contact layer 130 is exposed by etching using ICP or the like. Next, an n-electrode N1 is formed on the exposed n-type contact layer 130. Further, the p-electrode P1 is formed on the p-type contact layer 180. Thus, an electrode is formed on the group III nitride semiconductor layer.

1-4. Element partitioning step Further, grooves for partitioning the element are formed. Therefore, etching such as ICP may be performed.

1-5. Element Isolation Step Next, the sapphire substrate 100 is divided into chip sizes. For this purpose, a laser irradiation device or a braking device may be used. Thereby, the light emitting element 10 is manufactured.

2. Modification 2-1. Manufacturing Process In this embodiment, the element partitioning process was performed after the exposed portion of the n-type contact layer 130 for forming the n-electrode N1 was provided by etching. However, the step of forming the exposed portion and the element partitioning step may be performed in the same step.

3. Summary of this Embodiment As described in detail above, the method for manufacturing a semiconductor light emitting device according to this embodiment uses the sapphire substrate 100 manufactured by the method for manufacturing a sapphire substrate according to the first embodiment. Manufacturing.

  Note that this embodiment is merely an example, and does not limit the technique of this specification. Accordingly, the technology of the present specification can be variously improved and modified without departing from the gist thereof. For example, it is not limited to the metal organic chemical vapor deposition method (MOCVD method). Other crystal growth methods such as the HVPE method may be used.

A. Supplementary Note In the second resist pattern forming step, the flat surface of the first resist pattern is eliminated to form the second resist pattern. The second resist pattern does not have a flat surface.

DESCRIPTION OF SYMBOLS 10 ... Light emitting element P1 ... p electrode N1 ... n electrode 100 ... Sapphire substrate 100a ... 1st surface 100b ... 2nd surface 110 ... Convex part 111 ... Top part 112 ... Conical surface 113 ... Bottom part W1 ... Wafer W1a ... 1st surface W1b ... 2nd surface R0, R1, R2, R3 ... resist R1a, R2a ... inclined surface R1b ... surface 1000 ... etching apparatus

Claims (7)

In the method of manufacturing a sapphire substrate,
A first resist pattern forming step of forming a first resist pattern on the first surface of the sapphire wafer by photolithography;
A second resist pattern forming step of forming a second resist pattern by etching the first resist pattern;
A sapphire wafer etching step of etching the first surface of the sapphire wafer on which the second resist pattern is formed;
Have
The second resist pattern forming step includes:
In the first period,
A first resist etching step of etching the first resist pattern by supplying a chlorine-based gas to the first resist pattern;
In a second period following the first period,
A plasma irradiation step of irradiating the first resist pattern with a rare gas that has been converted into plasma;
In a third period following the second period,
A second resist etching step of forming the second resist pattern by etching the first resist pattern by supplying a chlorine-based gas to the first resist pattern;
A method for producing a sapphire substrate, comprising: In the manufacturing method of the sapphire substrate according to claim 1,
The first resist etching step and the second resist etching step are:
Adjusting the shape of the first resist pattern to the shape of the second resist pattern;
The plasma irradiation step,
A method of manufacturing a sapphire substrate, which is performed while the shape of the first resist pattern is being adjusted. In the manufacturing method of the sapphire substrate according to claim 1 or 2,
The first resist pattern is:
A first intersecting surface intersecting the first surface of the sapphire wafer;
The second resist pattern is:
A second intersecting surface intersecting the first surface of the sapphire wafer;
The angle formed by the first intersecting surface and the first surface is:
Within the range of 75 ° to 90 °,
The angle formed by the second intersecting surface and the first surface is
A method for producing a sapphire substrate, which is within a range of 45 ° to 65 °. In the manufacturing method of the sapphire substrate according to claim 1 or 2,
The first resist pattern is:
A first intersecting surface intersecting the first surface of the sapphire wafer;
The second resist pattern is:
A second intersecting surface intersecting the first surface of the sapphire wafer;
The angle formed by the second intersecting surface and the first surface is
A method for manufacturing a sapphire substrate, wherein the angle is 10 ° or more smaller than an angle formed by the first intersecting surface and the first surface. In the manufacturing method of the sapphire substrate of any one of Claim 1- Claim 4,
The shape of the first resist pattern is:
It has a truncated cone shape or polygonal truncated cone shape,
The shape of the second resist pattern is
A method for manufacturing a sapphire substrate, characterized by having a conical shape or a polygonal pyramid shape. In the manufacturing method of the sapphire substrate of any one of Claim 1- Claim 5,
At the start of the plasma irradiation process,
Start supplying the noble gas,
At the end of the plasma irradiation step,
A method for manufacturing a sapphire substrate, wherein the supply of the rare gas is stopped. A sapphire substrate manufacturing process for manufacturing a sapphire substrate by the method for manufacturing a sapphire substrate according to any one of claims 1 to 6,
A semiconductor layer forming step of forming a group III nitride semiconductor layer on the first surface of the sapphire substrate;
An electrode forming step of forming an electrode on the group III nitride semiconductor layer;
A method for producing a Group III nitride semiconductor light-emitting device, comprising:

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