CN111725063B - Etching method of semiconductor substrate - Google Patents
Etching method of semiconductor substrate Download PDFInfo
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- CN111725063B CN111725063B CN202010567655.2A CN202010567655A CN111725063B CN 111725063 B CN111725063 B CN 111725063B CN 202010567655 A CN202010567655 A CN 202010567655A CN 111725063 B CN111725063 B CN 111725063B
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- 239000000758 substrate Substances 0.000 title claims abstract description 116
- 238000005530 etching Methods 0.000 title claims abstract description 108
- 238000000034 method Methods 0.000 title claims abstract description 85
- 239000004065 semiconductor Substances 0.000 title claims abstract description 84
- 230000001965 increasing effect Effects 0.000 claims abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 23
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 11
- 235000012239 silicon dioxide Nutrition 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 7
- 229910052786 argon Inorganic materials 0.000 claims description 6
- 239000007789 gas Substances 0.000 description 14
- 229910004298 SiO 2 Inorganic materials 0.000 description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 239000002131 composite material Substances 0.000 description 6
- 230000005284 excitation Effects 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- -1 argon ions Chemical class 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 235000019820 disodium diphosphate Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000001000 micrograph Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The embodiment of the invention provides a method for etching a semiconductor substrate, which comprises the following steps: etching the mask pattern covered on the semiconductor substrate by adjusting the designated process parameters so that the lateral shrinkage rate of the mask pattern is greater than that of the semiconductor substrate; and etching the semiconductor substrate covered with the etched mask pattern to obtain a substrate pattern with a desired morphology. According to the etching method of the semiconductor substrate, provided by the embodiment of the invention, the platform at the top of the cross section appearance of the substrate pattern can be avoided, namely, the substrate pattern with the expected appearance can be obtained, so that the process window of the semiconductor substrate can be increased, and the process requirement can be met.
Description
Technical Field
The invention relates to the technical field of microelectronics, in particular to an etching method of a semiconductor substrate.
Background
The PSS (PATTERNED SAPP Substrates) technology, which is a patterned sapphire substrate, is a method currently in widespread use to improve the light extraction efficiency of GaN (gallium nitride) based LED devices. At present, siO 2 PSS composite substrates are continuously appeared on the market, wherein the conical pattern is of a SiO 2+Al2O3 composite structure, namely, the upper part of the triangular section of the conical pattern is a SiO 2 layer, the height is generally 1.87 mu m, the lower part of the triangular section is an Al 2O3 layer, and the height is generally 200nm-400nm.
The process manufacturing basic flow of the composite substrate is as follows: firstly, plating a SiO 2 layer on a sapphire plane substrate (namely, an Al 2O3 substrate); then, the SiO 2 layer is etched by adopting a photoetching and plasma etching method to form a conical pattern (the axial section is triangular). In the etching process, since the etching selectivity of the SiO 2 layer to the photoresist mask is about 1.1, and the etching selectivity of the Al 2O3 layer to the photoresist mask is about 0.9, that is, the etching selectivity of the SiO 2 layer to the photoresist mask is relatively high, the lateral shrinkage speed of the photoresist mask when the SiO 2 layer is etched is slower than that when the Al 2O3 layer is etched, so that a platform appears at the top of the cross-sectional morphology of the finally obtained substrate pattern, as shown in the region a in fig. 1, and the process window of the SiO 2 layer is smaller, and cannot meet the process requirements.
Disclosure of Invention
The embodiment of the invention aims at solving at least one of the technical problems in the prior art, and provides a method for etching a semiconductor substrate, which can avoid the occurrence of a platform at the top of the cross-section morphology of a substrate pattern, thereby enlarging the process window of the semiconductor substrate and meeting the process requirements.
In order to achieve the object of the embodiment of the present invention, there is provided an etching method of a semiconductor substrate, including:
Etching a mask pattern covered on a semiconductor substrate by adjusting specified process parameters so that the lateral shrinkage rate of the mask pattern is greater than that of the semiconductor substrate;
and etching the semiconductor substrate covered with the etched mask pattern to obtain a substrate pattern with a desired morphology.
Optionally, the specified process parameters include reaction pressure;
The etching the mask pattern on the semiconductor substrate by adjusting the designated process parameters comprises the following steps:
and the reaction pressure is increased, and the mask pattern is etched.
Optionally, the value range of the reaction pressure is 5mT-50mT.
Optionally, the specified process parameters further include an etching gas having an etching rate to the mask pattern that is greater than an etching rate to the semiconductor substrate.
Optionally, the etching the mask pattern on the semiconductor substrate by adjusting the specified process parameters includes:
and adding at least one of argon and nitrogen into the semiconductor cavity, and etching the mask pattern.
Optionally, the specified process parameters further include bias power;
the etching of the mask pattern on the semiconductor substrate by adjusting the specified process parameters further comprises:
And increasing the bias power and etching the mask pattern.
Optionally, the bias power has a value ranging from 800W to 1200W.
Optionally, before the etching the mask pattern on the semiconductor substrate by adjusting the specified process parameters, the method further comprises:
And setting the process duration of etching the mask pattern according to the width of the transverse section of the mask pattern before etching.
Optionally, the semiconductor substrate includes an alumina substrate and a silicon dioxide layer disposed on the alumina substrate; the mask pattern is formed on the silicon dioxide layer and is made of photoresist; or alternatively
The semiconductor substrate comprises a silicon dioxide substrate; the mask pattern is formed on the silicon dioxide substrate and is made of photoresist.
Optionally, the etching the semiconductor substrate covered with the etched mask pattern includes:
etching the semiconductor substrate to obtain a first pattern, wherein the etching height of the first pattern reaches the target etching height;
And etching the first pattern to obtain the substrate pattern with the expected shape by modifying the cross-sectional shape of the first pattern.
The embodiment of the invention has the following beneficial effects:
According to the method for etching the semiconductor substrate, disclosed by the embodiment of the invention, the step of etching the mask pattern is added before the semiconductor substrate is etched, and the mask pattern covered on the semiconductor substrate is etched by adjusting the designated process parameters, so that the transverse shrinkage rate of the mask pattern is larger than that of the semiconductor substrate, the problem that the transverse shrinkage rate of the mask is slower during the subsequent etching of the semiconductor substrate can be solved, and the problem that a platform appears at the top of the cross section morphology of the substrate pattern due to the slower transverse shrinkage rate of the mask pattern can be avoided, so that the substrate pattern with the expected morphology can be obtained, the process window of the semiconductor substrate can be further increased, and the process requirements are met.
Drawings
FIG. 1 is a scanning electron microscope image of a triangular cross-sectional morphology of a composite substrate obtained by a conventional etching method;
FIG. 2 is a block flow diagram of a method for etching a semiconductor substrate according to an embodiment of the present invention;
fig. 3 is a process diagram of an etching method of a semiconductor substrate according to an embodiment of the present invention.
Detailed Description
In order to enable those skilled in the art to better understand the technical scheme of the present invention, the following describes in detail the etching method of the semiconductor substrate provided by the embodiment of the present invention with reference to the accompanying drawings.
Referring to fig. 2, the method for etching a semiconductor substrate provided in this embodiment includes:
S1, etching a mask pattern covered on a semiconductor substrate by adjusting specified process parameters so that the transverse shrinkage rate of the mask pattern is larger than that of the semiconductor substrate;
s2, etching the semiconductor substrate covered with the etched mask pattern to obtain a substrate pattern with a desired morphology.
The step S1 and the step S2 each adopt the following etching process to etch the mask pattern and the semiconductor substrate, respectively, and are different in the process parameters adopted. Specifically, the etching process is as follows: introducing etching gas into the semiconductor chamber, and starting an excitation power supply (such as a radio frequency power supply) and a bias power supply, wherein the excitation power supply applies excitation power to the upper electrode so as to excite the etching gas in the semiconductor chamber to form plasma; the bias power supply applies bias power to the lower electrode to attract the plasma etch mask pattern or the semiconductor substrate. The process parameters of the etching process mainly include the type and flow rate of the etching gas, the exciting power, the bias power, the reaction pressure (i.e., the chamber pressure of the semiconductor chamber), the process duration, and the like.
Before the step S1, a mask layer is formed on the semiconductor substrate, and then the mask layer is etched by photolithography to form a mask pattern. As shown in fig. 3 (1), a mask pattern 1 is obtained by a photolithography process, and the cross-sectional shape of the mask pattern 1 is approximately a square, and the side length D (width and height) of the square is, for example, 2.0 to 2.1 μm.
In the above step S1, the mask pattern is etched by adjusting the specified process parameters so that the lateral shrinkage rate of the mask pattern is greater than that of the semiconductor substrate. As shown in fig. 3 (2), a mask pattern 1a after etching is obtained, and the lateral width of the mask pattern 1a is narrowed in the X direction, that is, is referred to as lateral shrinkage, via step S1. The lateral width of the etched mask pattern 1a is smaller than the side length D of the square cross section of the mask pattern 1 before etching. In this way, the mask pattern is etched in advance in the X direction before the step S2 is performed, so that the problem of slower transverse shrinkage rate of the mask can be solved when the step S2 is performed to etch the semiconductor substrate, the occurrence of a platform at the top of the cross-sectional morphology of the substrate pattern due to the slower transverse shrinkage rate of the mask pattern is avoided, the process window of the semiconductor substrate can be further increased, and the process requirements are met.
In some embodiments, the specified process parameter comprises reaction pressure. In this case, the step S1 includes:
and (3) increasing the reaction pressure and etching the mask pattern.
The higher the reaction pressure, the faster the lateral shrinkage rate of the mask pattern; otherwise, the slower. Based on this, in the above step S1, by setting a higher reaction pressure to etch the mask pattern, it is possible to achieve that the lateral shrinkage rate of the mask pattern is larger than that of the semiconductor substrate.
Optionally, in the step S1, the reaction pressure is in a range of 5mT to 50mT. By setting the reaction pressure within this range, on the one hand, the lateral shrinkage rate of the mask pattern can be effectively improved; on the other hand, the excessive longitudinal etching rate of the mask pattern caused by the excessive reaction pressure can be avoided, so that the excessive sacrifice of the etching height of the mask pattern is avoided.
On the basis of adjusting the reaction pressure, the lateral shrinkage rate of the mask pattern can be further improved by combining with the adjustment of other specified process parameters. For example, the specified process parameters further include an etching gas having an etching rate for the mask pattern greater than an etching rate for the semiconductor substrate, and the step S1 includes:
At least one of argon and nitrogen is added to the semiconductor chamber, and the mask pattern is etched. The etching gas can ionize to form heavy ions so as to achieve the purpose of enhancing physical bombardment effect, and on the basis, the transverse etching rate can be effectively improved by combining the action of high reaction pressure. Of course, in practical applications, other etching gases having an etching rate for the mask pattern greater than the etching rate for the semiconductor substrate may be used.
As another example, the specified process parameters described above may also include bias power. In this case, the step S1 includes:
And (5) increasing the bias power and etching the mask pattern.
The higher the bias power, the faster the lateral shrinkage rate of the mask pattern; otherwise, the slower. In this way, in step S1, the mask pattern is etched by setting the higher bias power in addition to setting the higher reaction pressure, so that the lateral shrinkage rate of the mask pattern can be further improved.
Optionally, in the step S1, the bias power has a value ranging from 800W to 1200W. By setting the bias power within this range, the lateral shrinkage rate of the mask pattern can be effectively increased.
Before the step S1, the method further includes: the process duration of etching the mask pattern (i.e., step S1 described above) may be set according to the width of the lateral cross section of the mask pattern before etching (e.g., the side length D of the square cross section of the mask pattern 1 described above). Specifically, the larger the width of the transverse section of the mask pattern is, the longer the process time of the step S1 is; on the contrary, the smaller the width of the transverse cross section of the mask pattern, the longer the process time of the step S1 is. For example, if the width of the lateral cross section of the mask pattern is in the range of 2 μm to 2.1 μm, the process duration for etching the mask pattern is in the range of 2min to 5min.
In this embodiment, the mask pattern may be etched according to a set process duration.
The etching method of the semiconductor substrate provided by the embodiment of the invention can be applied to a plurality of different semiconductor substrates, for example, the semiconductor substrate is a composite substrate, and comprises an alumina substrate (Al 2O3 substrate) and a silicon dioxide layer (SiO 2 layer) arranged on the alumina substrate; the mask pattern 1a is formed on the silicon oxide layer and is made of photoresist. As another example, the semiconductor substrate includes a silicon dioxide substrate, and a mask pattern is formed on the silicon dioxide substrate and made of photoresist.
In the step S1, at least one of argon and nitrogen may be used as an etching gas, and argon ions formed by argon may be used to etch a mask pattern made of photoresist, and the silicon dioxide layer may be etched more slowly, so as to increase the lateral shrinkage rate of the mask pattern.
Optionally, the step S2 further includes:
s21, etching the semiconductor substrate to obtain a first pattern, wherein the etching height of the first pattern reaches the target etching height;
s22, etching the first pattern to obtain a substrate pattern with a desired shape by modifying the cross-sectional shape of the first pattern.
The specific processes of step S21 and step S22 are similar to the etching process of step S1, and only the process parameters are different.
As shown in fig. 3 (3), the first pattern 2 and the mask pattern 1b of the semiconductor substrate, both of which have isosceles trapezoid cross-sectional shapes, are obtained through the above step S21. The step S21 is mainly to increase the etching height in the Y direction so that the etching height of the first pattern 2 reaches the target etching height to meet the process requirement.
As shown in fig. 3 (4), a final pattern of the semiconductor substrate is obtained in step S22, the cross-sectional shape of which is triangular, and the upper part of the triangle is the silicon dioxide layer 2a and the lower part is the aluminum oxide substrate 3 for the composite substrate.
In practical applications, the process parameters adopted in step S22 are different from the process parameters adopted in step S21 at least in that: different etching gas flows and/or bias powers are used. Specifically, the etching gas flow rate adopted in step S22 is smaller than the etching gas flow rate adopted in step S21; the bias power used in step S22 is higher than the bias power used in step S21, so that step S22 can play a role in modifying the morphology of the semiconductor substrate, for example, adjusting the sidewall morphology and the inclination angle of the substrate pattern.
Optionally, the etching gases used in the step S21 and the step S22 include boron chloride. In addition, the bias power adopted in the step S21 is 500W-800W, the reaction pressure is 2.6mT, and the etching gas flow is 120sccm; the bias power used in step S22 was 800W, the reaction pressure was 2.6mT, and the etching gas flow rate was 60sccm.
It should be noted that, the above step S2 is not limited to the above scheme provided in the present embodiment, and may be freely set according to specific needs in practical applications.
In summary, the method for etching a semiconductor substrate according to the embodiment of the present invention adds a step of etching a mask pattern before etching the semiconductor substrate, and the step etches the mask pattern covered on the semiconductor substrate by adjusting specified process parameters, so that the lateral shrinkage rate of the mask pattern is greater than that of the semiconductor substrate, and the problem that the lateral shrinkage rate of the mask is slower during subsequent etching of the semiconductor substrate can be overcome, thereby avoiding the occurrence of a platform on top of the cross-sectional morphology of the substrate pattern due to the slower lateral shrinkage rate of the mask pattern, and thus obtaining a substrate pattern with a desired morphology, and further increasing the process window of the semiconductor substrate, and meeting the process requirements.
It is to be understood that the above embodiments are merely illustrative of the application of the principles of the present invention, but not in limitation thereof. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the invention, and are also considered to be within the scope of the invention.
Claims (7)
1. A method of etching a semiconductor substrate, comprising:
Etching a mask pattern covered on a semiconductor substrate by adjusting specified process parameters so that the transverse shrinkage rate of the mask pattern is larger than that of the semiconductor substrate, wherein the cross section of the mask pattern before etching along the Y direction comprises a first rectangular surface, the cross section of the mask pattern after etching along the Y direction comprises a second rectangular surface and a trapezoid surface connected with the upper side of the second rectangular surface, the bottom edge width of the trapezoid surface is larger than the top edge width, and the bottom edge of the trapezoid surface coincides with the top edge of the second rectangular surface; the width of the top edge of the trapezoid surface is smaller than the width of the first rectangle surface along the X direction, the Y direction is perpendicular to the X direction, and the X direction is parallel to the plane of the semiconductor substrate;
Etching the semiconductor substrate covered with the etched mask pattern to obtain a substrate pattern with a triangular cross-section shape;
wherein, the etching the mask pattern covered on the semiconductor substrate by adjusting the designated technological parameters comprises the following steps:
Argon is added into the semiconductor cavity, and the mask pattern is etched; wherein the semiconductor substrate comprises an alumina substrate and a silicon dioxide layer arranged on the alumina substrate; the mask pattern is formed on the silicon dioxide layer and is made of photoresist.
2. The method of etching a semiconductor substrate of claim 1, wherein the specified process parameters include a reaction pressure;
the etching the mask pattern covered on the semiconductor substrate by adjusting the designated process parameters comprises the following steps:
and the reaction pressure is increased, and the mask pattern is etched.
3. The method of etching a semiconductor substrate according to claim 2, wherein the reaction pressure has a value in a range of 5mT to 50mT.
4. The method of etching a semiconductor substrate of claim 2, wherein the specified process parameters further comprise bias power;
the method for etching the mask pattern covered on the semiconductor substrate by adjusting the designated process parameters further comprises the following steps:
And increasing the bias power and etching the mask pattern.
5. The method of etching a semiconductor substrate according to claim 4, wherein the bias power has a value in a range of 800W to 1200W.
6. The method of etching a semiconductor substrate according to claim 1, further comprising, before said etching the mask pattern overlying the semiconductor substrate by adjusting the specified process parameters:
And setting the process duration of etching the mask pattern according to the width of the transverse section of the mask pattern before etching.
7. The method for etching a semiconductor substrate according to any one of claims 1 to 6, wherein the etching the semiconductor substrate covered with the mask pattern after etching comprises:
etching the semiconductor substrate to obtain a first pattern, wherein the etching height of the first pattern reaches the target etching height;
and etching the first pattern to obtain the substrate pattern with the triangular cross-sectional morphology by modifying the cross-sectional morphology of the first pattern.
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| CN202010567655.2A CN111725063B (en) | 2020-06-19 | 2020-06-19 | Etching method of semiconductor substrate |
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| JP2016012664A (en) * | 2014-06-30 | 2016-01-21 | 豊田合成株式会社 | Sapphire substrate manufacturing method and group iii nitride semiconductor light emitting element manufacturing method |
| CN105336659A (en) * | 2014-07-14 | 2016-02-17 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Isolation groove etching method of GaN-based LED chip |
| CN105513942A (en) * | 2014-09-22 | 2016-04-20 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Etching method |
| CN110649134A (en) * | 2018-06-26 | 2020-01-03 | 北京北方华创微电子装备有限公司 | Manufacturing method of patterned substrate, patterned substrate and light emitting diode |
| CN110867503A (en) * | 2018-08-28 | 2020-03-06 | 北京北方华创微电子装备有限公司 | Manufacturing method of patterned substrate, patterned substrate and light emitting diode |
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