CN103311092A - Method for etching grooves - Google Patents
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- CN103311092A CN103311092A CN2012100640704A CN201210064070A CN103311092A CN 103311092 A CN103311092 A CN 103311092A CN 2012100640704 A CN2012100640704 A CN 2012100640704A CN 201210064070 A CN201210064070 A CN 201210064070A CN 103311092 A CN103311092 A CN 103311092A
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Abstract
A method for etching grooves comprises: providing a semiconductor substrate on which an etching stop layer and a first dielectric layer are formed in sequence; forming a photoresist mask; performing a first etching so that openings, each of which is with a first width, are formed on the first dielectric layer; performing a first depositing and thus a second dielectric layer is formed; performing a second etching on the second dielectric layer and removing the second dielectric layer that is on the first dielectric layer and the bottom walls of the openings so that the second dielectric layer that is on the side walls of the openings, each of which is with the first width, is remained; performing a second depositing and depositing a third dielectric layer so that the third dielectric layer at least fills up the openings; flattening the third dielectric layer until the second dielectric layer is exposed; performing a third etching to remove the second dielectric layer so that gaps are formed between the first dielectric layer and the third dielectric layer; and performing a fourth etching to etch the first dielectric layer and the third dielectric layer so that the gas are widened to form grooves. According to the method, a more advanced process dimension requirement can be realized with current exposure equipment.
Description
Technical field
The present invention relates to field of semiconductor fabrication, relate in particular to a kind of lithographic method of groove of double-pattern technical field.
Background technology
For the transistor that integrated number is more on chip, size is less, must develop the photoetching technique that makes new advances constantly to reduce transistor size.
A developing direction of photoetching technique is fundamentally to shorten the optical wavelength that optical lithography adopts.The present photoetching technique wavelength of making great efforts to develop is extreme ultraviolet (EUV) photoetching technique of 13.5nm.Adopt the EUV photoetching technique may obtain characteristic size less than the chip of 32nm.Even compare with the chip that present disposal ability is the most powerful, the chip final speed of employing EUV photoetching also can be fast 100 times, and memory space can be high 100 times.Yet the EUV photoetching technique also has a lot of problems not solve at present, the EUV photoetching technique can't be carried out volume production.
Another developing direction is the double-pattern technology.The principle of double-pattern technology resolves into the lower figure of discrete, the density of two covers with the highdensity circuitous pattern of a cover, then they is printed on the target wafer.Basic step is to print first the figure of half, and spin coating one deck photoresist again after the development is printed second half figure again, utilizes at last hard mask or selective etch to finish whole photoetching process.
With regard to present development, realize that the method for double-pattern roughly is divided three classes: autoregistration double-pattern, secondarily etched double-pattern and single etching double-pattern.
Autoregistration type double-pattern (SADP) technology is a kind of in many double-pattern schemes of being assessed by chip manufacturer, although it also has a plurality of different names at present, reduce (pitch reduction), wall mask pattern (spacer mask patterning) or SA double-pattern etc. such as side wall spacers transfer graphic technology (sidewall spacer transfer patterning techniques), pitch.AppliedMaterials and Lam Research two companies all provide autoregistration type double-pattern technical solution at present.Its advantage is to be easy to control alignment precision and live width size, but needs the more mask plate of cost to determine sidewall, and needs more complicated pattern layout to split algorithm.
SADP has the ability to realize having the high density parallel lines of excellent live width and pitch control effect.Can use wall at each side with the lines of photoetching method definition for any given, after removing initial mould material, just can effectively realize doubling of line density.According to the concrete technology flow process, can use wall at give a definition lines or in the negative rubber moulding formula groove structure of giving a definition of positive rubber moulding formula.
Because lines (or groove structure) might not form in lines (or the groove structure) zone that initial lithographic is printed, so chip and mask plate designer need to closely cooperate at work.In addition, side wall spacers can form closed shape usually, thereby needs at least extra cutting mask plate of a step to come the making of completing circuit.Use the SADP technological process of two mask plates to limit to some extent the designer, or under positive rubber moulding formula, obtain to have the line size of variable spacing, or under negative rubber moulding formula, obtain to have the groove physical dimension of variable isolation (lines) width.For memory manufacturer, cost control is vital.SADP will make a lot of existing ripe deposition apparatus have place to show one's prowess, so the method is just becoming the preferred option of 3X even the manufacturing of 2X node memory.
Secondarily etched double-pattern method (DEDP) adopts the double-pattern method of exposure-etching-exposure-etching (LELE), need to be the Asia design of two groups of 64nm with the design decomposition of 32nm, and 64nm just can realize by present state-of-the-art single exposure technology.The principle of decomposing design is with two groups of inferior design overlaids, so just can reconstruct initial design.Two groups of overlapping graphically can realizing by the order of LELE of design.The difficult point of the method is to obtain to have repeatable technique, and need to adopt the Design and manufacture of cheaply technological process, Automated Design decomposition, mask, and the alignment precision of alignment.Complete LELE technique is more consuming time and expensive.Consuming time is because needed before carrying out for the second time exposure the wafer of for the first time exposure to be carried out etching one time.Costliness is because want exposure step repeated.
And single etching double-pattern method is to replace for the first time etch step in exposure, has obtained the flow process (LLE) of exposure-technique-exposure-etching.This flow process still needs two masks and two exposure steps, but etch step in the middle of having saved once.Because do not need wafer is interrupted from double exposure, this can accelerate whole flow process.The unique challenges of LLE is to make the figure that graphically obtains for the first time not be subjected to the impact of for the second time photoetching.Also inherited in addition the difficult point of LELE: need to decompose and make a plate initial design, design need to be in narrower process window (alignment precision) finish overlapping graphically, CD, CDU and LWR need consistent with the 32nm figure like this.
Compare with single imaging technique, the parameter of each node of double-pattern imaging technique such as alignment, CD control and line edge roughness approximately carry out the equal proportion reduction by 0.7.More rigorous Overlay control is the key point of successful implementation double-pattern imaging technique, and it requires the alignment precision (overlay accuracy) of about 2nm.Under former very difficult process environments, carry out dual imaging and further increased the complexity that keeps aspect the lithography alignment precision.Any register partial difference all will cause the change of live width size in the technique.A little deviation of live width all will make the parameters such as width, length and resistance of the gate electrode in the semiconductor device of producing change, and then can reduce the electric property of device.
Summary of the invention
The objective of the invention is under the larger photoetching technique of wavelength, avoid needing Twi-lithography in the double-pattern imaging technique and the difficulty of the alignment precision that produces, realize the etching than fine pattern.
For achieving the above object, the present invention proposes a kind of lithographic method of groove, comprising:
Semiconductor substrate is provided, is formed with successively etching stop layer and first medium layer on the described Semiconductor substrate;
Form the photoresist mask at the first medium layer, carry out the first etching, in the first medium layer, form the opening with first width, then remove remaining photoresist mask;
Carry out the first deposition, on the first medium layer and the sidewall of opening and diapire formation second medium layer;
Described second medium layer is carried out the second etching, remove on the first medium layer and the second medium layer on the opening diapire keeps first medium layer on the described opening sidewalls with first thickness;
Carry out the second deposition, form the 3rd dielectric layer, described the 3rd dielectric layer fills up described opening at least;
Described the 3rd dielectric layer of planarization is to exposing described second medium layer;
Carry out the 3rd etching, remove described second medium layer, between described first medium layer and described the 3rd dielectric layer, to form the slit;
Carry out the 4th etching, the described first medium of etching and described the 3rd medium form groove to widen described slit.
Optionally, the mode of described the first deposition is ald.
Optionally, the mode of described the 4th etching is the atomic layer etching.
Optionally, described first medium layer and the 3rd dielectric layer are polysilicon.
Optionally, described second medium layer is silica or silicon nitride.
Optionally, described the first thickness is 2～3nm.
Optionally, carry out described the 4th etching,, the width that makes final formation groove is half of described the first width.
Optionally, described Semiconductor substrate is silicon substrate.
Optionally, described etching stop layer is amorphous carbon.
Optionally, the formation of photoresist mask is applicable to exposure accuracy less than or equal to the exposure sources of 90nm in the described lithographic method.
Compared with prior art, the present invention can keep under the existing exposure accuracy at exposure sources, reduce largely the size of etching, be easier to utilize existing exposure sources to realize advanced process requirement, to adapt to the integrated circuit (IC) chip live width of more and more dwindling.
Description of drawings
Fig. 1 to Figure 10 is the schematic diagram of lithographic method execution mode of the present invention.
Embodiment
The present invention has only utilized a photoetching, then in conjunction with the effect of four etchings, thereby so that half of the minimum widith that the width of the opening that etching forms can be lithographic accuracy can be reached, avoid again needing Twi-lithography in the double-pattern imaging technique and the difficulty of the alignment precision that produces.Like this, can keep reducing largely to form the size of groove, to adapt to the integrated circuit (IC) chip live width of more and more dwindling under the existing exposure accuracy at exposure sources.The exposure accuracy of the maximum that can reach as existing exposure sources is 90nm, and existing advanced person's integrated circuit technology node is 18～23nm.Utilize method of the present invention, can be easier to utilize existing exposure sources to realize advanced process requirement.Lithographic method of the present invention mainly comprises etching four times:
Etching is to form the photoresist mask by photoetching for the first time, and then etching forms a series of openings in the first medium layer on semiconductor base, and the width of its split shed is designated as the first width.
Carry out after being etched in for the second time deposition skim second medium layer, etching is removed unnecessary second medium layer, so that the second medium layer only is formed on the sidewall of opening.
Be etched in for the third time and carry out after deposition the 3rd dielectric layer is filled and led up opening, etching is removed thin layer second medium layer for the third time, to form the gap between first medium layer and the 3rd dielectric layer.
The 4th etching is etching first medium layer and the 3rd dielectric layer, enlarges so that the gap of formation after for the third time etching removal second medium layer is given, and is preferably half that expand as the first width.
In above-mentioned technical process, wherein, it is thin that the thickness of the second medium layer that forms at opening sidewalls need to be tried one's best, smaller for the impact for the size of the opening between first medium layer and the 3rd dielectric layer in follow-up the 4th etching like this.Preferably, the second medium layer is as thin as 2～3nm.
In addition, in the 4th etching, when etching first medium layer and the 3rd dielectric layer, the progress of accurately controlling etching is also very important, controls accurately the progress of etching, thereby can control the size of the opening between the first medium layer and the 3rd dielectric layer after the etching.
Concrete, the process flow diagram of lithographic method of the present invention as shown in Figure 1, it comprises:
Step S1: semiconductor base is provided, and it comprises Semiconductor substrate, etching stop layer and first medium layer from bottom to up successively;
Step S2: carry out photoetching and form the photoresist mask;
Step S3: carry out the first etching, in the first medium layer, form a series of openings with first width;
Step S4: carry out the first deposition, on the first medium layer and the sidewall of opening and diapire form the second medium layer;
Step S5: described second medium layer is carried out the second etching, remove on the first medium layer and the second medium layer on the open bottom, keep the part on the described opening sidewalls with first thickness;
Step S6: carry out the second deposition, deposit the 3rd dielectric layer, fill up at least described opening;
Step S7: described the 3rd dielectric layer of planarization is to exposing described second medium layer;
Step S8: carry out the 3rd etching, remove described second medium layer, between described first medium layer and described the 3rd dielectric layer, to form the slit;
Step S9: carry out the described first medium of the 4th etching etching and described the 3rd medium, become groove to widen described slit-shaped.
Because above-mentioned situation, the present invention adopts the method for ald to form the second medium layer, adopts the method for atomic layer etching to widen the gap that removal second medium layer forms afterwards.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can be in the situation that do similar popularization without prejudice to intension of the present invention, so the present invention is not subjected to the restriction of following public implementation.
Step S1: semiconductor base is provided, and it comprises Semiconductor substrate, etching stop layer and first medium layer from bottom to up successively;
As shown in Figure 2, provide semiconductor base, comprise Semiconductor substrate 300, etching stop layer 301 and first medium layer 302.
Wherein, Semiconductor substrate 300 can not limit for the top layer silicon surface of monocrystalline substrate, SOI substrate, gallium arsenide substrate etc.In the present embodiment, it is silicon substrate.
First medium layer 302 can be polysilicon, silicon nitride etc., and still, the material of first medium layer 302 and etching stop layer 301 must be different.
Can form etching stop layer 301 and first medium layer 302 in Semiconductor substrate 300 by depositing operation.
Step S2: carry out photoetching and form the photoresist mask;
Still as shown in Figure 2, provide mask plate 211, first medium layer 302 is carried out photoetching.Comprising spin coating photoresist on first medium layer 302, semiconductor base is sent into exposure sources expose, and then utilize developing liquid developing, in the first medium layer, form photoresist mask, the steps such as cleaning.This is the technology that those skilled in the art were familiar with, and does not explain in detail.
Need to prove, the figure on the mask plate 211 of formation mask pattern is a series of wide equidistant openings, and wherein, the width of opening is a, and the width of opening and the spacing sum between the opening are b.B is the lithographic accuracy of exposure sources in this step.In the present embodiment, with exposure accuracy, namely b is 90nm, and the width a of opening is its half, and namely a is that 45nm is that example is explained technology of the present invention and effect in detail.In the reality, those skilled in the art can easier spread to the practice situation of other exposure accuracy.
Step S3: carry out the first etching, in the first medium layer, form a series of openings with first width;
As mask, first medium layer 302 being carried out etching with the photoresist after developing, is the using plasma dry etching in the present embodiment.Form structure as shown in Figure 3 after the etching, in first medium layer 302, etch a series of openings (not indicating among the figure) with first width.Ignore the impact in the etching, described the first width should be the width a of mask plate opening among the previous step S2, and the distance on the same limit of the correspondence of a certain limit of one of them opening and adjacent apertures is lithographic accuracy b.Same, b is 90nm, a is 45nm.
Then remove remaining photoresist mask.
Step S4: carry out the first deposition, on the first medium layer and the sidewall of opening and diapire form the second medium layer;
As shown in Figure 4, at first medium layer 302 deposition skim second medium layer 303.
The material of second medium layer 303 can be silica, silicon nitride etc.But they should be different from the material of first medium 302 and etching stop layer 301.It is little that the thickness of this skim second medium layer 303 will be tried one's best.Then, the technique of formation second medium layer 303 will can be good at controlling the thickness of second medium layer 303.Can adopt general depositing operation, the therein control by technological parameters such as times realizes the control to second medium layer 303 thickness.
And another more preferably to carry out the first mode that deposits to form skim second medium layer 303 be ald (ALD).Ald be a kind of can be with material with the monatomic form membrane method that is plated in substrate surface in layer.Ald and common chemical deposition have similarity.But in atomic layer deposition process, the chemical reaction of new one deck atomic film is directly to be associated with one deck before, and this mode makes every secondary response only deposit one deck atom.
Concrete, ald is by the pulse of gas phase presoma alternately being passed into reactor and chemisorbed and reaction and formation deposited film on depositing base.Because the surface reaction of ald has from restricted, in fact this from the restricted feature basis of technique for atomic layer deposition just.Constantly repeat thisly just to form needed film from limited reactions.
Adopt HfCl in the present embodiment
4Carry out ald as reactant.Course of reaction is put into basis material as shown in Figure 5 in reactor, the semiconductor base after the basis material is here namely processed through step S3.In reactor, pass into the HfCl of gas phase
4, because the O atom that substrate material surface just has, and and water in air steam formation-OH suspension key.HfCl
4In Cl and H in conjunction with the HCl that generates gaseous state, Hf is attached to substrate material surface by the O atom.Because only have substrate material surface that the O atom is arranged, so, can only form one deck Hf (polymer) on the surface of basis material.
Then, pass into again steam (H
2O), H
2O displaces the Cl ion, forms gaseous state HCl, forms the new O atomic layer of one deck on the surface of Hf simultaneously.So can prepare to carry out the formation of lower one deck Hf.
In said process, preferred process conditions are: reaction temperature is 100～400 ℃, and reaction pressure is less than 10Torr, N
2Perhaps Ar (introduces HfCl as the reaction carrier gas
4, HCl etc.).It is 0.05～10s that reactant passes into the time, and finding time is 0.10～10s.
Same, similar HfCl
4Material, other selection can be selected TDEAH (Hf (DEA)
4), TDMAH (Hf (DMA)
4), TEMAH (Hf (EMA)
4) carry out ald as reactant.
About the technology of ald, also there are many researchs present stage, and the selection of limited enforceable mode only is provided in present specification.
Step S5: described second medium layer is carried out the second etching, remove on the first medium layer and the second medium layer on the open bottom, keep the part on the described opening sidewalls with first thickness;
The second medium layer 303 of etching horizontal direction keeps the part on the opening sidewalls, as shown in Figure 6.Because after this step finished, the thickness of second medium layer 303 was the live width that etching forms in the first thickness effect subsequent technique on the sidewall, so need it narrow.And too narrow, also affect the process of subsequent etching, and be difficult to control process conditions.The thickness of preferred second medium layer 303 is 2～3nm, and namely the first thickness is 2～3nm.
Step S6: carry out the second deposition, form the 3rd dielectric layer, fill up at least described opening;
Carry out the second deposition so that the 3rd dielectric layer 304 fill up at least shown in opening, form structure as shown in Figure 7.
Be deposited as general chemical vapour deposition (CVD) or physical vapour deposition (PVD) herein.The material of the 3rd dielectric layer can be polysilicon, silicon nitride, and silicon nitride etc., still, the material of the 3rd dielectric layer 304 and second medium layer 303, etching stop layer 301 must be different.
Preferably, the 3rd dielectric layer 304 and first medium layer 302 are polysilicon.
Step S7: described the 3rd dielectric layer of planarization is to exposing described second medium layer;
Utilize cmp, planarization the 3rd dielectric layer 304 in the reality, simultaneously, has also exposed first medium layer 302 to exposing second medium layer 303.
Form structure as shown in Figure 8.
Step S8: carry out the 3rd etching, remove described second medium layer, between described first medium layer and described the 3rd dielectric layer, to form the slit;
In this step, utilize wet etching to remove second medium layer 303, as shown in Figure 9, like this, between first medium layer and the 3rd dielectric layer, formed the slit, the width in slit is aforesaid the first thickness, is 2～3nm.Etching agent is the HF aqueous solution.
Step S9: carry out the 4th etching, the described first medium of etching and described the 3rd medium are to widen described slit to form groove.
Form structure as shown in figure 10, the width of the groove of formation is half of a, i.e. 22nm～23nm.
Those skilled in the art easily spread to, and in practice, the groove or the lines that use method of the present invention to form other width also are feasible.
In this step, the size that first medium layer 302 and the 3rd dielectric layer 304 are etched, namely going up in the step and removing the size of the slit that stays after the second medium layer 303 being widened is exactly size after the final etching that forms of lithographic method of the present invention, and whether it can accurately be controlled also is very important.
Can adopt general etching technics, the therein control by technological parameters such as times realizes the control to size after the etching.
And in the present embodiment, what provide is preferred, controls better that the lithographic method of size is the atomic layer etching after the etching.The atomic layer etching can realize that the etching of the medium that is etched being carried out single atomic layer peels off, thereby can accurately be controlled the size that forms after its etching.
First piece of patent document about atomic layer etching (ALE) is on August 31st, 1987, and publication number is US 4756794, after this, the paper publishing of correlative study is arranged successively, as:
Atomic?layer?etching?of?silicon?by?using?a?low-angle?forward?reflected?ar?neutral?beam，2006.IEEE.
A?molecular?dynamics?investigation?of?fluorocarbon?based?layer-by-layer?etching?of?silicon?and?SiO
2，J.Appl.Phys.，2007.2.15
A?Two-Step-Recess?Process?Based?on?Atomic-Layer?Etching?for?High-Performance?In
0.52Al
0.48As/In
0.53Ga
0.47As?p-HEMTs，2008.IEEE.
Novel Damage-Free High-k Removal for sub-32nm Metal Gate/High-k LSTP CMOSFETs using Neutral Beam-Assisted Atomic Layer Etching, the papers such as 2011.VLST-TSA. all are studied discussion about the correlation technique of ALE.
Summary is got up, the basic principle of atomic layer etching (ALE) is based on such fact: the bond energy between the bond energy of the most surperficial atom of semiconductor monocrystal silicon materials and internal layer atom and the atom of internal layer is different, and the bond energy of the most surperficial atom and internal layer atom is less than the bond energy between the internal layer atom, and namely the bond energy between ground floor and the second layer atom is smaller.Again by the other auxiliary atom of reaction bonded on the surface atom layer (such as Cl, Hr etc.), so that the bond energy between basis material ground floor and the second layer atom is subject to the impact of auxiliary atom and further reduces, thereby the bond energy and the interatomic bond energy of internal layer that have amplified between basis material ground floor and the second layer atom are poor.And then the gas that will import auxiliary atom extracts out fully, by energy excitation under vacuum environment, so that the chemical bond between basis material ground floor and the second layer atom disconnects, peels off the outermost layer atomic layer.Like this, just realized the effect that one deck atom one deck atom is etched away.Such as, can process silicon chip surface with chlorine, then, in vacuum environment, detach, just can be removed the outermost layer atom.
In the present embodiment, can adopt the semiconductor base after processing through step S8 is placed in the vacuum that vacuum degree is 0.1～1mT, at 30～70 ℃, continue to pass into Cl
2Reach 10～100s, then remaining reacting gas and product in the extraction cavity are used less than 27eV energy again under the environment of vacuum degree 0.1～100mt, and atomic density is 1E14～1E16/cm
2Ne atom bombardment surface, the effect that can realize peeling off the individual layer atomic layer, thus realize the atomic layer etching.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.
Although the present invention discloses as above with preferred embodiment, yet is not to limit the present invention.Any those of ordinary skill in the art, do not breaking away from the technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1. the lithographic method of a groove is characterized in that, comprising:
Semiconductor substrate is provided, is formed with successively etching stop layer and first medium layer on the described Semiconductor substrate;
Form the photoresist mask at the first medium layer, carry out the first etching, in the first medium layer, form the opening with first width, then remove remaining photoresist mask;
Carry out the first deposition, on the first medium layer and the sidewall of opening and diapire formation second medium layer;
Described second medium layer is carried out the second etching, remove on the first medium layer and the second medium layer on the opening diapire keeps first medium layer on the described opening sidewalls with first thickness;
Carry out the second deposition, form the 3rd dielectric layer, described the 3rd dielectric layer fills up described opening at least;
Described the 3rd dielectric layer of planarization is to exposing described second medium layer;
Carry out the 3rd etching, remove described second medium layer, between described first medium layer and described the 3rd dielectric layer, to form the slit;
Carry out the 4th etching, the described first medium of etching and described the 3rd medium form groove to widen described slit.
2. lithographic method as claimed in claim 1 is characterized in that, the mode of described the first deposition is ald.
3. lithographic method as claimed in claim 1 is characterized in that, the mode of described the 4th etching is the atomic layer etching.
4. lithographic method as claimed in claim 1 is characterized in that, described first medium layer and the 3rd dielectric layer are polysilicon.
5. lithographic method as claimed in claim 1 is characterized in that, described second medium layer is silica or silicon nitride.
6. lithographic method as claimed in claim 1 is characterized in that, described the first thickness is 2～3nm.
7. lithographic method as claimed in claim 1 is characterized in that, carries out described the 4th etching, and the width that makes final formation groove is half of described the first width.
8. lithographic method as claimed in claim 1 is characterized in that, described Semiconductor substrate is silicon substrate.
9. lithographic method as claimed in claim 1 is characterized in that, described etching stop layer is amorphous carbon.
10. lithographic method as claimed in claim 1 is characterized in that, the formation of photoresist mask is applicable to exposure accuracy less than or equal to the exposure sources of 90nm in the described lithographic method.
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| CN104752198A (en) * | 2013-12-29 | 2015-07-01 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Substrate etching method |
| CN105470117A (en) * | 2014-09-09 | 2016-04-06 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device based on double patterns and manufacturing method thereof and electronic device |
| JP2018182103A (en) * | 2017-04-14 | 2018-11-15 | 東京エレクトロン株式会社 | Etching method |
| CN109148273A (en) * | 2017-06-28 | 2019-01-04 | 中芯国际集成电路制造(上海)有限公司 | The production method of semiconductor structure |
| CN111620297A (en) * | 2020-05-27 | 2020-09-04 | 瑞声声学科技(深圳)有限公司 | Deep cavity etching method |
| WO2021237532A1 (en) * | 2020-05-27 | 2021-12-02 | 瑞声声学科技(深圳)有限公司 | Deep cavity etching method |
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