CN1431680A - Method for forming structure of fine sizes - Google Patents
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- CN1431680A CN1431680A CN 02101821 CN02101821A CN1431680A CN 1431680 A CN1431680 A CN 1431680A CN 02101821 CN02101821 CN 02101821 CN 02101821 A CN02101821 A CN 02101821A CN 1431680 A CN1431680 A CN 1431680A
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Abstract
The invention utilizes the one-off mask or the one-off pattern transfer technique, the self-alignment etch back technique and the traditional sedimentation techinque forms the pattern with superfine size, which is one third of the size the applicable microimage technique forms. By selecting the material to be sedimentated and etched back, the pattern can be the mask or the component itself.
Description
(1) technical field
The relevant a kind of method that forms structure of fine sizes of the present invention, particularly a kind of relevant what forms has the method for minute sized component structure.
(2) background technology
In semi-conductor industry, lithography process is used in the middle of the process that forms integrated circuit on the what semiconductor wafer.A kind of form of emittance in lithography process, ultraviolet for example, by a light shield to semiconductor wafer.Comprise printing opacity and lighttight zone on this light shield, these printing opacities and lighttight zone constitute required pattern.In the various patterns for example the pattern of lock shape can be used on semiconductor wafer to form parallel lead.Ultraviolet ray is with the photoresist layer on the formation of the design transfer on the light shield what semiconductor wafer.Photoresist layer then is developed the unexposed part with exposed part that removes positive photoresist layer or negative photoresist layer.Next can be used in the semiconductor technology of for example implanting ions or etching etc. by the photoresist layer of design transfer or formation.
When the integrated level of integrated circuit improves constantly, the characteristics of semiconductor element have been contracted to the grade of dark this micron.The characteristics of these deep-sub-micrometers comprise the live width or the spacing of metal or polycrystalline silicon conducting wire, or other various geometric properties of semiconductor element.Being used for geometric properties must constantly dwindle, and the improvement of lithography process and equipment or development are also carried out always continuously.For instance, the phase shift lithography process utilize phase displacement light-cover with the exposure light phase shift at pattern edge place to strengthen image contrast.Other lithography process comprises little shadow technology of electron beam (e-beam) and the little shadow technology of X-ray etc.
However, above-mentioned lithography process technology with what deep-sub-micrometer technology still faces the congenital restriction that can't avoid and be difficult to overcome.When the various geometric properties of semiconductor element reach 0.18 micron, 0.13 micron even more small size, problem can get over seriously.Therefore the shortcoming that the above-mentioned traditional handicraft of mirror what is arranged is necessary to develop technology and the technology that a kind of novel progress, and this technology and technology can overcome the congenital restriction of lithography process technology before brand-new revolutionary technological development success.
(3) summary of the invention
A purpose of the present invention is for providing a kind of method that forms structure of fine sizes, and the method can effectively further be dwindled the live width of modern integrated circuits, wherein only uses little shadow technology of mature and feasible.
Another object of the present invention is for providing a kind of method that forms structure of fine sizes, and the method can form a pattern with fine sizes, and its fine sizes only has with 1/3rd of the formed fine sizes of little shadow technology of mature and feasible.
Another purpose of the present invention is for providing a kind of method that forms structure of fine sizes, and the method has excellent critical dimension and pattern line Position Control ability, and technology is simply easy simultaneously.
A kind of method that forms structure of fine sizes according to an aspect of the present invention is characterized in, comprises the following steps: to provide a ground at least, and described ground is provided with a photoresist layer pattern, and described pattern comprises several line style patterns at least; Form a ground floor and cover described pattern and described ground; The described ground floor of etch-back is to expose described ground; Form a second layer and cover described pattern, described ground floor and described ground; The described second layer of etch-back is to expose described pattern and described ground floor; Remove described pattern; Form one the 3rd layer and cover described ground floor, the described second layer and described ground; Etch-back described the 3rd layer to expose described ground; Form one the 4th layer and cover described ground floor, the described second layer, described the 3rd layer of described ground in territory, it is identical with the material that constitutes described ground floor wherein to constitute described the 4th layer material; Etch-back described the 4th layer to expose described ground floor, the described second layer and described the 3rd layer; And remove the described second layer and described the 3rd layer.
A kind of method that forms structure of fine sizes according to a further aspect of the invention, be characterized in, at least comprise the following steps: to provide a ground, described ground has a dielectric layer pattern what on it, wherein, described pattern comprises the distance of whats such as the width adjacent two described line style patterns of several equidistant line style patterns and described line style pattern at least; Form a ground floor and cover described pattern and described ground; The described ground floor of etch-back is to expose described ground; Form a second layer and cover described pattern, described ground floor and described ground; The described second layer of etch-back is to expose described pattern and described ground floor; Remove described pattern; Form one the 3rd layer and cover described ground floor, the described second layer and described ground; Etch-back described the 3rd layer to expose described ground; Form one the 4th layer and cover described ground floor, the described second layer, described the 3rd layer and described ground, wherein, it is identical with the material that constitutes described ground floor to constitute described the 4th layer material; Etch-back described the 4th layer to expose described ground floor, the described second layer and described the 3rd layer; And remove the described second layer and described the 3rd layer.
A kind of method that forms structure of fine sizes according to another aspect of the invention, be characterized in, at least comprise the following steps: to provide a ground, described ground has one by pattern what that one deck constituted on it, wherein, described pattern comprises the distance of whats such as the width adjacent two described line style patterns of several equidistant line style patterns and described line style pattern at least; Form a ground floor and cover described pattern and described ground, wherein, the thickness of described ground floor be about adjacent two described line style patterns distance 1/3rd; The described ground floor of etch-back is to expose described ground; Form a second layer and cover described pattern, described ground floor and described ground, wherein, the thickness of the described second layer be about adjacent two described line style patterns distance 1/3rd; The described second layer of etch-back is to expose described pattern and described ground floor; Remove described pattern; Form one the 3rd layer and cover described ground floor, the described second layer and described ground, wherein, described the 3rd layer thickness be about adjacent two described line style patterns distance 1/3rd; Etch-back described the 3rd layer to expose described ground; Form one the 4th layer and cover described ground floor, the described second layer, described the 3rd layer and described ground, wherein, constitute described the 4th layer material thickness identical and described the 4th layer with the material that constitutes described ground floor be about adjacent two described line style patterns distance 1/3rd; Etch-back described the 4th layer to expose described ground floor, the described second layer and described the 3rd layer; And remove the described second layer and described the 3rd layer.
For further specifying above-mentioned purpose of the present invention, design feature and effect, the present invention is described in detail below with reference to accompanying drawing.
(4) description of drawings
Figure 1A shows the result schematic diagram that forms on a patterned layer what one ground;
Figure 1B shows that conformal generation one deck covers the result schematic diagram on the ground shown in Figure 1A;
Fig. 1 C is the result schematic diagram that shows structure shown in anisotropic etch-back Figure 1B;
Fig. 1 D shows structural result schematic diagram shown in conformal generation one deck what Fig. 1 C;
Fig. 1 E is the result schematic diagram that shows structure shown in anisotropic etch-back Fig. 1 D;
Fig. 1 F shows the result schematic diagram that removes the patterned layer shown in Figure 1A to Fig. 1 E;
Fig. 1 G shows the structural result schematic diagram shown in conformal generation one deck what Fig. 1 F;
Fig. 1 H is the result schematic diagram that shows structure shown in anisotropic etch-back Fig. 1 G;
Fig. 1 I shows structural result schematic diagram shown in conformal generation one deck what Fig. 1 H;
Fig. 1 J is the result schematic diagram that shows structure shown in anisotropic etch-back Fig. 1 I; And
Fig. 1 K shows the result schematic diagram that forms patterned layer of the present invention.
(5) embodiment
In this mandatory declaration is that processing step described below and structure do not comprise complete technology.The present invention can implement by various integrated circuit technologies, only mentions at this and understands technology required for the present invention.
Below will be described in detail in conjunction with the accompanying drawings, please note that diagram is simple form and not according to scaling, and size all be understood the present invention by exaggerative in order to what according to the present invention.
Shown in Figure 1A, show that a pattern that is formed by a ground floor 102 forms on what one ground 100.This pattern comprises that at least several are through forming and equidistant linear pattern.The interval of linear pattern or each other between its width of what such as distance.For the width of the limit linear pattern of breaking through lithography process or distance each other should be rough etc. the resolution limit of the applied lithography process of what modern semiconductors industrial circle or the minimum feature that can reach with other the whole bag of tricks.For instance, the width of linear pattern or distance each other can be 0.18 micron or even finer 0.13 micron.However, still in development constantly, the width of the linear pattern shown in Figure 1A or its distance each other should the above-mentioned technology live width grade of limited what at modern lithography process.Ground 100 can be a dielectric layer, a conductor layer, an integrated circuit and other various grounds, and why ground 100 is to depend on what application of the present invention and decide.
In one embodiment of this invention, ground floor 102 is inclusion one photoresist layer at least, for example deep UV (DUV) photoresist layer with conventional method formation.Linear pattern shown in Figure 1A can be traditional lithography process form.Shown in Figure 1B, a second layer 104 forms on the what ground 100.The second layer 104 can be a dielectric layer, and this dielectric layer can be an oxide layer or a silicon nitride layer with traditional method formation.The thickness of the second layer 104 is 1/3rd preferable with the width that is about the linear pattern shown in Figure 1A.Ground floor 102 also can be a dielectric layer, and this dielectric layer and the second layer 104 must have high etching selectivity.Also even ground floor 102 is an oxide layer, and then the second layer 104 can be one silica layer.
Shown in figure 1C, the second layer 104 by with for example with the conventional dry etch method anisotropic etch-back of dielectric layers such as what etching oxide layer or silicon nitride layer to expose ground 100 and ground floor 102.Shown in Fig. 1 C, clearance wall forms the sidewall of the linear pattern shown in next-door neighbour's what Figure 1A, the thickness of this gap wall be the linear pattern shown in Figure 1A width 1/3rd.Shown in figure 1D, one the 3rd layer 106 forms on the structure shown in what Fig. 1 C.At least comprise a non-photosensitive macromolecule layer for the 3rd layer 106, but do not limit what one non-photosensitive macromolecule layer.This non-photosensitive macromolecule layer can be one and is used as the macromolecule layer that (BARC) layer is reflected in the bottom.In fact only be required to be non-photosensitive for the 3rd layer 106 and have the high etching selectivity of comparing with the second layer 104.The 3rd layer 106 thickness is 1/3rd preferable with the width of the linear pattern shown in Figure 1A.
Shown in figure 1E, the 3rd layer of 106 conventional method anisotropic etch-back that is divested (DryStrip) method with the dry type of for example using the gas plasma is to expose the ground floor 102 and the second layer 104.Shown in figure 1F, if when ground floor 102 is positive photoresist layer, ground floor 102 will remove with traditional exposure method exposure imaging.In the removing of ground floor 102, need not use light shield.Therefore have non-photosensitive for the 3rd layer 10 by what, the 3rd layer of 106 what remove ground floor 102 Hous and still exist.
Shown in figure 1G, the structure shown in one the 4th layer of 108 conformal generation coverage diagram 1F.The 4th layer 108 thickness be the linear pattern shown in Figure 1A width 1/3rd.Also can be a non-photosensitive macromolecule layer for the 4th layer 108 and be used as the macromolecule layer of bottom antireflecting layer, or be a non-photosensitive and have the layer high etching selectivity material of comparing with adjacent contact as one.With reference to shown in the figure 1H the 4th layer 108 by with traditional method anisotropic etch-back to expose ground 100.
Shown in figure 1I, a layer 5 110 forms on the structure shown in the coverage diagram 1H.The material of layer 5 110 is identical with the second layer 104.Then shown in Fig. 1 J, layer 5 110 by with traditional method anisotropic etch-back to expose the second layer 104, the 3rd layer 106 and the 4th layers 108.
Shown in figure 1K, the 3rd layer 106 and the 4th layers 108 are removed and form a pattern of being made up of the layer 5 110 and the second layer 104 in regular turn.The 3rd layer 106 with the 4th layer 108 as when being identical non-photosensitive macromolecular material, the step that removes the 3rd layer 106 and the 4th layers 108 can the oxygen plasma dry type divest (Dry Strip).The pattern of being made up of the layer 5 110 and the second layer 104 has several equidistant line style patterns, the width of this line style pattern be the pattern that constituted by ground floor 102 the line style pattern width 1/3rd.The pattern of being made up of the layer 5 110 and the second layer 104 can be used as etch mask to form various component structures with micro-structure feature, for example gate or hole.Only use a light shield or a big pattern transfering process in the forming process of the pattern of forming by the layer 5 110 and the second layer 104, and light shield or pattern transfering process are the limit of limited what lithography process.
In another embodiment of the present invention, the ground floor 102 shown in Figure 1A can be a dielectric layer or a photoresist layer, for example an oxide layer or a silicon nitride layer with conventional method formation.Pattern shown in Figure 1A can be traditional little shadow and etch process redly become.The pattern of being made up of ground floor 102 among Figure 1A comprises several equidistant linear patterns at least.The interval of linear pattern or its width of what such as distance each other.In order to break through the limit of lithography process, the width of linear pattern or distance each other should be rough etc. the resolution limit of the applied lithography process of what modern semiconductors industrial circle or the minimum feature that can reach with other the whole bag of tricks.For instance, the width of linear pattern or distance each other can be 0,18 micron or even finer 0.13 micron.However, still in development constantly, the width of the linear pattern shown in Figure 1A or its distance each other should the above-mentioned technology live width grade of limited what at modern lithography process.Ground 100 is to depend on what application of the present invention and decide.
The second layer 104 shown in Figure 1B comprises for example a polysilicon layer or a metal level with traditional method formation of a conductor layer at least.The thickness of the second layer 104 is 1/3rd preferable with the width that is about the linear pattern shown in Figure 1A.The second layer 104 has the high etching selectivity of comparing with the layer of adjacent contact.Then shown in Fig. 1 C, the second layer 104 by with conventional dry etch method anisotropic etch-back to expose ground 100 and ground floor 102.Moreover with reference to shown in the figure 1D, the 3rd layer 106 forms on the structure shown in what Fig. 1 C.At least comprise an oxide layer or a silicon nitride layer for the 3rd layer 106, and have the high etching selectivity of comparing with the layer of adjacent contact.The 3rd layer 106 thickness is 1/3rd preferable with the width that is about the linear pattern shown in Figure 1A.The 3rd layer 106 then by with conventional dry etch method anisotropic etch-back shown in Fig. 1 E.Then with reference to shown in the figure 1F, ground floor 102 is removed with traditional method.In addition, shown in Fig. 1 G, the 4th layer 108 with the structure shown in the conformal generation coverage diagram of the traditional method 1F, and the 4th layer 108 can be an oxide layer or a silicon nitride layer, and has the high etching selectivity of comparing with the layer of adjacent contact.The 4th layer 108 thickness be the linear pattern shown in Figure 1A width 1/3rd.Then, shown in Fig. 1 H, the 4th layer 108 by with traditional method anisotropic etch-back to expose the end 100.With reference to shown in figure 1I and Fig. 1 J, layer 5 110 forms and covers and etch-back again.Hou is with reference to shown in the figure 1K, and the 3rd layer 106 and the 4th layers 108 are removed and form one in regular turn by layer 5 110 and the 3rd layer of 104 pattern of forming.In this embodiment, the pattern of being made up of the layer 5 110 and the second layer 104 can be a gate pattern, if layer 5 110 is polysilicon layer with the second layer 104.Can be identical materials for the 3rd layer 106 and the 4th layers 108 and remove the 3rd layer 106 and the 4th layers 108 step and can simplify merging.In this embodiment, the pattern of being made up of the layer 5 110 and the second layer 104 itself is the component structure with micro-structure feature.
In one embodiment of this invention, the present invention utilizes light shield and once pattern transfering process to form a photoresist layer pattern, and the fine sizes of this photoresist layer pattern is the resolution limit of lithography process.Then the present invention utilizes four depositions and aims at etch back process voluntarily forming an etch mask, and the fine sizes of this etch mask only is 1/3rd of the above-mentioned fine sizes that is formed by the resolution limit of lithography process.This etch mask can form various component structures with atomic thin architectural feature with what, and this feature size only is 1/3rd of the fine sizes that forms of the resolution limit by lithography process.
In another embodiment of the present invention, the present invention also utilizes a light shield and a big pattern transfering process to form a pattern, the expired resolution limit that is of a size of lithography process of this pattern.The present invention utilizes four big depositions and aims at etch back process has atomic thin architectural feature with direct formation one component structure voluntarily.The size of the architectural feature of this component structure only is 1/3rd of the above-mentioned fine sizes that is formed by the resolution limit of lithography process.
Certainly, those of ordinary skill in the art will be appreciated that, above embodiment is used for illustrating the present invention, and be not to be used as limitation of the invention, as long as in connotation scope of the present invention, all will drop in the scope of claims of the present invention variation, the modification of the above embodiment.
Claims (9)
1. a method that forms structure of fine sizes is characterized in that, comprises the following steps: at least
One ground is provided, and described ground is provided with a photoresist layer pattern, and described pattern comprises several line style patterns at least;
Form a ground floor and cover described pattern and described ground;
The described ground floor of etch-back is to expose described ground;
Form a second layer and cover described pattern, described ground floor and described ground;
The described second layer of etch-back is to expose described pattern and described ground floor;
Remove described pattern;
Form one the 3rd layer and cover described ground floor, the described second layer and described ground;
Etch-back described the 3rd layer to expose described ground;
Form one the 4th layer and cover described ground floor, the described second layer, described the 3rd layer of described ground in territory, it is identical with the material that constitutes described ground floor wherein to constitute described the 4th layer material;
Etch-back described the 4th layer to expose described ground floor, the described second layer and described the 3rd layer; And
Remove the described second layer and described the 3rd layer.
2. the method for claim 1 is characterized in that, the described second layer and described the 3rd layer comprise a non-photosensitive macromolecule layer at least.
3. the method for claim 1 is characterized in that, described ground floor, the described second layer, described the 3rd layer with described the 4th layer thickness be about adjacent two described line style patterns distance 1/3rd.
4. a method that forms structure of fine sizes is characterized in that, comprises the following steps: at least
One ground is provided, and described ground has a dielectric layer pattern what on it, and wherein, described pattern comprises the distance of whats such as the width adjacent two described line style patterns of several equidistant line style patterns and described line style pattern at least;
Form a ground floor and cover described pattern and described ground;
The described ground floor of etch-back is to expose described ground;
Form a second layer and cover described pattern, described ground floor and described ground;
The described second layer of etch-back is to expose described pattern and described ground floor;
Remove described pattern;
Form one the 3rd layer and cover described ground floor, the described second layer and described ground;
Etch-back described the 3rd layer to expose described ground;
Form one the 4th layer and cover described ground floor, the described second layer, described the 3rd layer and described ground, wherein, it is identical with the material that constitutes described ground floor to constitute described the 4th layer material;
Etch-back described the 4th layer to expose described ground floor, the described second layer and described the 3rd layer; And
Remove the described second layer and described the 3rd layer.
5. method as claimed in claim 4 is characterized in that described dielectric layer comprises an oxide layer at least.
6. method as claimed in claim 4 is characterized in that, described ground floor and described the 4th layer comprise the polycrystalline layer of sand at least.
7. a method that forms structure of fine sizes is characterized in that, comprises the following steps: at least
One ground is provided, and described ground has one by pattern what that one deck constituted on it, and wherein, described pattern comprises the distance of whats such as the width adjacent two described line style patterns of several equidistant line style patterns and described line style pattern at least;
Form a ground floor and cover described pattern and described ground, wherein, the thickness of described ground floor be about adjacent two described line style patterns distance 1/3rd;
The described ground floor of etch-back is to expose described ground;
Form a second layer and cover described pattern, described ground floor and described ground, wherein, the thickness of the described second layer be about adjacent two described line style patterns distance 1/3rd;
The described second layer of etch-back is to expose described pattern and described ground floor;
Remove described pattern;
Form one the 3rd layer and cover described ground floor, the described second layer and described ground, wherein, described the 3rd layer thickness be about adjacent two described line style patterns distance 1/3rd;
Etch-back described the 3rd layer to expose described ground;
Form one the 4th layer and cover described ground floor, the described second layer, described the 3rd layer and described ground, wherein, constitute described the 4th layer material thickness identical and described the 4th layer with the material that constitutes described ground floor be about adjacent two described line style patterns distance 1/3rd;
Etch-back described the 4th layer to expose described ground floor, the described second layer and described the 3rd layer; And
Remove the described second layer and described the 3rd layer.
8. method as claimed in claim 7 is characterized in that, described layer is an oxide layer, and described ground floor and described the 4th layer are polysilicon layer, and the described second layer and described the 3rd layer are silicon nitride layer.
9. method as claimed in claim 7 is characterized in that, described layer is an oxide layer, and described ground floor is that the polysilicon layer and the described second layer are a silicon nitride layer with described the 4th layer, and described the 3rd layer is an oxide layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02101821 CN1206702C (en) | 2002-01-10 | 2002-01-10 | Method for forming structure of fine sizes |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02101821 CN1206702C (en) | 2002-01-10 | 2002-01-10 | Method for forming structure of fine sizes |
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| CN1431680A true CN1431680A (en) | 2003-07-23 |
| CN1206702C CN1206702C (en) | 2005-06-15 |
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| CN 02101821 Expired - Fee Related CN1206702C (en) | 2002-01-10 | 2002-01-10 | Method for forming structure of fine sizes |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187524A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of phase change resistor in phase change memory |
| CN103311092A (en) * | 2012-03-12 | 2013-09-18 | 中芯国际集成电路制造(上海)有限公司 | Method for etching grooves |
| CN103390544A (en) * | 2012-05-11 | 2013-11-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming hard mask layer |
| CN103794475A (en) * | 2012-10-30 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Self aligned triple patterning method |
| CN104516104A (en) * | 2013-09-30 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Formation method of digital micro display |
-
2002
- 2002-01-10 CN CN 02101821 patent/CN1206702C/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187524A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of phase change resistor in phase change memory |
| CN103187524B (en) * | 2011-12-31 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | The formation method of phase change resistor in phase transition storage |
| CN103311092A (en) * | 2012-03-12 | 2013-09-18 | 中芯国际集成电路制造(上海)有限公司 | Method for etching grooves |
| CN103311092B (en) * | 2012-03-12 | 2015-08-05 | 中芯国际集成电路制造(上海)有限公司 | The lithographic method of groove |
| CN103390544A (en) * | 2012-05-11 | 2013-11-13 | 中芯国际集成电路制造(上海)有限公司 | Method for forming hard mask layer |
| CN103390544B (en) * | 2012-05-11 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | For the formation of the method for hard mask layer |
| CN103794475A (en) * | 2012-10-30 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Self aligned triple patterning method |
| CN103794475B (en) * | 2012-10-30 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | The triple graphic method of autoregistration |
| CN104516104A (en) * | 2013-09-30 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Formation method of digital micro display |
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|---|---|
| CN1206702C (en) | 2005-06-15 |
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