CN104701367A - Current stabilizer tube and manufacturing method thereof - Google Patents
Current stabilizer tube and manufacturing method thereof Download PDFInfo
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- CN104701367A CN104701367A CN201310655018.0A CN201310655018A CN104701367A CN 104701367 A CN104701367 A CN 104701367A CN 201310655018 A CN201310655018 A CN 201310655018A CN 104701367 A CN104701367 A CN 104701367A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000003381 stabilizer Substances 0.000 title abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 38
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 38
- 239000010703 silicon Substances 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims description 34
- 238000005516 engineering process Methods 0.000 claims description 15
- 238000005468 ion implantation Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 8
- 230000001105 regulatory effect Effects 0.000 claims description 7
- 238000000605 extraction Methods 0.000 claims description 6
- 238000005070 sampling Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a current stabilizer tube comprising a P-type epitaxial layer, two first N-type areas, a longitudinal conduction trench and a third N-type area. The P-type epitaxial layer is formed on the front surface of a P+ silicon substrate. The first N-type areas are formed in the P-type epitaxial layer. The part, between the first N-type areas forms the longitudinal conduction trench. The third N-type area is formed in the P-type epitaxial layer in the bottom area of the longitudinal conduction trench. When a device operates, the third N-type area helps increase the ability to consume the P-type epitaxial layer in the bottom area of the longitudinal conduction trench, pinch-of voltage of the device can be reduced thereby; increase in the width of the longitudinal conduction trench leads to increase in conduction current; by adjusting the pinch-off voltage of the device through the third N-type area, the pinch-off voltage can be kept unchanged or lower while conduction current is increased, and reliability of the device is improved thereby. The invention further discloses a manufacturing method of the current stabilizer tube.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of barretter.The invention still further relates to a kind of manufacture method of barretter.
Background technology
Barretter as discrete device, due to circuit stability and protective circuit can be improved and be widely adopted.As shown in Figure 1, be the structure chart of existing barretter; Existing barretter comprises:
The heavily doped silicon substrate 101 of P type.The thickness being formed with P type epitaxial loayer 102, P type epitaxial loayer 102 in the front face surface of silicon substrate 101 is larger, and the longitudinal direction of barretter is withstand voltage larger.
Two N-type region 103 being formed at P type epitaxial loayer 102 surface, described P type epitaxial loayer 102 between two N-type region 103 forms longitudinal conductive channel of described barretter, spacing between two described first N-type region 103 is larger, longitudinal conductive channel of described barretter is wider, and the On current of barretter is larger.
In two N-type region 103, be formed with a N+ district 104 respectively, each N+ district 104 draws for the electrode realizing corresponding N-type region 103.
P+ district 105, is formed in the subregion on described P type epitaxial loayer 102 surface between two N-type region 103.Be made up of the source region of longitudinal conductive channel P+ district 105, be made up of the drain region of described longitudinal conductive channel silicon substrate 101.
The top in Ge N+ district 104, P+ district 105 is formed with metal contact hole 106 respectively and all passes through corresponding metal contact hole 106 and is connected to the source electrode be made up of front metal layer 107; The back side of silicon substrate 101 is formed with the drain electrode be made up of metal layer on back.
During barretter work, source ground, drain electrode connects the bias voltage being more than or equal to pinch-off voltage, and two N-type region 103 exhaust the P type epitaxial loayer 102 of longitudinal conductive channel bottom section simultaneously completely, and such voltage-stabiliser tube can provide a stable On current.
As shown in Figure 1, be withstand voltage by regulating the thickness of P type epitaxial loayer 102 to realize higher longitudinal direction in prior art; And to realize larger On current, then usually need the width increasing longitudinal conductive channel, also the spacing between increase by two N-type region 103 is namely needed, when spacing between N-type region 103 increases, voltage-stabiliser tube operationally drains needs the bias voltage of Jia Genggao that the P type epitaxial loayer 102 of longitudinal conductive channel bottom section is exhausted completely, also namely pinch-off voltage can increase, and the increase of pinch-off voltage can make reliability decrease, and the possibility that circuit is burned increases.Also namely there is a contradiction in existing structure between On current and pinch-off voltage, and when needs increase On current, pinch-off voltage also will certainly increase, and cannot realize large On current and little pinch-off voltage simultaneously.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of barretter, can increase the On current of device, realize High-current output under or the condition that reduces constant at pinch-off voltage.For this reason, the present invention also provides a kind of manufacture method of barretter.
For solving the problems of the technologies described above, barretter provided by the invention comprises:
The heavily doped silicon substrate of P type.
P type epitaxial loayer, is formed at the front face surface of described silicon substrate, and the thickness of described P type epitaxial loayer is larger, and the longitudinal direction of barretter is withstand voltage larger.
Two the first N-type region being formed at described P type epi-layer surface, two described first N-type region are separated by a distance, longitudinal conductive channel of described barretter is made up of the described P type epitaxial loayer between two described first N-type region, spacing between two described first N-type region is larger, longitudinal conductive channel of described barretter is wider, and the On current of described barretter is larger; The bottom of two described first N-type region is separated by a distance with described silicon substrate all respectively.
One P+ district, is formed in the subregion of the described P type epi-layer surface between two described first N-type region; Be made up of the source region of described longitudinal conductive channel a described P+ district, be made up of the drain region of described longitudinal conductive channel described silicon substrate.
A the 2nd N+ district is formed respectively in two described first N-type region, each described 2nd N+ district is for realizing the extraction of corresponding described first N-type region, and the top in each described 2nd N+ district, a described P+ district is formed with metal contact hole respectively and is all connected to by corresponding described metal contact hole the source electrode be made up of front metal layer; The back side of described silicon substrate is formed with the drain electrode be made up of metal layer on back.
3rd N-type region, is formed at the bottom section of the described P type epitaxial loayer between two described first N-type region, and described 3rd N-type region and described silicon substrate are separated by a segment distance, and described 3rd N-type region and two described first N-type region are also separated by a segment distance respectively.
During described barretter work, described source ground, described drain electrode connects the bias voltage being more than or equal to pinch-off voltage, two described first N-type region and described 3rd N-type region exhaust the described P type epitaxial loayer of described longitudinal conductive channel bottom section simultaneously completely, described pinch-off voltage is regulated by described 3rd N-type region, the region of described 3rd N-type region is larger, and described pinch-off voltage is less.
For solving the problems of the technologies described above, the manufacture method of barretter provided by the invention comprises the steps:
Step one, form P type epitaxial loayer in the front face surface of the heavily doped silicon substrate of P type, the thickness of described P type epitaxial loayer is larger, and the longitudinal direction of barretter is withstand voltage larger.
Step 2, employing front N-type ion implantation technology form two the first N-type region in described P type epi-layer surface, two described first N-type region are separated by a distance, longitudinal conductive channel of described barretter is made up of the described P type epitaxial loayer between two described first N-type region, spacing between two described first N-type region is larger, longitudinal conductive channel of described barretter is wider, and the On current of described barretter is larger; The bottom of two described first N-type region is separated by a distance with described silicon substrate all respectively.
The bottom section of step 3, the described P type epitaxial loayer of employing front N-type ion implantation technology between two described first N-type region forms the 3rd N-type region, described 3rd N-type region and described silicon substrate are separated by a segment distance, and described 3rd N-type region and two described first N-type region are also separated by a segment distance respectively.
Step 4, sampling front N+ ion implantation technology form a 2nd N+ district respectively in two described first N-type region, and each described 2nd N+ district is for realizing the extraction of corresponding described first N-type region.
A P+ district is formed in the subregion of step 5, the described P type epi-layer surface of sampling front P+ ion implantation technology between two described first N-type region; Be made up of the source region of described longitudinal conductive channel a described P+ district, be made up of the drain region of described longitudinal conductive channel described silicon substrate.
Step 6, form metal contact hole respectively at the top in each described 2nd N+ district and a described P+ district, form front metal layer and carry out chemical wet etching to described front metal layer and form source electrode figure, each described 2nd N+ district and a described P+ district are all connected to source electrode by corresponding described metal contact hole.
Step 7, form metal layer on back the drain electrode be made up of described metal layer on back at the back side of described silicon substrate, during described barretter work, described source ground, described drain electrode connects the bias voltage being more than or equal to pinch-off voltage, two described first N-type region and described 3rd N-type region exhaust the described P type epitaxial loayer of described longitudinal conductive channel bottom section simultaneously completely, described pinch-off voltage is regulated by described 3rd N-type region, the region of described 3rd N-type region is larger, and described pinch-off voltage is less.
The present invention by arranging the 3rd N-type region in the P type epitaxial loayer of longitudinal conductive channel bottom section, can increase when barretter works and ability is exhausted to the P type epitaxial loayer of longitudinal conductive channel bottom section, thus the pinch-off voltage of device can be reduced, the present invention can also increase On current by the width increasing longitudinal conductive channel, by the 3rd N-type region to the adjustment of the pinch-off voltage of device, the present invention can under the increase condition of On current, pinch-off voltage remained unchanged or reduces, thus improving the reliability of device.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the structure chart of existing barretter;
Fig. 2 is the structure chart of embodiment of the present invention barretter;
Fig. 3 is the pinch-off voltage comparison curves of embodiment of the present invention barretter and existing barretter;
Fig. 4 A-Fig. 4 E is the device architecture figure in each step of embodiment of the present invention method.
Embodiment
As shown in Figure 2, be the structure chart of embodiment of the present invention barretter; Embodiment of the present invention barretter comprises:
The heavily doped silicon substrate 1 of P type.
P type epitaxial loayer 2, is formed at the front face surface of described silicon substrate 1, and the thickness of described P type epitaxial loayer 2 is larger, and the longitudinal direction of barretter is withstand voltage larger.
Two the first N-type region 3 being formed at described P type epitaxial loayer 2 surface, two described first N-type region 3 are separated by a distance, longitudinal conductive channel of described barretter is made up of the described P type epitaxial loayer 2 between two described first N-type region 3, spacing between two described first N-type region 3 is larger, longitudinal conductive channel of described barretter is wider, and the On current of described barretter is larger; The bottom of two described first N-type region 3 is separated by a distance with described silicon substrate 1 all respectively.
One P+ district 6, is formed in the subregion on described P type epitaxial loayer 2 surface between two described first N-type region 3; Be made up of the source region of described longitudinal conductive channel a described P+ district 6, be made up of the drain region of described longitudinal conductive channel described silicon substrate 1.
A the 2nd N+ district 5 is formed respectively in two described first N-type region 3, each described 2nd N+ district 5 is for realizing the extraction of corresponding described first N-type region 3, and the top in each described 2nd N+ district 5, a described P+ district 6 is formed with metal contact hole 7 respectively and all passes through corresponding described metal contact hole 7 and is connected to the source electrode be made up of front metal layer 8; The back side of described silicon substrate 1 is formed with the drain electrode be made up of metal layer on back.
3rd N-type region 4, be formed at the bottom section of the described P type epitaxial loayer 2 between two described first N-type region 3, described 3rd N-type region 4 and described silicon substrate 1 are separated by a segment distance, and described 3rd N-type region 4 and two described first N-type region 3 are also separated by a segment distance respectively.
During described barretter work, described source ground, described drain electrode connects the bias voltage being more than or equal to pinch-off voltage, two described first N-type region 3 and described 3rd N-type region 4 exhaust the described P type epitaxial loayer 2 of described longitudinal conductive channel bottom section simultaneously completely, described pinch-off voltage is regulated by described 3rd N-type region 4, the region of described 3rd N-type region 4 is larger, and described pinch-off voltage is less.
As shown in Figure 3, be the pinch-off voltage comparison curves of embodiment of the present invention barretter and existing barretter, suppose in Fig. 3 that the width of longitudinal conductive channel of embodiment of the present invention barretter is identical with the width of existing barretter, abscissa is bias voltage Vp, ordinate is leakage current Id, the pinch-off voltage of embodiment of the present invention device is V1, existing device pinch-off voltage be V2, V1 is less than V2, the pinch-off voltage of visible embodiment of the present invention device diminishes, when being greater than pinch-off voltage, barretter is operated in stable On current state, as shown in Figure 3, embodiment of the present invention device is identical with the On current of existing device, so embodiment of the present invention device can keep the pinch-off voltage reducing device under the constant condition of On current, equally, embodiment of the present invention device, by the change to the width of longitudinal conductive channel, can realize while On current increases, and makes pinch-off voltage reduce or remain unchanged.
As shown in Fig. 4 A to Fig. 4 E, be the device architecture figure in each step of embodiment of the present invention method.The manufacture method of embodiment of the present invention barretter comprises the steps:
Step one, as shown in Figure 4 A, form P type epitaxial loayer 2 in the front face surface of the heavily doped silicon substrate 1 of P type, the thickness of described P type epitaxial loayer 2 is larger, and the longitudinal direction of barretter is withstand voltage larger.
Step 2, as shown in Figure 4 B, front N-type ion implantation technology is adopted to form two the first N-type region 3 on described P type epitaxial loayer 2 surface, two described first N-type region 3 are separated by a distance, longitudinal conductive channel of described barretter is made up of the described P type epitaxial loayer 2 between two described first N-type region 3, spacing between two described first N-type region 3 is larger, longitudinal conductive channel of described barretter is wider, and the On current of described barretter is larger; The bottom of two described first N-type region 3 is separated by a distance with described silicon substrate 1 all respectively.
Step 3, as shown in Figure 4 C, the bottom section of the described P type epitaxial loayer 2 of front N-type ion implantation technology between two described first N-type region 3 is adopted to form the 3rd N-type region 4, described 3rd N-type region 4 and described silicon substrate 1 are separated by a segment distance, and described 3rd N-type region 4 and two described first N-type region 3 are also separated by a segment distance respectively.
Step 4, as shown in Figure 4 D, sampling front N+ ion implantation technology forms a 2nd N+ district 5 respectively in two described first N-type region 3, and each described 2nd N+ district 5 is for realizing the extraction of corresponding described first N-type region 3.
Step 5, as shown in Figure 4 E, forms a P+ district 6 in the subregion on sampling described P type epitaxial loayer 2 surface of P+ ion implantation technology between two described first N-type region 3, front; Be made up of the source region of described longitudinal conductive channel a described P+ district 6, be made up of the drain region of described longitudinal conductive channel described silicon substrate 1.
Step 6, as shown in Figure 2, metal contact hole 7 is formed respectively at the top in each described 2nd N+ district 5 and a described P+ district 6, form front metal layer 8 and carry out chemical wet etching to described front metal layer 8 and form source electrode figure, each described 2nd N+ district 5 and a described P+ district 6 all pass through corresponding described metal contact hole 7 and are connected to source electrode.
Step 7, as shown in Figure 2, metal layer on back is formed and the drain electrode be made up of described metal layer on back at the back side of described silicon substrate 1, during described barretter work, described source ground, described drain electrode connects the bias voltage being more than or equal to pinch-off voltage, two described first N-type region 3 and described 3rd N-type region 4 exhaust the described P type epitaxial loayer 2 of described longitudinal conductive channel bottom section simultaneously completely, described pinch-off voltage is regulated by described 3rd N-type region 4, the region of described 3rd N-type region 4 is larger, and described pinch-off voltage is less.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (2)
1. a barretter, is characterized in that, comprising:
The heavily doped silicon substrate of P type;
P type epitaxial loayer, is formed at the front face surface of described silicon substrate, and the thickness of described P type epitaxial loayer is larger, and the longitudinal direction of barretter is withstand voltage larger;
Two the first N-type region being formed at described P type epi-layer surface, two described first N-type region are separated by a distance, longitudinal conductive channel of described barretter is made up of the described P type epitaxial loayer between two described first N-type region, spacing between two described first N-type region is larger, longitudinal conductive channel of described barretter is wider, and the On current of described barretter is larger; The bottom of two described first N-type region is separated by a distance with described silicon substrate all respectively;
One P+ district, is formed in the subregion of the described P type epi-layer surface between two described first N-type region; Be made up of the source region of described longitudinal conductive channel a described P+ district, be made up of the drain region of described longitudinal conductive channel described silicon substrate;
A the 2nd N+ district is formed respectively in two described first N-type region, each described 2nd N+ district is for realizing the extraction of corresponding described first N-type region, and the top in each described 2nd N+ district, a described P+ district is formed with metal contact hole respectively and is all connected to by corresponding described metal contact hole the source electrode be made up of front metal layer; The back side of described silicon substrate is formed with the drain electrode be made up of metal layer on back;
3rd N-type region, is formed at the bottom section of the described P type epitaxial loayer between two described first N-type region, and described 3rd N-type region and described silicon substrate are separated by a segment distance, and described 3rd N-type region and two described first N-type region are also separated by a segment distance respectively;
During described barretter work, described source ground, described drain electrode connects the bias voltage being more than or equal to pinch-off voltage, two described first N-type region and described 3rd N-type region exhaust the described P type epitaxial loayer of described longitudinal conductive channel bottom section simultaneously completely, described pinch-off voltage is regulated by described 3rd N-type region, the region of described 3rd N-type region is larger, and described pinch-off voltage is less.
2. a manufacture method for barretter, is characterized in that, comprises the steps:
Step one, form P type epitaxial loayer in the front face surface of the heavily doped silicon substrate of P type, the thickness of described P type epitaxial loayer is larger, and the longitudinal direction of barretter is withstand voltage larger;
Step 2, employing front N-type ion implantation technology form two the first N-type region in described P type epi-layer surface, two described first N-type region are separated by a distance, longitudinal conductive channel of described barretter is made up of the described P type epitaxial loayer between two described first N-type region, spacing between two described first N-type region is larger, longitudinal conductive channel of described barretter is wider, and the On current of described barretter is larger; The bottom of two described first N-type region is separated by a distance with described silicon substrate all respectively;
The bottom section of step 3, the described P type epitaxial loayer of employing front N-type ion implantation technology between two described first N-type region forms the 3rd N-type region, described 3rd N-type region and described silicon substrate are separated by a segment distance, and described 3rd N-type region and two described first N-type region are also separated by a segment distance respectively;
Step 4, sampling front N+ ion implantation technology form a 2nd N+ district respectively in two described first N-type region, and each described 2nd N+ district is for realizing the extraction of corresponding described first N-type region;
A P+ district is formed in the subregion of step 5, the described P type epi-layer surface of sampling front P+ ion implantation technology between two described first N-type region; Be made up of the source region of described longitudinal conductive channel a described P+ district, be made up of the drain region of described longitudinal conductive channel described silicon substrate;
Step 6, form metal contact hole respectively at the top in each described 2nd N+ district and a described P+ district, form front metal layer and carry out chemical wet etching to described front metal layer and form source electrode figure, each described 2nd N+ district and a described P+ district are all connected to source electrode by corresponding described metal contact hole;
Step 7, form metal layer on back the drain electrode be made up of described metal layer on back at the back side of described silicon substrate, during described barretter work, described source ground, described drain electrode connects the bias voltage being more than or equal to pinch-off voltage, two described first N-type region and described 3rd N-type region exhaust the described P type epitaxial loayer of described longitudinal conductive channel bottom section simultaneously completely, described pinch-off voltage is regulated by described 3rd N-type region, the region of described 3rd N-type region is larger, and described pinch-off voltage is less.
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| CN201310655018.0A CN104701367A (en) | 2013-12-06 | 2013-12-06 | Current stabilizer tube and manufacturing method thereof |
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| CN201310655018.0A CN104701367A (en) | 2013-12-06 | 2013-12-06 | Current stabilizer tube and manufacturing method thereof |
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| CN102916049A (en) * | 2012-10-30 | 2013-02-06 | 成都芯源系统有限公司 | Semiconductor device including junction field effect transistor and method of manufacturing the same |
| JP2013120784A (en) * | 2011-12-06 | 2013-06-17 | Toyota Motor Corp | Semiconductor device |
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2013
- 2013-12-06 CN CN201310655018.0A patent/CN104701367A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101366124A (en) * | 2005-12-27 | 2009-02-11 | 美商科斯德半导体股份有限公司 | Ultrafast recovery diode |
| CN102437187A (en) * | 2010-09-29 | 2012-05-02 | 万国半导体股份有限公司 | Semiconductor device die with integrated MOSFET and low forward voltage diode-connected enhancement mode JFET and method |
| JP2013120784A (en) * | 2011-12-06 | 2013-06-17 | Toyota Motor Corp | Semiconductor device |
| CN102916049A (en) * | 2012-10-30 | 2013-02-06 | 成都芯源系统有限公司 | Semiconductor device including junction field effect transistor and method of manufacturing the same |
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