CN104679083A - Integrated circuit and electronic device - Google Patents
Integrated circuit and electronic device Download PDFInfo
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- CN104679083A CN104679083A CN201310614172.3A CN201310614172A CN104679083A CN 104679083 A CN104679083 A CN 104679083A CN 201310614172 A CN201310614172 A CN 201310614172A CN 104679083 A CN104679083 A CN 104679083A
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Abstract
The invention provides an integrated circuit and an electronic device. The integrated circuit comprises at least one load circuit and an LDO (Low Dropout Regulator); the LDO is respectively connected with the high-voltage input end and low-voltage input end of the load circuit. According to the integrated circuit, the LDO is connected with the high-voltage input end and the low-voltage input end of the load circuit, and thus the voltage for normal work of the load circuit can be gained as requirement; the use convenience of the integrated circuit can be improved, and moreover, the area of the integrated circuit can be reduced, and the energy conversion efficiency of the whole system of the integrated circuit can be increased.
Description
Technical field
The present invention relates to electronic circuit technology field, be specifically related to a kind of integrated circuit and electronic equipment.
Background technology
Load circuit has application widely in the field of electronic circuit.The kind of load circuit has a lot, such as can comprise and door or the digital circuit such as door, rejection gate, can also comprise other circuit.In a particular application, load circuit can be connected with other components and parts, forms the integrated circuit with certain function.
Each load circuit can have one or more input end.Signal added by each input end of each load circuit is when meeting some requirements, and described load circuit has corresponding output.
In addition, the load circuit of normal work also must have low-tension supply input end and high-voltage power supply input end, required voltage during for providing normal work to load circuit.
But existing for providing the power supply of voltage to described load circuit, or be external power, the power supply beyond the integrated circuit being namely placed in described load circuit place, is not easy to the use of integrated circuit; Be built-in power, be namely placed in the power supply of the IC interior at described load circuit place, described power supply architecture is complicated, add the area of integrated circuit, and the energy conversion efficiency of integrated circuit whole system is lower.
Summary of the invention
The problem that the embodiment of the present invention solves how to provide required power supply to load circuit easily, so that the area of the use of described integrated circuit and reduction integrated circuit.
For solving the problem, the embodiment of the present invention provides integrated circuit, and described integrated circuit comprises: at least one load circuit, and low pressure difference linear voltage regulator LDO, and described LDO is connected with the high voltage input terminal of described load circuit and low pressure input end respectively.
Alternatively, described LDO comprises: comparer, Correctional tube, first resistance and the second resistance, the output terminal of described comparer is connected with the control pole of described Correctional tube, first pole of described Correctional tube is connected with the first end of described first resistance and the low pressure input end of described load circuit, second pole of described Correctional tube is connected with the high voltage input terminal of power supply and described load circuit, second end of described first resistance is connected with the first end of described second resistance and the first input end of described comparer, second input end input reference voltage of described comparer, second end ground connection of described second resistance.
Alternatively, described Correctional tube is PMOS or PNP type triode.
Alternatively, described integrated circuit also comprises: the first level shift circuit and the second level shift circuit, described first level shift circuit is connected with the input end of described load circuit, current potential for the signal by load circuit described in pre-entered converts the current potential being suitable for inputting described load circuit to, described second level shift circuit is connected with the output terminal of described load circuit, and the current potential for the output signal by described load circuit converts the current potential of the signal of load circuit described in described pre-entered to.
Alternatively, described first level shift circuit comprises: the first change-over circuit and the second change-over circuit be connected with the output terminal of described first change-over circuit, the noble potential of described first change-over circuit to the signal of pre-entered load circuit is changed, the signal exported through described first change-over circuit inputs to described second change-over circuit, the electronegative potential of described second change-over circuit to the signal that described first change-over circuit exports is changed, and the signal that described second change-over circuit exports inputs to described load circuit.
Alternatively, described first change-over circuit is identical with described second converting circuit structure, includes: for receiving the first NMOS tube of input signal, the second NMOS tube, the first PMOS, the second PMOS and for receiving input signal phase inverter; The grid of described first NMOS tube is connected with the input end of described phase inverter, and source electrode is connected with the source electrode of described second NMOS tube, and drain electrode is connected with the drain electrode of described first PMOS and the grid of described second PMOS respectively; The grid of described second NMOS tube is connected with the output terminal of described phase inverter, and drain electrode is connected with the grid of described first PMOS and the drain electrode of the second PMOS; The source electrode of described first PMOS is connected with the source electrode of described second NMOS tube.
Alternatively, described second level shift circuit comprises: the 3rd change-over circuit and the 4th change-over circuit be connected with the output terminal of described 3rd change-over circuit, the noble potential of described 3rd change-over circuit to the signal of pre-entered load circuit is changed, the signal exported through described 3rd change-over circuit inputs to described 4th change-over circuit, the electronegative potential of described 4th change-over circuit to the signal that described 3rd change-over circuit exports is changed, and the signal that described 4th change-over circuit exports inputs to described load circuit.
Alternatively, described 3rd change-over circuit is identical with described 4th converting circuit structure, includes: for receiving the 3rd NMOS tube of input signal, the 4th NMOS tube, the 3rd PMOS, the 4th PMOS and for receiving input signal phase inverter; The grid of described 3rd NMOS tube is connected with the input end of described phase inverter, and source electrode is connected with the source electrode of described 4th NMOS tube, and drain electrode is connected with the drain electrode of described 3rd PMOS and the grid of described 4th PMOS respectively; The grid of described 4th NMOS tube is connected with the output terminal of described phase inverter, and drain electrode is connected with the grid of described 3rd PMOS and the drain electrode of the 4th PMOS; The source electrode of described 3rd PMOS is connected with the source electrode of described 4th NMOS tube.
Alternatively, embodiments of the invention additionally provide a kind of electronic equipment, and described electronic equipment comprises above-mentioned integrated circuit.
Compared with prior art, the technical scheme of the embodiment of the present invention has the following advantages:
By the high voltage input terminal of LDO and load circuit and low pressure input end are connected, namely described load circuit can be made to obtain voltage required when normally working, and need not again for described load circuit provides independent power supply, not only more be convenient to the use of integrated circuit, and the area of integrated circuit can be reduced, improve the energy conversion efficiency of integrated circuit whole system.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of integrated circuit in the embodiment of the present invention;
Fig. 2 is the structural representation of another kind of integrated circuit in the embodiment of the present invention;
Fig. 3 is the structural representation of the first current potential translation in the embodiment of the present invention.
Embodiment
When existing load circuit is applied in integrated circuits, usual needs provide independent power supply for described load circuit, the power supply provided or external power, cause the inconvenience in integrated circuit use procedure, or built-in power, cause the area of integrated circuit to increase, and the energy conversion efficiency of integrated circuit whole system is lower.
For the problems referred to above, The embodiment provides a kind of integrated circuit, described integrated circuit comprises at least one load circuit and low pressure difference linear voltage regulator (Low Dropout Regulator, LDO), by LDO is connected with the high voltage input terminal of load circuit and low pressure input end respectively, the power supply that load circuit provides required when normally working can be thought, and power supply need not be provided for described load circuit separately again, not only make the use of described integrated circuit convenient, and efficiently reduce the area of chip.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
See Fig. 1, The embodiment provides a kind of integrated circuit, described integrated circuit comprises: the load electricity 120 of at least one, and the LDO110 that the high voltage input terminal of described load circuit 120 is connected with low pressure input end.
Wherein, described load circuit 120 can be digital circuit, also can be other circuit.Described LDO110 is low pressure difference linear voltage regulator, and the output terminal of described LDO110 can produce stabilizing low voltage, is usually connected with the power input of other components and parts of integrated circuit.In the present embodiment, the output terminal of described LDO110 is not subject to the impact of load circuit 120, therefore, the high voltage input terminal of described LDO110 and load circuit 120 and low pressure input end are connected, be not only described load circuit 120 and provide required power supply, and effectively improve the utilization factor of LDO110 circuit, and the energy conversion efficiency of integrated circuit whole system.
It should be noted that, described integrated circuit can comprise several load circuits 120, and when described integrated circuit also comprises LDO110 simultaneously, each load circuit 120 all can provide required power supply by described LDO110.
As shown in Figure 1, in embodiments of the invention, described integrated circuit, except the LDO110 that can comprise load circuit 120 and be connected with described load circuit 120, can also comprise the first level shift circuit 130 and the second level shift circuit 140.Wherein, described first level shift circuit 130 can be connected with the input end of described load circuit 120, and the current potential for the signal by load circuit described in pre-entered 120 converts the current potential being suitable for inputting described load circuit 120 to.Described second level shift circuit 140 is connected with the output terminal of described load circuit 120, and the current potential for the output signal by described load circuit 120 converts the current potential of the signal of load circuit 120 described in described pre-entered to.
Wherein, described load circuit 120 can have one or more input end, and accordingly, described in pre-entered, the signal of load circuit 120 can have one, also can have multiple.When described in one of them pre-entered, the current potential of the signal of load circuit 120 is unsuitable for inputting described load circuit 120, can the signal of described pre-entered load circuit 120 first be inputed in the first level shift circuit 130, convert the signal of described pre-entered load circuit 120 to be suitable for inputting described load circuit 120 signal and input to described load circuit 120.In order to the current potential of the signal making signal and the pre-entered load circuit 120 exported in load circuit 120 is consistent, so that subsequent treatment, the output signal of load circuit 120 can be inputed to the second level shift circuit 140 again, the current potential of the output signal of described load circuit 120 be returned to the current potential of the signal of described pre-entered load circuit 120.
It should be noted that, when the signal of wherein multiple pre-entered load circuit 120 is all unsuitable for inputting described load circuit 120, respectively the signal of described pre-entered load circuit 120 can be carried out above-mentioned current potential conversion, make the signal of each pre-entered load circuit 120 all be suitable for inputting in described load circuit 120.
Below the particular circuit configurations of described first level shift circuit 130 and the second level shift circuit 140 is described in detail:
Described first level shift circuit 130 can comprise the first change-over circuit and the second change-over circuit.Wherein, the output terminal of described first change-over circuit is connected with described second change-over circuit.Described first change-over circuit is first changed the noble potential of the signal of pre-entered load circuit 120, the signal exported through described first change-over circuit inputs to described second change-over circuit, changed by the electronegative potential of described second change-over circuit to the signal that described first change-over circuit exports, the signal that described second change-over circuit exports inputs to described load circuit 120 again.
In concrete enforcement, described first change-over circuit can be identical with the circuit structure of the second change-over circuit, also can be different.Such as, see Fig. 2, described first change-over circuit 210 is identical with the circuit structure of the second change-over circuit 220.
For described first change-over circuit 210, described first change-over circuit 210 can comprise: the first NMOS tube 2102, second NMOS tube 2104, first PMOS 2106, second PMOS 2108 and phase inverter 2110.Wherein, the grid of the first NMOS tube 2102 is connected with the input end of described phase inverter 2110, input signal V
ininput to described first NMOS tube 2102 and phase inverter 2110 simultaneously.The source electrode of the first NMOS tube is connected through the source electrode of phase inverter 2110 with described second NMOS tube, and drain electrode is connected with the drain electrode of described first PMOS and the grid of described second PMOS 2104 respectively.The grid of described second NMOS tube 2104 is connected with the output terminal of described phase inverter 2110, and drain electrode is connected with the grid of described first PMOS 2106 and the drain electrode of the second PMOS 2108.The source electrode of described first PMOS 2106 is connected with the source electrode of described second NMOS tube 2104.
When described first change-over circuit 210 normally works, the signal inputing to the first NMOS tube 2102 is V
in, the signal inputing to the second NMOS tube 2104 is input signal V
inoutput signal after phase inverter.That is, the signal inputing to the first NMOS tube 2102 is contrary with the signal inputing to the second NMOS tube 2104, and when the signal inputing to the first NMOS tube 2102 is high level, the signal inputing to the second NMOS tube 2104 is then low level.Therefore, synchronization, in the first NMOS tube 2102 and the second NMOS tube 2104, one is in conducting state, and another is then in cut-off state.
Similarly, synchronization, in the first PMOS 2106 and the second PMOS 2108, one is in conducting state, and another is then in cut-off state.Further, when the first NMOS tube 2102 is in conducting state, the second PMOS 2108 is also in conducting state, under the effect of the first NMOS tube 2102 and the second PMOS 2108, and input signal V
innoble potential be exaggerated.When the second NMOS tube 2104 is in conducting state, the first PMOS 2106 is also in conducting state, under the effect of the second NMOS tube 2104 and the first PMOS 2106, and input signal V
innoble potential exaggerated equally
Because described first change-over circuit 210 is identical with the circuit structure of the second change-over circuit 220, based on the principle of work same with described first change-over circuit 210, output signal after the first change-over circuit 210 amplifies inputs to the first NMOS tube and the phase inverter of the second change-over circuit 220 respectively, the finally output signal V of described second change-over circuit 220
in'.
Such as, input signal V
incan be 1V for high level, low level be the square-wave signal of 0V, and after the first change-over circuit 210, output high level is 4V, and low level is the square-wave signal of 0V, then after the second change-over circuit 220, output high level is 4V, and low level is the square-wave signal of 3V.
It should be noted that, in concrete enforcement, also after can first changing the electronegative potential of the signal of described pre-entered load circuit 120, again the noble potential of the signal that electronegative potential has been changed is changed, those skilled in the art with reference to the corresponding change-over circuit of vibrational power flow of above-mentioned first change-over circuit and the second change-over circuit, can repeat no more herein.
In concrete enforcement, described second level shift circuit can comprise: the 3rd change-over circuit and the 4th change-over circuit.Wherein, the output terminal of described 3rd change-over circuit is connected with the 4th change-over circuit.The noble potential of described 3rd change-over circuit to the signal of pre-entered load circuit is changed, the signal exported through described 3rd change-over circuit inputs to described 4th change-over circuit, the electronegative potential of described 4th change-over circuit to the signal that described 3rd change-over circuit exports is changed, and the signal that described 4th change-over circuit exports inputs to described load circuit.
In concrete enforcement, described second level shift circuit can be identical with the first level shift circuit structure.Such as, described 3rd change-over circuit and described 4th converting circuit structure all can comprise: for receiving the 3rd NMOS tube of input signal, the 4th NMOS tube, the 3rd PMOS, the 4th PMOS and for receiving input signal phase inverter; The grid of described 3rd NMOS tube is connected with the input end of described phase inverter, and source electrode is connected with the source electrode of described 4th NMOS tube, and drain electrode is connected with the drain electrode of described 3rd PMOS and the grid of described 4th PMOS respectively; The grid of described 4th NMOS tube is connected with the output terminal of described phase inverter, and drain electrode is connected with the grid of described 3rd PMOS and the drain electrode of the 4th PMOS; The source electrode of described 3rd PMOS is connected with the source electrode of described 4th NMOS tube.
It should be noted that, those skilled in the art can implement described 3rd change-over circuit and described 4th change-over circuit with reference to the circuit structure of above-mentioned first change-over circuit and the second change-over circuit, repeat no more herein.
It should be noted that, in concrete enforcement, also after can first changing the electronegative potential of the signal of described pre-entered load circuit 120, again the noble potential of the signal that electronegative potential has been changed is changed, those skilled in the art with reference to the corresponding change-over circuit of vibrational power flow of above-mentioned first change-over circuit and the second change-over circuit, can repeat no more herein.
See Fig. 3, in concrete enforcement, described LDO can comprise: comparer 302, Correctional tube 304, first resistance R
1and the second resistance R
2, the output terminal of described comparer 302 is connected with the control pole of described Correctional tube 304, the first pole of described Correctional tube 304 and described first resistance R
1first end and to be describedly connected with the low pressure input end of load circuit A320, the second pole of described Correctional tube 304 and power supply V
dDand to be describedly connected with the high voltage input terminal of load circuit A320, described first resistance R
1the second end and described second resistance R
2first end and described comparer 302 first input end connect, the second input end input reference voltage V of described comparer 302
ref.Described second resistance R
2the second end ground connection.The voltage that the output terminal of described LDO exports is V
dD' after wave filter C, input to load circuit B350.Described load circuit B is the load circuit be connected with the output terminal of LDO circuit, and described load circuit can be arbitrary load circuit, as long as can be connected with the output terminal of LDO circuit.
Wherein, the first input end of described comparer 302 can be in-phase end, and correspondingly, described second input end is end of oppisite phase.The first input end of described comparer 302 also can be end of oppisite phase, and accordingly, described second input end is in-phase end.Described Correctional tube 304 can be PMOS, also can be PNP type triode, can also be other Correctional tube.When described Correctional tube 304 is PMOS, the grid of the very described PMOS of described control, the drain electrode of the described first very described PMOS, the source electrode of the described second very described PMOS.
In the present embodiment, with described first input end for in-phase end, the second input end is end of oppisite phase, and described Correctional tube 304 for PMOS be that example is described.
As shown in Figure 3, the first resistance R
1the output voltage V of the second end
1input to the in-phase input end of comparer 302, comparer 302 is by V
1with reference voltage V
refcompare, and to described V
1with reference voltage V
refbetween difference amplify after export the grid of Correctional tube 304 to, and then control the pressure drop of described Correctional tube 304, thus stable output voltage V
dD'.In the present embodiment, by the drain voltage of described Correctional tube 304 and V
dDbe connected with the described high voltage input terminal with load circuit A320, source voltage is connected with the low pressure input end of load circuit A320 with described, thus can for described to provide with load circuit A320 normally work time required voltage.
In concrete enforcement, the integrated circuit of the present embodiment can also comprise the first level shift circuit 330 and the second level shift circuit 340.Wherein said first level shift circuit 330 is connected with the input end of described load circuit A320, for the current potential of the signal of load circuit A320 described in pre-entered being converted to the current potential being suitable for inputting described load circuit A320.Described second level shift circuit 340 is connected with the output terminal of described load circuit A320, and the current potential for the output signal by described load circuit A320 converts the current potential of the signal of load circuit A320 described in described pre-entered to.Concrete potential transfer process, with reference to the corresponding description of Fig. 2, can repeat no more herein.
It should be noted that, in concrete enforcement, LDO can also be adopted to provide required power supply for described second change-over circuit 220.Particularly, see Fig. 2 and Fig. 3, can by the drain voltage V of Correctional tube 304
dDbe connected with the drain electrode of described first PMOS 2206 and the drain electrode of the second PMOS 2208, by the source voltage of described Correctional tube 304, i.e. the output voltage V of described LDO
dD' be connected with the source electrode of the first NMOS tube 2202 of described second change-over circuit 220 and the source electrode of the second NMOS tube 2204.Like this, by the output V of described second change-over circuit 220
in' namely input ' input to load circuit A320, obtain the output V of corresponding load circuit A320
dD' namely export '.The output V of load circuit A320
dD' again through the second level shift circuit, obtain the output corresponding with the input of described first level shift circuit 330.As shown in Figures 1 and 2, described second change-over circuit exports V
in' the namely output of the first level shift circuit 130 namely input ', by the output of the first level shift circuit 130 input ' input to load circuit 120 after, the output obtaining load circuit 120 exports ', again through the second level shift circuit 140, obtain the output corresponding with the input of described first level shift circuit 130.
Embodiments of the invention additionally provide a kind of electronic equipment, and described electronic equipment comprises above-mentioned integrated circuit.Due in described integrated circuit, adopt LDO to provide required power supply for load circuit, effectively can reduce the area of integrated circuit, thus the volume of described electronic equipment can be reduced.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (9)
1. an integrated circuit, is characterized in that, comprising: at least one load circuit, and low pressure difference linear voltage regulator LDO, and described LDO is connected with the high voltage input terminal of described load circuit and low pressure input end respectively.
2. integrated circuit as claimed in claim 1, it is characterized in that, described LDO comprises: comparer, Correctional tube, first resistance and the second resistance, the output terminal of described comparer is connected with the control pole of described Correctional tube, first pole of described Correctional tube is connected with the first end of described first resistance and the low pressure input end of described load circuit, second pole of described Correctional tube is connected with the high voltage input terminal of power supply and described load circuit, second end of described first resistance is connected with the first end of described second resistance and the first input end of described comparer, second input end input reference voltage of described comparer, second end ground connection of described second resistance.
3. integrated circuit as claimed in claim 2, it is characterized in that, described Correctional tube is PMOS or PNP type triode.
4. integrated circuit as claimed in claim 1, it is characterized in that, also comprise: the first level shift circuit and the second level shift circuit, described first level shift circuit is connected with the input end of described load circuit, current potential for the signal by load circuit described in pre-entered converts the current potential being suitable for inputting described load circuit to, described second level shift circuit is connected with the output terminal of described load circuit, and the current potential for the output signal by described load circuit converts the current potential of the signal of load circuit described in described pre-entered to.
5. integrated circuit as claimed in claim 4, it is characterized in that, described first level shift circuit comprises: the first change-over circuit and the second change-over circuit be connected with the output terminal of described first change-over circuit, the noble potential of described first change-over circuit to the signal of pre-entered load circuit is changed, the signal exported through described first change-over circuit inputs to described second change-over circuit, the electronegative potential of described second change-over circuit to the signal that described first change-over circuit exports is changed, and the signal that described second change-over circuit exports inputs to described load circuit.
6. integrated circuit as claimed in claim 5, it is characterized in that, described first change-over circuit is identical with described second converting circuit structure, include: for receiving the first NMOS tube of input signal, second NMOS tube, the first PMOS, the second PMOS and for receiving input signal phase inverter; The grid of described first NMOS tube is connected with the input end of described phase inverter, and source electrode is connected with the source electrode of described second NMOS tube, and drain electrode is connected with the drain electrode of described first PMOS and the grid of described second PMOS respectively; The grid of described second NMOS tube is connected with the output terminal of described phase inverter, and drain electrode is connected with the grid of described first PMOS and the drain electrode of the second PMOS; The source electrode of described first PMOS is connected with the source electrode of described second NMOS tube.
7. integrated circuit as claimed in claim 4, it is characterized in that, described second level shift circuit comprises: the 3rd change-over circuit and the 4th change-over circuit be connected with the output terminal of described 3rd change-over circuit, the noble potential of described 3rd change-over circuit to the signal of pre-entered load circuit is changed, the signal exported through described 3rd change-over circuit inputs to described 4th change-over circuit, the electronegative potential of described 4th change-over circuit to the signal that described 3rd change-over circuit exports is changed, and the signal that described 4th change-over circuit exports inputs to described load circuit.
8. integrated circuit as claimed in claim 7, it is characterized in that, described 3rd change-over circuit is identical with described 4th converting circuit structure, include: for receiving the 3rd NMOS tube of input signal, 4th NMOS tube, the 3rd PMOS, the 4th PMOS and for receiving input signal phase inverter; The grid of described 3rd NMOS tube is connected with the input end of described phase inverter, and source electrode is connected with the source electrode of described 4th NMOS tube, and drain electrode is connected with the drain electrode of described 3rd PMOS and the grid of described 4th PMOS respectively; The grid of described 4th NMOS tube is connected with the output terminal of described phase inverter, and drain electrode is connected with the grid of described 3rd PMOS and the drain electrode of the 4th PMOS; The source electrode of described 3rd PMOS is connected with the source electrode of described 4th NMOS tube.
9. an electronic equipment, is characterized in that, comprises the integrated circuit as described in any one of claim 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310614172.3A CN104679083B (en) | 2013-11-27 | 2013-11-27 | Unicircuit and electronics |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310614172.3A CN104679083B (en) | 2013-11-27 | 2013-11-27 | Unicircuit and electronics |
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| Publication Number | Publication Date |
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| CN104679083A true CN104679083A (en) | 2015-06-03 |
| CN104679083B CN104679083B (en) | 2016-06-01 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101662277A (en) * | 2008-08-25 | 2010-03-03 | 台湾积体电路制造股份有限公司 | Adaptive voltage bias control system and integrated circuit |
| CN101807911A (en) * | 2010-03-25 | 2010-08-18 | 华为终端有限公司 | Level shift circuit and method |
| CN102495654A (en) * | 2011-11-25 | 2012-06-13 | 上海艾为电子技术有限公司 | Low-dropout regulator and integrated circuit system |
| CN202424296U (en) * | 2011-11-24 | 2012-09-05 | 比亚迪股份有限公司 | Two-way power supply unit |
| WO2013059810A1 (en) * | 2011-10-21 | 2013-04-25 | Qualcomm Incorporated | System and method to regulate voltage |
| CN203070144U (en) * | 2012-01-10 | 2013-07-17 | 成都芯源系统有限公司 | Low dropout voltage regulator and electronic circuit |
-
2013
- 2013-11-27 CN CN201310614172.3A patent/CN104679083B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101662277A (en) * | 2008-08-25 | 2010-03-03 | 台湾积体电路制造股份有限公司 | Adaptive voltage bias control system and integrated circuit |
| CN101807911A (en) * | 2010-03-25 | 2010-08-18 | 华为终端有限公司 | Level shift circuit and method |
| WO2013059810A1 (en) * | 2011-10-21 | 2013-04-25 | Qualcomm Incorporated | System and method to regulate voltage |
| CN202424296U (en) * | 2011-11-24 | 2012-09-05 | 比亚迪股份有限公司 | Two-way power supply unit |
| CN102495654A (en) * | 2011-11-25 | 2012-06-13 | 上海艾为电子技术有限公司 | Low-dropout regulator and integrated circuit system |
| CN203070144U (en) * | 2012-01-10 | 2013-07-17 | 成都芯源系统有限公司 | Low dropout voltage regulator and electronic circuit |
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| Publication number | Publication date |
|---|---|
| CN104679083B (en) | 2016-06-01 |
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