CN104617086A - Parallel structural integrated LED chip and production method thereof - Google Patents
Parallel structural integrated LED chip and production method thereof Download PDFInfo
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- CN104617086A CN104617086A CN201510062397.1A CN201510062397A CN104617086A CN 104617086 A CN104617086 A CN 104617086A CN 201510062397 A CN201510062397 A CN 201510062397A CN 104617086 A CN104617086 A CN 104617086A
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Abstract
The invention provides a parallel structural integrated LED chip and a production method thereof, and belongs to the technical field of packaging of semiconductor materials. The parallel structural integrated LED chip is that a plurality of rows of P surface metal connecting electrodes are prepared on the P surface of an epitaxial wafer; the epitaxial wafer is integrally bonded with a sapphire substrate through benzocyclobutene; a temporary substrate at one side of the epitaxial wafer is removed; insulating slots are respectively formed in the epitaxial wafer to enable metal interconnection of the P surfaces of each chip particles in the same row; the N surfaces of each chip particle in the same row are insulated from each other; each individual chip particle can be fixed and insulated at the same time through polyimide; the N surface electrode s are connected through metal, and thus the chip particles in each rank can be lengthways connected; as a result, the chip particles can be connected in parallel; when in packaging, a line is formed on the upper surface of a special electrode; in addition, the uniformity of the chip is ensured, so that the problem above in packaging can be avoided; the difficulty at packaging can be greatly reduced; the stability of the packaged chip can be improved.
Description
Technical field
The present invention relates to light-emitting diode technology of preparing, belong to the encapsulation technology field of semi-conducting material.
Background technology
At present for the LED integration packaging of multi-chip, because of its build-in attribute, there is the defect that it is intrinsic, such as the independently LED chip one by one of band encapsulation, carry out selecting of electrical property, forward voltage difference should more than 0.1V, and reverse voltage then must at more than 10V; And to antistatic be paid special attention to when making, once electrostatic problem appears in individual chip, probably causing large area to lose efficacy.When ensuing die bond, all LED chips need to keep same height in lengthwise position, on aluminium base when grooving, the size of groove and the degree of depth, according to chip number and the size of rising angle determine etc., encapsulation requirement is higher.These all defects, make downstream client when encapsulating, in order to keep chip uniformity, and the stability of finished product, often pay great effort.This provides for improved encapsulation difficulty, the stability remaining potted rear chip is also more difficult.
Summary of the invention
For the defect in prior art, the present invention seeks to propose a kind ofly to facilitate downstream client at the integrated LED chip of parallel-connection structure of encapsulation.
Technical solution of the present invention is: the core grain being bonded with some latticed array on same sapphire transparent substrate by adhesive layer, P pole with each core grain of a line is electrically connected to each other, and P bonding wire connection site is set in one end of each row core grain, the N pole of each core grain of same row is electrically connected to each other, and arranges N bonding wire connection site in one end of each row core grain.
The present invention adopts the mode of metal interconnection, makes core grain separately can conducting mutually.P face metal connects, and plays p side electrode effect simultaneously, makes the core grain lateral connection of every a line.N face electrode uses metal to couple together, and the core grain making each arrange longitudinally connects.So user can not need each core grain welding electrode, only welds on the electrode of specific region, just can reach and control the whether luminous a kind of chip of core grain.During use, making as needed a certain core grain in integrated LED chip luminous, only needing to allow electric current by the P on the row and column at this core grain place and N electrode, this core grain just can be allowed luminous.
Namely the present invention realizes the connection of multi-core grain in die terminals, makes downstream client when encapsulating, only need on special electrodes routing.And chip uniformity, can avoid occurring above-mentioned problem during encapsulation, significantly reduce encapsulation difficulty, improve the stability of the rear chip of encapsulation.
Another object of the present invention is the production technology of the integrated LED chip proposing more parallel structure.
Its technical scheme comprises the following steps:
1) in epitaxial wafer P profile, prepare at least two row P face metal connecting electrodes:
Temporary substrates GaAs makes and forms epitaxial wafer;
The P profile of epitaxial wafer deposits SiO
2layer, then at SiO
2layer erodes away through hole; Adopt electron beam evaporation methods, at SiO
2be packed into the metal level that figure is at least two row in layer and through hole thereof, to make metal be covered with whole epitaxial wafer P profile layer outer surface, form ohm articulamentum and reflector; Then adopt the way of chemical etching, produce at least two row P face metal connecting electrodes;
At the epi-layer surface coating benzocyclobutene of P face metal connecting electrode.
2) at the sapphire substrate surface coating benzocyclobutene of clean surface.
3) epitaxial wafer of coating benzocyclobutene and Sapphire Substrate are bonded together.
4) the temporary substrates GaAs of epitaxial wafer side is removed; Thus epitaxial loayer is transferred in the Sapphire Substrate of insulation.
5) utilize inductively coupled plasma etching technique, the epitaxial wafer being positioned at each row in Sapphire Substrate makes isolation channel respectively, make the only mutual metal connection in the P face of each core grain of same a line, and be isolated from each other in the N face of each core grain of same a line.
6) on epitaxial wafer, adopt spin coating method coating polyimide layer, then at polyimide layer applied atop photoresist, again by after semi-products exposure, development, bath, with the KOH aqueous solution, polyimide layer is corroded, polyimides is only existed in the isolation channel often between row core grain and fills up isolation channel; Again by the cooling after 120 DEG C ~ 230 DEG C solidifications of the epitaxial wafer of coating polyimide layer; Make polyimides stable be present in isolation channel; While each independent core grain being fixed by polyimides, also achieve insulation.
7) adopt negative photoresist to produce N face electrode pattern, adopt electron beam evaporation methods to be packed into metal level; Then N face metal connecting electrode is produced.N face electrode uses metal to couple together, and the core grain making each arrange longitudinally connects; Thus the parallel connection realized between each core grain.
The present invention is in step 1), utilize the metallic reflection light of high reflectance, utilize BCB bonding techniques to bond, because reflector metal itself is with figure, so ensure to be integrated at the core grain of same a line, and the core grain of adjacent lines can realize the isolation of P face.
On sapphire substrate epitaxial wafer upside-down mounting is bonded in by step 3), in step 4), peel off by the mode of chemical corrosion the GaAs substrate removing extinction again, and plate in the middle of epitaxial wafer and sapphire substrate figure, conduction, heat conductivility are good and have the multiple layer metal group of high reflectance.
Etch Cutting Road by step 5), the N face realized between the adjacent core grain of same a line is mutually isolated.
Made in different rows by step 7), but N between each core material of same row is extremely parallel with one another.
The present invention adopts spin coating mode to apply benzocyclobutene layer, active layer and transfer Sapphire Substrate is bonded together, can plays the effect of support, whole device can be made again to be not easy fragmentation after heating cure.In subsequent technique, by photo etched mask, removing of photoresist by plasma, the technology of alkaline solution corrosion, produces and needs device architecture, and use polyimides to be cured isolation.Finally form the product that design needs.
In addition, the present invention is in described step 1), and the benzocyclobutene being 1800 ~ 2000cp by viscosity with the speed of 4000 turns/min is coated in the epi-layer surface of P face metal connecting electrode.Viscosity is that 1800 ~ 2000cp benzocyclobutene chemical composition is more stable, and heat conduction is better.Speed 4000 turns be in order to THICKNESS CONTROL within 0.5 μm.Rotating speed and thickness relationship test out by experiment.
The benzocyclobutene thickness of coating is 0.5 μm.If benzocyclobutene thickness entirety, more than 1 μm, can affect heat radiation, also can spill into wafer surface during bonding, pollute.
In described step 2) in, with the speed of 3000 turns/min by viscosity be the benzocyclobutene coating of 1800 ~ 2000cp on a sapphire substrate.Same speed 3000 turns be in order to THICKNESS CONTROL within 0.5 μm.Rotating speed and thickness relationship are the preferred technique schemes testing out by experiment.
In order to ensure that benzocyclobutene thickness entirety is no more than 1 μm, the benzocyclobutene thickness of coating is 0.5 μm.
In described step 3), the pressure condition of described bonding is 300kg/m
2, temperature is 200 DEG C, and pressure action time is 1h.Pressure 300kg/m
2, use benzocyclobutene this material to carry out bonding, because it is similar to viscous liquid, although through drying, if pressure is too large, still can cause spilling or local thickness uneven.Temperature is 200 DEG C, and in order to some solvent evaporates in benzocyclobutene be fallen, bonding that can be good, plays the effect of a solidification.Through overtesting, as pressure is too short for action time, solvent evaporates is clean, and pressure is long for action time, then the adhesive layer in the middle of will blackening, cracking, so preferred pressure of the present invention action time is 1h.
In described step 6), with the speed of 5000 turns/min coating photoresist on polyimide layer; When developing, service quality percentage is the KOH aqueous solution of 3.5%, the development of the 45s that develops under 20 ~ 25 DEG C of ambient temperatures; The mass percent of the KOH aqueous solution of corrosion be 3%.
The ratio of viscosities of polyimides own is higher, if when rotating speed is lower, carrier film thickness is likely uneven, because substrate surface has inevitable defect, use the even glue of high rotating speed, can avoid the impact of substrate defects, whole surface thickness can be more even.Verified by many experiments, the rotating speed of 5000 turns/min is relatively applicable to this technique.
Using the KOH aqueous solution of different proportion, is for different materials, to photoresist, uses 3.5%, speed is fast, and graphical quality is good, but this concentration is just higher for polyimides, have larger lateral erosion, so when corroding polyimides, just ratio is reduced.Temperature and developing time preferred is all grope out according to repeatedly reaction experiment.
In described step 6), described solidification is: first toast 1 hour under temperature is the environment of 120 DEG C, then by homogeneous temperature rise to 150 DEG C after, constant temperature toasts 1 hour again, then temperature increase is kept cooling after hour to 230 DEG C; The process of described cooling is divided into two stages, the first stage, in one hour, temperature is reduced to 150 DEG C by 230 DEG C, second stage, with one hour, temperature is reduced to initial 120 DEG C by 150 DEG C.The method of this temperature control stage by stage, can prevent the polyimide film embrittlement of solidification, cracking effectively.
In described step 1), metal level is evaporation three-layer metal at twice, the down payment of first evaporation thickness 500, and then evaporation thickness is the metal A uZn layer of 1000, and finally evaporation thickness is the metal A u layer of 5500 ~ 6000 again.
Ground floor is down payment, object be increase metal and wafer surface adhering, but in order to not affect ohmic contact, so can not be too thick, 500 or suitable.The second layer is metal A uZn layer, is exactly ohmic contact doped layer, by alloy, makes to form ohmic contact between electrode and semiconductor, and Zn is used to do and adulterates.Last metal A u, adopting thickness to be 6000 is the effects playing a stable protection, and certain electrode integral is thicker, and conductance also can be improved.These metal vapor deposition layer layer distributed are in whole SiO
2layer and through hole in.
In described step 4), described alkaline corrosion liquid is by NH
4oH, H
2o
2and H
2o is by volume for the ratio of 1:5:5 is mixed.For GaAs material, NH
4oH and H
2o
2mixed liquor corrosion is that effectiveness comparison is fast, but because this chemical reaction is heat release reflection, easily cause the phenomenon that corrosion is excessive, in order to effectively control reaction process, the mixed solution of special ratios is taked extremely to be necessary, through many experiments checking, the ratio of 1:5:5 has good effect.
In described step 7), N electrode material adopts AuGe/Au/Al/Au to make, and thickness is respectively 1500,1000,60000 and 500.
As a whole, electrode has certain thickness, can improve the collection efficiency of photogenerated current, and use this conductivity of Al very outstanding, the metal of relative inexpensiveness, as electrode, is proper.And the situation highly significant that Au and Al melts altogether, makes the possibility of electrode hierarchy very little.Later layer Au considers in order to existing encapsulation technology, because Au ratio is easier to welding under existing process conditions.AuGe is equally in order to form ohmic contact evaporation, and experiment proves, for the epitaxial structure that the present invention adopts, the AuGe of 1500 just can form good ohmic contact.
Accompanying drawing explanation
Fig. 1 is a kind of plan view of the present invention.
Fig. 2 is that the A-A of Fig. 1 is to cut-away view.
Fig. 3 is the process chart of production method of the present invention.
Fig. 4 is the schematic diagram obtaining semi-products in production process.
Fig. 5 is the schematic diagram obtaining second half goods in production process.
Embodiment
Concrete manufacture method, as shown in Figure 3:
1, utilize PECVD technology, the epitaxial wafer that temporary substrates GaAs makes to apply a layer thickness be the refractive index of 800 ~ 900nm is the SiO of 1.6
2.
2, at deposition SiO
2after, utilize photoresist mask technique, and for the technique of photoresist, increase the time of exposure, photoresist can be exposed fully, in development, the KOH solution of 4% is used to develop, temperature controls between 20 ~ 25 DEG C, and through the development of 1min, KOH solution by the graphic making above photoresist out, now the wafer with photoresist is carried out the fast row that washes by water, through bath after a while, hydrone by the KOH solution molecular replacement in photoetching offset plate figure out, does object prevents KOH solution to SiO like this
2the corrosion of layer, finally, uses HF solution, the SiO in the place protected not having photoresist
2etch away.Like this, just at SiO
2regular figure through hole has been produced above layer.
3, at the SiO with through hole of epitaxial wafer
2on layer, electron beam evaporation technique is adopted to be packed into metal level: whole metal level is divided into three layers to carry out evaporation: the first evaporation layer is Au, and thickness is approximately 500 dusts; Second evaporation layer is AuZn, and thickness is 1000 dusts; 3rd evaporation layer is Au, and thickness is 5500 ~ 6000 dusts.These metal vapor deposition layer layer distributed are in whole SiO
2layer and through hole in.
4, adopt photo etched mask technology, utilize photoresist to produce the P electrode graphics shape being divided into several rows at layer on surface of metal, then use I and KI mixed liquor, metal is etched, finally obtains p side electrode connection layout.These metals and the SiO deposited before
2together, all-metal mirror (ODR) layer is formed.
As shown in Figure 4, because reflector metal itself is with figure, so ensure to be integrated at the core grain of same a line, and the core grain of adjacent lines can realize the isolation of P face, and P1, P2, P3 and P4 of the arrangement that is namely divided into lines as seen are in the diagram capable.
5, in all-metal mirror (ODR) layer surface deposition a layer thickness be the SiO of 2000 dusts
2after, 450 DEG C of annealing 15min.P face is made to form ohmic contact.And then by SiO
2remove.
6, the benzocyclobutene being 1800 ~ 2000cp by viscosity with the speed of 4000 turns/min is coated in the epi-layer surface of P face metal connecting electrode, and the benzocyclobutene thickness of coating is 0.5 μm.With the speed of 3000 turns/min by viscosity be the benzocyclobutene coating of 1800 ~ 2000cp on a sapphire substrate, the benzocyclobutene thickness of coating is 0.5 μm.
Under 300kg pressure, 200 DEG C of conditions, by relative with the benzocyclobutene layer in Sapphire Substrate for the benzocyclobutene layer on epitaxial wafer pressing 60min, both are made to be bonded together.
7, the temporary substrates GaAs using alkaline corrosion liquid to get rid of (or stripping) to go on the epitaxial wafer of semi-products after bonding.Epitaxial structure is transferred in Sapphire Substrate.
Wherein, alkaline corrosion liquid adopts NH
4oH and H
2o
2with H
2o is by volume for 1:5:5 is mixed.
8, utilize photoresist as mask, use the etching of ICP(inductively coupled plasma), the epitaxial wafer being positioned at each row in Sapphire Substrate makes isolation channel respectively, makes the only mutual metal connection in the P face of each core grain of same a line, and be isolated from each other in the N face of each core grain of same a line.As shown in Figure 5.
9, one deck protection SiO is first deposited
2, then when substrate rotates, full-bodied polyimides (5000 ~ 6000cp) is coated on the substrate of basilar memebrane.Formed and there is the polyimide layer that thickness is 50 ~ 120 μm.After the spin-coating, utilize photoresist mask technique, face applies one deck photoresist on polyimide, selects the even glue of the slow-speed of revolution, because uneven phenomenon appears in the polyimides that the too high meeting of rotating speed applies before causing.For the thick adhesive process of photoresist, increase the time of exposure, photoresist can be exposed fully, in development, the KOH solution of 4% is used to develop, temperature controls between 20 ~ 25 DEG C, through the development of 1min, KOH solution by the graphic making above photoresist out, now the wafer with photoresist and polyimides is carried out washing by water and arrange soon, through bath after a while, hydrone by the KOH solution molecular replacement in photoetching offset plate figure out, do object prevents KOH solution to the corrosion of polyimide layer like this, because in this step, KOH solution containing photoresist molecule is very fast to polyimide layer corrosion rate, more severe by lateral erosion of polyimides layer pattern can be caused.After the fast row of bath, use 3%KOH solution, polyimide layer is further corroded, owing to reducing KOH solution concentration, the figure of polyimides obtains good control, is now removed by the photoresist above polyimides with acetone, like this, just between each chip, polyimides is used to make separator.
10, the goods upper step made are cured under 120 DEG C ~ 230 DEG C ambient temperatures, then lower the temperature.
During solidification, in the first stage, adopt the time of 4 hours, have the environment of 120 DEG C in temperature under, toast one hour, moisture in polyimides is evaporated fully, then, in ensuing one hour, temperature is risen to 150 DEG C uniformly by 120 DEG C, and 150 DEG C of constant temperature one hour, the polyimides of different viscosities is merged, after polyimides merges, utilize the time of 1 hour, temperature increase is kept one hour to 230 DEG C, allow the polyimides merged be solidified, now start cooling.
The process of cooling is divided into two stages, the first stage, in one hour, temperature is reduced to 150 DEG C by 230 DEG C, second stage, utilizes one hour equally, temperature is reduced to initial about 120 DEG C by 150 DEG C.This method of lowering the temperature stage by stage, effectively can prevent the polyimide film embrittlement of solidifying, cracking.
11, after solidification, first remove cutoff layer, use electrode evaporation and negative glue lift-off technology, complete the making of the N face metal contact wires between the N face electrode of each core grain and the adjacent core grain on same row.And erode the GaAs that surface is exposed.
Wherein, N face electrode material and N face metal contact wires adopt AuGe/Au/Al/Au to make, and thickness is respectively 1500,1000,60000 and 500.
12, test, scribing.
Two, the product structure feature formed:
As shown in Figure 1, 2, same sapphire transparent substrate 500 is bonded with by benzocyclobutene adhesive layer 300 the core grain 100 of some latticed array, P pole with each core grain 100 of a line is interconnected, spaced with adhesive layer 300 between the P pole of adjacent lines, and P bonding wire connection site P1, P2, P3, P4 are set in one end of each row core grain, the N pole of each core grain of same row is interconnected by N face metal contact wires 900, and arranges N bonding wire connection site N1, N2, N3 in one end of each row core grain.
As seen from Figure 2, in the P face of each core grain 100 of same a line, mutual metal connects.Be isolated from each other by isolation channel 200 in the N face of each core grain 100 of same a line, between the N face in isolation channel 200 with adjacent each core grain 100 of a line, be provided with N face metal contact wires 900.
Only need P1, P2, P3, P4 and N1, N2, N3 position in FIG to weld during use, just can control any one core grain luminous.Such as, want to make in Fig. 1, to be positioned at a P3 core grain that is capable and N2 row place luminous, only need to allow electric current by P3 and N2 electrode, this core grain just can be allowed luminous.
Claims (10)
1. the integrated LED chip of a parallel-connection structure, it is characterized in that the core grain being bonded with some latticed array on same sapphire transparent substrate by adhesive layer, P pole with each core grain of a line is electrically connected to each other, and P bonding wire connection site is set in one end of each row core grain, the N pole of each core grain of same row is electrically connected to each other, and arranges N bonding wire connection site in one end of each row core grain.
2. a production method for the integrated LED chip of parallel-connection structure as claimed in claim 1, is characterized in that comprising the following steps:
1) in epitaxial wafer P profile, prepare at least two row P face metal connecting electrodes:
Temporary substrates GaAs makes and forms epitaxial wafer;
The P profile of epitaxial wafer deposits SiO
2layer, then at SiO
2layer erodes away through hole; Adopt electron beam evaporation methods, at SiO
2be packed into the metal level that figure is at least two row in layer and through hole thereof, to make metal be covered with whole epitaxial wafer P profile layer outer surface, form ohm articulamentum and reflector; Then adopt the way of chemical etching, produce at least two row P face metal connecting electrodes;
At the epi-layer surface coating benzocyclobutene of P face metal connecting electrode;
2) at the sapphire substrate surface coating benzocyclobutene of clean surface;
3) epitaxial wafer of coating benzocyclobutene and Sapphire Substrate are bonded together;
4) the temporary substrates GaAs of epitaxial wafer side is removed;
5) utilize inductively coupled plasma etching technique, the epitaxial wafer being positioned at each row in Sapphire Substrate makes isolation channel respectively, make the only mutual metal connection in the P face of each core grain of same a line, and be isolated from each other in the N face of each core grain of same a line;
6) on epitaxial wafer, adopt spin coating method coating polyimide layer, then at polyimide layer applied atop photoresist, again by after semi-products exposure, development, bath, with the KOH aqueous solution, polyimide layer is corroded, polyimides is only existed in the isolation channel often between row core grain and fills up isolation channel; Again by the cooling after 120 DEG C ~ 230 DEG C solidifications of the epitaxial wafer of coating polyimide layer;
7) adopt negative photoresist to produce N face electrode pattern, adopt electron beam evaporation methods to be packed into metal level; Then N face metal connecting electrode is produced.
3. the production method of the integrated LED chip of parallel-connection structure according to claim 2, it is characterized in that in described step 1), the benzocyclobutene being 1800 ~ 2000cp by viscosity with the speed of 4000 turns/min is coated in the epi-layer surface of P face metal connecting electrode, and the benzocyclobutene thickness of coating is 0.5 μm.
4. the production method of the integrated LED chip of parallel-connection structure according to claim 2, it is characterized in that in described step 2) in, with the speed of 3000 turns/min by viscosity be the benzocyclobutene coating of 1800 ~ 2000cp on a sapphire substrate, the benzocyclobutene thickness of coating is 0.5 μm.
5. the production method of the integrated LED chip of parallel-connection structure according to claim 2, it is characterized in that in described step 3), the pressure condition of described bonding is 300kg/m
2, temperature is 200 DEG C, and pressure action time is 1h.
6. the production method of the integrated LED chip of parallel-connection structure according to claim 2, is characterized in that in described step 6), with the speed of 5000 turns/min coating photoresist on polyimide layer; When developing, service quality percentage is the KOH aqueous solution of 3.5%, the development of the 45s that develops under 20 ~ 25 DEG C of ambient temperatures; The mass percent of the KOH aqueous solution of corrosion be 3%.
7. the production method of the integrated LED chip of parallel-connection structure according to claim 2, it is characterized in that in described step 6), described solidification is: first toast 1 hour under temperature is the environment of 120 DEG C, then by homogeneous temperature rise to 150 DEG C after, constant temperature toasts 1 hour again, then temperature increase is kept cooling after hour to 230 DEG C; The process of described cooling is divided into two stages, the first stage, in one hour, temperature is reduced to 150 DEG C by 230 DEG C, second stage, with one hour, temperature is reduced to initial 120 DEG C by 150 DEG C.
8. the production method of the integrated LED chip of parallel-connection structure according to Claims 2 or 3 or 4 or 5 or 6 or 7, it is characterized in that in described step 1), metal level is evaporation three-layer metal at twice, the down payment of first evaporation thickness 500, then evaporation thickness is the metal A uZn layer of 1000, and finally evaporation thickness is the metal A u layer of 5500 ~ 6000 again.
9. the production method of the integrated LED chip of parallel-connection structure according to Claims 2 or 3 or 4 or 5 or 6 or 7, it is characterized in that in described step 4), described alkaline corrosion liquid is by NH
4oH, H
2o
2and H
2o is by volume for the ratio of 1:5:5 is mixed.
10. the production method of the integrated LED chip of parallel-connection structure according to Claims 2 or 3 or 4 or 5 or 6 or 7, it is characterized in that in described step 7), N electrode material adopts AuGe/Au/Al/Au to make, and thickness is respectively 1500,1000,60000 and 500.
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| CN104157757A (en) * | 2014-08-15 | 2014-11-19 | 天津三安光电有限公司 | Quaternary light-emitting diode (LED) with transparent substrate and manufacturing method |
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| CN204441283U (en) * | 2015-02-06 | 2015-07-01 | 扬州乾照光电有限公司 | A kind of integrated LED chip of parallel-connection structure |
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| US20030020084A1 (en) * | 1991-01-18 | 2003-01-30 | Kopin Corporation | Method of making light emitting diode displays |
| CN1734796A (en) * | 2004-08-02 | 2006-02-15 | 晶元光电股份有限公司 | LED with bonding layer and making method thereof |
| CN101090128A (en) * | 2007-06-20 | 2007-12-19 | 中国科学院长春光学精密机械与物理研究所 | LED array microdisplay device and manufacturing method |
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