EP1523762A2 - Method for making an anisotropic conductive polymer film on a semiconductor wafer - Google Patents

Method for making an anisotropic conductive polymer film on a semiconductor wafer

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Publication number
EP1523762A2
EP1523762A2 EP03748222A EP03748222A EP1523762A2 EP 1523762 A2 EP1523762 A2 EP 1523762A2 EP 03748222 A EP03748222 A EP 03748222A EP 03748222 A EP03748222 A EP 03748222A EP 1523762 A2 EP1523762 A2 EP 1523762A2
Authority
EP
European Patent Office
Prior art keywords
conductive
layer
inserts
polymer film
connection pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03748222A
Other languages
German (de)
French (fr)
Inventor
Jean-Charles Souriau
Pierre Renard
Jean Brun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Publication of EP1523762A2 publication Critical patent/EP1523762A2/en
Withdrawn legal-status Critical Current

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    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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    • H01L23/53204Conductive materials
    • H01L23/5328Conductive materials containing conductive organic materials or pastes, e.g. conductive adhesives, inks
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Definitions

  • the invention relates to a method for making an anisotropic conductive polymer film on a semiconductor wafer.
  • the invention also relates to a method for manufacturing a semiconductor chip provided with an anisotropic conductive polymer film as well as a semiconductor chip provided with an anisotropic conductive polymer film.
  • This technology is based on the implementation of a process on a complete wafer of semiconductor material requiring two levels of lithography: a first level to define the metallurgy for attaching microbeads and a second level dedicated to the electrolytic deposition of fusible materials. This method cannot be used for the interconnection of cut chips or when the number of wafers to be treated is too low to justify the drawing of specific masks necessary for the lithography step.
  • the ACF technique relates to conductive films made of conductive particles incorporated in an insulating film or of metallic inserts included in an insulating film.
  • ACF films with conductive particles incorporated in an insulating film are the best known.
  • This type of film is based on a random distribution of conductive particles in a polymer matrix.
  • the conductive particles typically have a diameter of a few microns. These are either metal coated polymer beads, or metal beads which can be, for example, nickel or silver.
  • the interconnection is obtained by bonding the film between the substrate and the chip, bonding being followed by thermocompression.
  • the interconnection of a chip and a substrate using a film with conductive particles is shown in FIG. 1A.
  • a chip 1 provided with conductive pads 5 is connected to a substrate 2 provided with conductive pads 7.
  • An ACF film consisting of an insulating film 3 in which 'conductive particles 4 are incorporated is placed between the chip and the substrate.
  • Bosses 6 establish contact between the studs conductors and ACF film.
  • This type of interconnection leads to a relatively high electrical contact resistance, which reduces the scope of its fields of application.
  • ACF films with through metal inserts The production of an ACF film with through metal inserts is based on the orderly insertion of metallic microstructures into a sheet of polymer.
  • the interconnection of a chip and a substrate using a film with through metal inserts is shown in FIG. 1B.
  • the ACF film consists of an insulating film 8 in which metal inserts are placed 9.
  • a high redundancy in the number of contacts per pad ensures a homogeneous contact of low resistivity and making it possible to pass large currents.
  • ACF films causes several problems, including that of the reliability of the electrical contact. Indeed, oxidized layers are formed on the ends of the metal inserts and on the interconnection pads of the chip, which leads to greatly reducing the quality of the electrical contacts.
  • a solution has been proposed to this problem, namely, the addition of a fusible material to the ends of the metal inserts.
  • the fusible material is liable to creep during its redesign and, consequently, to short-circuit the metal inserts.
  • impurities can be reported between the film and the chip or between the film and its substrate during hybridization.
  • the films are produced on a rigid sacrificial support which must be separated from the ACF film before hybridization. It is then necessary to assemble three elements, the chip, the film and the substrate.
  • the present invention does not have the drawbacks mentioned above.
  • the invention relates to an anisotropic conductive polymer film making process on a wafer coated semiconductor, on a 'face, a passivation layer is practiced wherein at least one opening exposing a bonding pad electric.
  • the method comprises at least the following successive steps:
  • the filling of the through holes is carried out by electrolytic growth assisted or not by an electric field.
  • the method according to the invention comprises, between the step of filling the through holes with one or more materials conductors and the step of removing the polymer layer, the following successive steps: deposition of a photosensitive resin on the photosensitive polymer layer in which the conductive inserts are formed, exposure and development of the photosensitive resin through a mask so that only one resin pellet remains at the top of a first end of each insert, - isotropic chemical etching of the first ends of the conductive inserts until the resin pellets are removed so that a point appears on the first end of each conductive insert.
  • the invention also relates to a method for manufacturing a semiconductor chip.
  • the method comprises a method for manufacturing an anisotropic conductive polymer film on a semiconductor wafer according to the invention and a step for cutting a structure resulting from said anisotropic conductive polymer film on a semiconductor wafer.
  • the invention also relates to a semiconductor chip comprising, on one side, a passivation layer in which is formed at least one opening revealing a connection pad.
  • the chip comprises, on the passivation layer and the connection pad, an anisotropic conductive polymer film consisting of conductive inserts enclosed in an insulating material, a conductive insert having a first end projecting from the insulating material and one. second end brought into contact with the passivation layer or the connection pad via a conductive element.
  • the anisotropic conductive film according to the invention is produced directly on a wafer of semiconductor material in which active and / or passive elements of the integrated circuit type are present. The method according to the invention ensures an excellent electrical connection between the metals brought into contact.
  • the metal inserts are connected to the interconnection pads almost irreversibly thanks to a non-fusible hanging material.
  • the anisotropic conductive polymer film makes it possible to make chip-substrate contacts having a low electrical resistance, a good mechanical solidity and a good reliability.
  • FIGS. 1A and 1B represent the interconnection of a chip and a substrate according to the known art, using, respectively, an anisotropic conductive polymer film with conductive particles and an anisotropic conductive polymer film with conductive inserts;
  • FIG. 2 represents a chip equipped with an anisotropic conductive polymer film according to the invention;
  • FIGS. 3A-3I represent a method of manufacturing an anisotropic conductive polymer film on a semiconductor wafer according to the invention,
  • FIGS. 4A-4F represent a variant of the manufacturing process shown in FIGS. 3A-3I.
  • the same references designate the same elements. Detailed description of methods of implementing the invention
  • FIG. 2 represents an example of a semiconductor chip equipped with an anisotropic conductive polymer film according to the invention.
  • a chip 10 is provided with an interconnection pad 11 placed in an opening of a passivation layer 12.
  • a conductive film 13 comprising a layer of insulating material 14 in which are placed conductive inserts 15 covers the passivation layer 12 and the connection pad 11.
  • a metal insert 15 has a first end which projects from the insulating film 14 and a second end connected by a conductive element 16 to the passivation layer 12 or to the conductive stud 11.
  • the conductive element 16 consists of a metal pad 17 and a hooking element 18.
  • the method is implemented from a slice 'of semiconductor material.
  • a semiconductor wafer T is covered, on one side, with a passivation layer 12 in which are made openings revealing connection pads 11 (cf. FIG. 3A).
  • the first step of the process is the deposition in full layer of a conductive and adherent material 19 on the passivation layer 12 and the connection pads 11 (cf. FIG. 3B).
  • the conductive and adherent material 19 is, for example, Ti, Cr, W, Ta, etc. This step is preferably carried out after pickling the surface of the pads.
  • the deposition of at least one metallic layer 20 (Cu, Ni, Ti, Au, Al, etc.) is then carried out on the layer 19 (see Figure 3C).
  • the metal layer 20 is intended to serve as an electric current supply layer at the time of the electrolytic growth of the conductive inserts.
  • a layer of photosensitive polymer 21 of the resin type is then deposited on the metal layer 20 (cf. FIG. 3D).
  • the thickness of the photosensitive polymer layer 21 is between a few ⁇ m and several tens of ⁇ m.
  • the layer 21 is then exposed through a mask in order to form through holes 22 (cf. FIG. 3E).
  • the holes can have a depth of a few ⁇ m to several tens of ⁇ m, depending on the thickness ' of the layer 21.
  • the mask allowing the formation of the holes ensures a homogeneous and redundant distribution of these.
  • the holes are then filled with one or more conductive materials (Cu, Ni, Ti, Cr, W, SnPb, Au, Ag, etc.), for example electrolytically, to form conductive inserts 23 (cf. FIG. 3F) .
  • the resin is then removed, for example by dissolution, (see Figure 3G).
  • the layer of conductive and adherent material 19 and the metallic layer 20 constitute a conductive layer which is then selectively etched in the zones situated between the inserts (cf. FIG. 3H).
  • the etched layers 19 and 20 then form the conductive elements 16, each element 16 comprising a metal patch 17 coming from the metal layer 20 and a hooking element 18 coming from the layer 19.
  • the connection pads 11 are then ' electrically isolated one another.
  • This step can be accomplished by dry or chemical means, the latter being preferred.
  • An insulating material 24 is deposited on the plate, partially covering the metal inserts (cf. FIG. 31). In the case where the insulating material completely covers the inserts, an engraving is carried out to update them.
  • This material is preferably a polymer such as a polyimide, a thermoplastic material, a photosensitive resin or any type of adhesive. It is also possible to spread a fusible glass commonly called "Spin On Glass".
  • the conductive inserts have a pointed end allowing an improvement in the electrical contact of the anisotropic conductive polymer film and of the substrates on which it is desired to carry the chips.
  • the method according to the variant of the invention comprises additional steps between the step of forming the conductive inserts (cf. FIG. 3F) and the step of removing the photosensitive polymer layer (cf. FIG. 3G).
  • the step of forming the conductive inserts is followed here by the deposition of a photosensitive resin 25 on all of the inserts (cf. FIG. 4A).
  • the photosensitive resin is exposed through a mask so that only one resin pellet 26 remains at the top of each insert (cf. FIG. 4B). Isotropic etching, for example wet or dry
  • inserts are then produced (cf. FIG. 4C) until the resin pellets are removed
  • an anisotropic conductive polymer film produced directly on a chip considerably simplifies the method of hybridization of the chip on a substrate. Indeed, it is no longer necessary to manipulate a film to interpose it between the chip and the substrate. Only two elements are to be handled, the chip and the substrate. In addition, thanks to the bonding layer present under the inserts, the electrical contact of the anisotropic conductive polymer film on the chip is of very good quality. Other advantages of the method according to the invention can be emphasized. Thus, the production of an anisotropic conductive polymer film according to the method of the invention does not require a critical alignment step since the redundancy of the holes made during the etching step (cf. FIG.

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Abstract

The invention concerns a method for making an anisotropic conductive polymer film (23, 24) on a semiconductor wafer (T) comprising, on one face, a passivation layer (12) wherein is provided at least one opening exposing a bond pad (11). The invention is useful for forming components (chips, integrated circuits) with high interconnect density.

Description

PROCEDE DE FABRICATION DE FILM POLYMERE CONDUCTEUR ANISOTROPE SUR TRANCHE DE SEMI-CONDUCTEUR PROCESS FOR PRODUCING ANISOTROPIC CONDUCTIVE POLYMER FILM ON SEMICONDUCTOR WAFER
Domaine technique et art antérieur: L' invention concerne un procédé de f brication de film polymère conducteur anisotrope sur tranche de semi-conducteur. L'invention concerne également un procédé de fabrication de puce semi-conductrice munie d'un film polymère conducteur anisotrope ainsi qu'une puce semi-conductrice munie d'un film polymère conducteur anisotrope.TECHNICAL FIELD AND PRIOR ART: The invention relates to a method for making an anisotropic conductive polymer film on a semiconductor wafer. The invention also relates to a method for manufacturing a semiconductor chip provided with an anisotropic conductive polymer film as well as a semiconductor chip provided with an anisotropic conductive polymer film.
Avec l'essor du multimédia, de nombreux dispositifs électroniques doivent être capables de gérer, de traiter et de transmettre rapidement et facilement une grande quantité d'informations. Ces dispositifs nécessitent un accroissement de la densité des interconnexions ainsi qu'une diminution de leur poids et de leur coût de fabrication.With the rise of multimedia, many electronic devices must be able to manage, process and transmit large amounts of information quickly and easily. These devices require an increase in the density of the interconnections as well as a reduction in their weight and in their manufacturing cost.
Il existe plusieurs grandes familles de techniques pour connecter des puces et des circuits intégrés à des substrats d'interconnexion comme, par exemple, la technique de connexion par billes dite technique « flip-chip » et la technique ACF (ACF pour « Anisotropic Conductive Film ») . Ces techniques présentent un certain nombre d' avantages pour l'intégration des circuits.' Compte tenu de la répartition surfacique des plots d' interconnexion, elles offrent la capacité de connecter des puces à haute densité d' interconnexions dans un volume réduit tout en maintenant ou en améliorant les performances électriques, notamment en diminuant les effets de self- inductance. Ces techniques sont utilisées, par exemple, dans les téléphones cellulaires et, plus généralement, dans les dispositifs multimédia, comme cela a été mentionné ci-dessus. Parmi les techniques de type « flip-chip », la technologie par microbilles fusibles est celle qui prédomine actuellement. Cette technologie repose sur la mise en œuvre d'un procédé sur tranche complète de matériau semi-conducteur nécessitant deux niveaux de lithographie: un premier niveau pour définir la métallurgie d'accrochage des microbilles et un second niveau dédié au dépôt électrolytique de matériaux fusibles. Ce procédé n'est pas utilisable pour l'interconnexion de puces découpées ou lorsque le nombre de tranches à traiter est trop faible pour justifier le dessin de masques spécifiques nécessaires à l'étape de lithographie.There are several major families of techniques for connecting chips and integrated circuits to interconnection substrates such as, for example, the ball connection technique known as the “flip-chip” technique and the ACF technique (ACF (Anisotropic Conductive Film). "). These techniques have a number of advantages for integrating circuits. '' Given the surface distribution of the interconnection pads, they offer the ability to connect high density interconnection chips in a reduced volume while maintaining or improving electrical performance, in particular by reducing the effects of self-inductance . These techniques are used, for example, in cell phones and, more generally, in multimedia devices, as mentioned above. Among the “flip-chip” type techniques, the technology by fusible microbeads is that which currently predominates. This technology is based on the implementation of a process on a complete wafer of semiconductor material requiring two levels of lithography: a first level to define the metallurgy for attaching microbeads and a second level dedicated to the electrolytic deposition of fusible materials. This method cannot be used for the interconnection of cut chips or when the number of wafers to be treated is too low to justify the drawing of specific masks necessary for the lithography step.
La technique ACF concerne des films conducteurs faits de particules conductrices incorporées dans un film isolant ou d' inserts métalliques inclus dans un film isolant.The ACF technique relates to conductive films made of conductive particles incorporated in an insulating film or of metallic inserts included in an insulating film.
Les films ACF à particules conductrices incorporées dans un film isolant sont les plus connus. Ce type de film est basé sur une répartition aléatoire de particules conductrices dans une matrice polymère. Les particules conductrices ont typiquement un diamètre de quelques microns. Ce sont soit des billes de polymère recouvertes de métal, soit des billes de métal qui peuvent être, par exemple, en nickel ou en argent. L' interconnexion est obtenue en collant le film entre le substrat et la puce, le collage étant suivi d'une thermocompression. L'interconnexion d'une puce et d'un substrat à l'aide d'un film à particules conductrices est représenté en figure 1A. Une puce 1 munie de plots conducteurs 5 est reliée à un substrat 2 muni de plots conducteurs 7. Un film ACF constitué d'un film isolant 3 dans lequel ' sont incorporées des particules conductrices 4 est placé entre la puce et le substrat. Des bossages 6 établissent le contact entre les plots conducteurs et le film ACF. Ce type d'interconnexion conduit à une résistance électrique de contact relativement élevée, ce qui réduit le champ de ses domaines d'application. Une application connue est, par exemple, le domaine des écrans plats.ACF films with conductive particles incorporated in an insulating film are the best known. This type of film is based on a random distribution of conductive particles in a polymer matrix. The conductive particles typically have a diameter of a few microns. These are either metal coated polymer beads, or metal beads which can be, for example, nickel or silver. The interconnection is obtained by bonding the film between the substrate and the chip, bonding being followed by thermocompression. The interconnection of a chip and a substrate using a film with conductive particles is shown in FIG. 1A. A chip 1 provided with conductive pads 5 is connected to a substrate 2 provided with conductive pads 7. An ACF film consisting of an insulating film 3 in which 'conductive particles 4 are incorporated is placed between the chip and the substrate. Bosses 6 establish contact between the studs conductors and ACF film. This type of interconnection leads to a relatively high electrical contact resistance, which reduces the scope of its fields of application. A known application is, for example, the field of flat screens.
L'inconvénient mentionné ci-dessus a conduit à la conception des films ACF à inserts métalliques traversants. La fabrication d'un film ACF à inserts métalliques traversants est basée sur l'insertion ordonnée de microstructures métalliques dans une nappe de polymère. L'interconnexion d'une puce et d'un substrat à l'aide d'un film à inserts métalliques traversants est représenté en figure 1B. Le film ACF est constitué d'un film isolant 8 dans lequel sont placés des inserts métalliques 9. Une forte redondance du nombre de contacts par plot assure un contact homogène de faible résistivité et permettant de passer des courants importants.The above-mentioned drawback has led to the design of ACF films with through metal inserts. The production of an ACF film with through metal inserts is based on the orderly insertion of metallic microstructures into a sheet of polymer. The interconnection of a chip and a substrate using a film with through metal inserts is shown in FIG. 1B. The ACF film consists of an insulating film 8 in which metal inserts are placed 9. A high redundancy in the number of contacts per pad ensures a homogeneous contact of low resistivity and making it possible to pass large currents.
L'utilisation des films ACF entraîne cependant plusieurs problèmes parmi lesquels celui de la fiabilité du contact électrique. En effet, il se forme des couches oxydées sur les extrémités des inserts métalliques et sur les plots d'interconnexion de la puce, ce qui conduit à fortement réduire la qualité des contacts électriques. Une solution a été proposée à ce problème, à savoir, l'ajout d'un matériau fusible aux extrémités des inserts métalliques. Cependant, le matériau fusible est susceptible de fluer pendant sa refonte et, partant, de mettre en court-circuit les inserts métalliques. De plus, des impuretés peuvent être rapportées entre le film et la puce ou entre le film et son substrat pendant l'hybridation.The use of ACF films, however, causes several problems, including that of the reliability of the electrical contact. Indeed, oxidized layers are formed on the ends of the metal inserts and on the interconnection pads of the chip, which leads to greatly reducing the quality of the electrical contacts. A solution has been proposed to this problem, namely, the addition of a fusible material to the ends of the metal inserts. However, the fusible material is liable to creep during its redesign and, consequently, to short-circuit the metal inserts. In addition, impurities can be reported between the film and the chip or between the film and its substrate during hybridization.
Un autre problème est lié à la manipulation des films ACF de faible épaisseur. Les films sont réalisés sur un support sacrificiel rigide qu' il faut séparer du film ACF avant l'hybridation. Il faut alors assembler trois éléments, la puce, le film et le substrat. La présente invention ne présente pas les inconvénients mentionnés ci-dessus.Another problem is related to the handling of thin ACF films. The films are produced on a rigid sacrificial support which must be separated from the ACF film before hybridization. It is then necessary to assemble three elements, the chip, the film and the substrate. The present invention does not have the drawbacks mentioned above.
Exposé de l' inventionStatement of the invention
En effet, l'invention concerne un procédé de fabrication de film polymère conducteur anisotrope sur une tranche de semi-conducteur recouverte, sur une ' face, d'une couche de passivation dans laquelle est pratiquée au moins une ouverture laissant apparaître un plot de connexion électrique. Le procédé comprend au moins les étapes successives suivantes :Indeed, the invention relates to an anisotropic conductive polymer film making process on a wafer coated semiconductor, on a 'face, a passivation layer is practiced wherein at least one opening exposing a bonding pad electric. The method comprises at least the following successive steps:
- dépôt d'une couche conductrice sur la couche de passivation et sur le plot de connexion,- deposition of a conductive layer on the passivation layer and on the connection pad,
- dépôt d'une couche de polymère photosensible sur la couche conductrice,- deposition of a photosensitive polymer layer on the conductive layer,
- insolation et développement de la couche de polymère photosensible à travers un masque afin de former des trous traversants,- exposure and development of the photosensitive polymer layer through a mask in order to form through holes,
- remplissage des trous traversants par un ou plusieurs matériaux conducteurs de façon à former un insert conducteur dans chaque trou,- filling the through holes with one or more conductive materials so as to form a conductive insert in each hole,
- suppression de la couche de polymère photosensible, - gravure de la couche conductrice dans les zones situées entre les inserts,- removal of the photosensitive polymer layer, - etching of the conductive layer in the areas between the inserts,
- dépôt d'une couche de matériau isolant entre les inserts conducteurs.- deposit of a layer of insulating material between the conductive inserts.
Selon un mode de réalisation avantageux, le remplissage des trous traversants est effectué par croissance électrolytique assistée ou- non d'un champ électrique.According to an advantageous embodiment, the filling of the through holes is carried out by electrolytic growth assisted or not by an electric field.
Selon une variante, le procédé selon l'invention comprend, entre l'étape de remplissage des trous traversants par un ou plusieurs matériaux conducteurs et l'étape de suppression de la couche de polymère, les étapes successives suivantes : dépôt d'une résine photosensible sur la couche de polymère photosensible dans laquelle sont formés les inserts conducteurs, insolation et développement de la résine photosensible à travers un masque de sorte que seule une pastille de résine demeure au sommet d'une première extrémité de chaque insert, - gravure chimique isotrope des premières extrémités des inserts conducteurs jusqu'au retrait des pastilles de résine de sorte qu'une pointe apparaisse sur la première extrémité de chaque insert conducteur. L'invention concerne également un procédé de fabrication de puce semi-conductrice. Le procédé comprend un procédé de fabrication de film polymère conducteur anisotrope sur tranche de semi-conducteur selon l'invention et une étape de découpe d'une structure issue dudit procédé de fabrication de film polymère conducteur anisotrope sur tranche de semiconducteur.According to a variant, the method according to the invention comprises, between the step of filling the through holes with one or more materials conductors and the step of removing the polymer layer, the following successive steps: deposition of a photosensitive resin on the photosensitive polymer layer in which the conductive inserts are formed, exposure and development of the photosensitive resin through a mask so that only one resin pellet remains at the top of a first end of each insert, - isotropic chemical etching of the first ends of the conductive inserts until the resin pellets are removed so that a point appears on the first end of each conductive insert. The invention also relates to a method for manufacturing a semiconductor chip. The method comprises a method for manufacturing an anisotropic conductive polymer film on a semiconductor wafer according to the invention and a step for cutting a structure resulting from said anisotropic conductive polymer film on a semiconductor wafer.
L' invention concerne encore une puce semi- conductrice comprenant, sur une face, une couche de passivation dans laquelle est pratiquée au moins une ouverture laissant apparaître un plot de connexion. La puce comprend, sur la couche de passivation et le plot de connexion, un film polymère conducteur anisotrope constitué d' inserts conducteurs enserrés dans un matériau isolant, un insert conducteur ayant une première extrémité faisant saillie hors du matériau isolant et une. deuxième extrémité mise au contact de la couche de passivation ou du plot de connexion par l' intermédiaire 'd'un élément conducteur. Le film conducteur anisotrope selon l'invention est réalisé directement sur une tranche de matériau semi-conducteur dans laquelle sont présents des éléments actifs et/ou passifs de type circuits intégrés. Le procédé selon l'invention permet d'assurer une excellente liaison électrique entre les métaux mis en contact. Les inserts métalliques sont reliés aux plots d'interconnexion de manière quasi irréversible grâce à un matériau d'accroché non fusible. Le film polymère conducteur anisotrope permet de réaliser des contacts puce-substrat présentant une faible résistance électrique, une bonne solidité mécanique et une bonne fiabilité.The invention also relates to a semiconductor chip comprising, on one side, a passivation layer in which is formed at least one opening revealing a connection pad. The chip comprises, on the passivation layer and the connection pad, an anisotropic conductive polymer film consisting of conductive inserts enclosed in an insulating material, a conductive insert having a first end projecting from the insulating material and one. second end brought into contact with the passivation layer or the connection pad via a conductive element. The anisotropic conductive film according to the invention is produced directly on a wafer of semiconductor material in which active and / or passive elements of the integrated circuit type are present. The method according to the invention ensures an excellent electrical connection between the metals brought into contact. The metal inserts are connected to the interconnection pads almost irreversibly thanks to a non-fusible hanging material. The anisotropic conductive polymer film makes it possible to make chip-substrate contacts having a low electrical resistance, a good mechanical solidity and a good reliability.
Brève description des figuresBrief description of the figures
D'autres caractéristiques et avantages de l'invention apparaîtront à la lecture d'un mode de réalisation préférentiel de l'invention fait en référence .aux figures jointes parmi lesquelles : - les figures 1A et 1B représentent l'interconnexion d'une puce et d'un substrat selon l'art connu, à l'aide, respectivement, d'un film polymère conducteur anisotrope à particules conductrices et d'un film polymère conducteur anisotrope à inserts conducteurs ; la figure 2 représente une puce équipée d'un film polymère conducteur anisotrope selon l'invention ; les figures 3A-3I représentent un procédé de fabrication de film polymère conducteur anisotrope sur tranche de semi-conducteur selon l'invention, les figures 4A-4F représentent une variante du procédé de fabrication représenté aux figures 3A-3I. Sur toutes les figures, les mêmes repères désignent les mêmes éléments. Description détaillée de modes de mise en œuyre de 1' inventionOther characteristics and advantages of the invention will appear on reading a preferred embodiment of the invention made with reference to the attached figures, in which: FIGS. 1A and 1B represent the interconnection of a chip and a substrate according to the known art, using, respectively, an anisotropic conductive polymer film with conductive particles and an anisotropic conductive polymer film with conductive inserts; FIG. 2 represents a chip equipped with an anisotropic conductive polymer film according to the invention; FIGS. 3A-3I represent a method of manufacturing an anisotropic conductive polymer film on a semiconductor wafer according to the invention, FIGS. 4A-4F represent a variant of the manufacturing process shown in FIGS. 3A-3I. In all the figures, the same references designate the same elements. Detailed description of methods of implementing the invention
La figure 2 représente un exemple de puce semi- conductrice équipée d'un film polymère conducteur anisotrope selon l'invention.FIG. 2 represents an example of a semiconductor chip equipped with an anisotropic conductive polymer film according to the invention.
Une puce 10 est munie d'un plot d'interconnexion 11 placé dans une ouverture d'une couche de passivation 12. Un film conducteur 13 comprenant une couche de matériau isolant 14 dans laquelle sont placés des inserts conducteurs 15 recouvre la couche de passivation 12 et le plot de connexion 11. Un insert métallique 15 a une première extrémité qui fait saillie hors du film isolant 14 et une deuxième extrémité reliée par un élément conducteur 16 à la couche de passivation 12 ou au plot conducteur 11. L'élément conducteur 16 est constitué d'une pastille métallique 17 et d'un élément d'accrochage 18.A chip 10 is provided with an interconnection pad 11 placed in an opening of a passivation layer 12. A conductive film 13 comprising a layer of insulating material 14 in which are placed conductive inserts 15 covers the passivation layer 12 and the connection pad 11. A metal insert 15 has a first end which projects from the insulating film 14 and a second end connected by a conductive element 16 to the passivation layer 12 or to the conductive stud 11. The conductive element 16 consists of a metal pad 17 and a hooking element 18.
Le procédé de fabrication de film polymère conducteur sur tranche de semi-conducteur selon l'invention va maintenant être décrit en référence aux figures 3A-3I.The process for manufacturing a conductive polymer film on a semiconductor wafer according to the invention will now be described with reference to FIGS. 3A-3I.
Le procédé est mis en œuvre à partir d'une tranche' de matériau semi-conducteur. Une tranche de semi-conducteur T est recouverte, sur une face, d'une couche de passivation 12 dans laquelle sont pratiquées des ouvertures laissant apparaître des plots de connexion 11 (cf. figure 3A) . La première étape du procédé est le dépôt en pleine couche d'un matériau conducteur et adhérent 19 sur la couche de passivation 12 et les plots de connexion 11 (cf. figure 3B) . Le matériau conducteur et adhérent 19 est, par exemple, du Ti, Cr, W, Ta, etc. Cette étape est préférentiellement réalisée après un décapage de la surface des plots. Le dépôt d'au moins une couche métallique 20 (Cu, Ni, Ti, Au, Al, etc.) est ensuite effectué sur la couche 19 (cf. figure 3C) . La couche métallique 20 est destinée à servir de couche d' apport de courant électrique au moment de la croissance électrolytique des inserts conducteurs. On dépose ensuite une couche de polymère photosensible 21 de type résine sur la couche métallique 20 (cf. figure 3D) . L'épaisseur de la couche de polymère photosensible 21 est comprise entre quelques μm et plusieurs dizaines de μm. La couche 21 est ensuite insolée à travers un masque afin de former des trous traversants 22 (cf. figure 3E) . Typiquement les trous peuvent avoir une profondeur de quelques μm à plusieurs dizaines de μm, selon l'épaisseur 'de la couche 21. Le masque permettant la formation des trous assure une répartition homogène et redondante de ceux- ci. Les trous sont ensuite remplis par un ou plusieurs matériaux conducteurs (Cu, Ni, Ti, Cr, W, SnPb, Au, Ag, etc.), par exemple par voie électrolytique, pour former des inserts conducteurs 23 (cf. figure 3F) . La résine est alors supprimée, par exemple par dissolution, (cf. figure 3G) . La couche de matériau conducteur et adhérent 19 et la couche métallique 20 constituent une couche conductrice qui est alors gravée sélectivement dans les zones situées entre les inserts (cf. figure 3H) . Les couches 19 et 20 gravées forment alors les éléments conducteurs 16, chaque élément 16 comportant une pastille métallique 17 issue de la couche métallique 20 et un élément d'accrochage 18 issu de la couche 19. Les plots de connexion 11 sont alors' électriquement isolés les uns des autres. Cette' étape peut se réaliser par voie sèche ou chimique, cette dernière étant préférée. Un matériau isolant 24 est déposé sur la plaque, recouvrant partiellement .les inserts métalliques (cf. figure 31) . Dans le cas où le matériau isolant recouvre entièrement les inserts, on procède à une gravure pour les mettre à jour. Ce matériau est préferentiellement un polymère tel qu'un polyimide, un matériau thermoplastique, une résine photosensible ou tout type de colle. Il est également possible d'étaler un verre fusible communément appelé « Spin On Glass ».The method is implemented from a slice 'of semiconductor material. A semiconductor wafer T is covered, on one side, with a passivation layer 12 in which are made openings revealing connection pads 11 (cf. FIG. 3A). The first step of the process is the deposition in full layer of a conductive and adherent material 19 on the passivation layer 12 and the connection pads 11 (cf. FIG. 3B). The conductive and adherent material 19 is, for example, Ti, Cr, W, Ta, etc. This step is preferably carried out after pickling the surface of the pads. The deposition of at least one metallic layer 20 (Cu, Ni, Ti, Au, Al, etc.) is then carried out on the layer 19 (see Figure 3C). The metal layer 20 is intended to serve as an electric current supply layer at the time of the electrolytic growth of the conductive inserts. A layer of photosensitive polymer 21 of the resin type is then deposited on the metal layer 20 (cf. FIG. 3D). The thickness of the photosensitive polymer layer 21 is between a few μm and several tens of μm. The layer 21 is then exposed through a mask in order to form through holes 22 (cf. FIG. 3E). Typically the holes can have a depth of a few μm to several tens of μm, depending on the thickness ' of the layer 21. The mask allowing the formation of the holes ensures a homogeneous and redundant distribution of these. The holes are then filled with one or more conductive materials (Cu, Ni, Ti, Cr, W, SnPb, Au, Ag, etc.), for example electrolytically, to form conductive inserts 23 (cf. FIG. 3F) . The resin is then removed, for example by dissolution, (see Figure 3G). The layer of conductive and adherent material 19 and the metallic layer 20 constitute a conductive layer which is then selectively etched in the zones situated between the inserts (cf. FIG. 3H). The etched layers 19 and 20 then form the conductive elements 16, each element 16 comprising a metal patch 17 coming from the metal layer 20 and a hooking element 18 coming from the layer 19. The connection pads 11 are then ' electrically isolated one another. This step can be accomplished by dry or chemical means, the latter being preferred. An insulating material 24 is deposited on the plate, partially covering the metal inserts (cf. FIG. 31). In the case where the insulating material completely covers the inserts, an engraving is carried out to update them. This material is preferably a polymer such as a polyimide, a thermoplastic material, a photosensitive resin or any type of adhesive. It is also possible to spread a fusible glass commonly called "Spin On Glass".
Pour obtenir une puce semi-conductrice selon l'invention, il suffit alors de découper la tranche de semi-conducteur recouverte de film polymère conducteur anisotrope en autant de puces élémentaires qu'il est nécessaire.To obtain a semiconductor chip according to the invention, it then suffices to cut the semiconductor wafer covered with anisotropic conductive polymer film into as many elementary chips as necessary.
Une variante du procédé de fabrication de film polymère conducteur selon l'invention va maintenant être décrite en référence aux figures 4A-4F. Selon cette variante, les inserts conducteurs ont une extrémité pointue permettant une amélioration du contact électrique du film polymère conducteur anisotrope et des substrats sur lesquels on désire réporter les puces.A variant of the method for manufacturing a conductive polymer film according to the invention will now be described with reference to FIGS. 4A-4F. According to this variant, the conductive inserts have a pointed end allowing an improvement in the electrical contact of the anisotropic conductive polymer film and of the substrates on which it is desired to carry the chips.
Le procédé selon la variante de l'invention comprend des étapes supplémentaires entre l'étape de formation des inserts conducteurs (cf. figure 3F) et l'étape de suppression de la couche de polymère photosensible (cf. figure 3G) . Selon la variante de l'invention, à l'étape de formation des inserts conducteurs, succède ici le dépôt d'une résine photosensible 25 sur l'ensemble des inserts (cf. figure 4A) . La résine photosensible est insolée à travers un masque de sorte que seule une pastille de résine 26 demeure au sommet de chaque insert (cf. figure 4B) . Une gravure isotrope, par exemple par voie humide ou sècheThe method according to the variant of the invention comprises additional steps between the step of forming the conductive inserts (cf. FIG. 3F) and the step of removing the photosensitive polymer layer (cf. FIG. 3G). According to the variant of the invention, the step of forming the conductive inserts is followed here by the deposition of a photosensitive resin 25 on all of the inserts (cf. FIG. 4A). The photosensitive resin is exposed through a mask so that only one resin pellet 26 remains at the top of each insert (cf. FIG. 4B). Isotropic etching, for example wet or dry
(par exemple acide nitrique dilué pour des inserts en nickel) , des inserts est alors réalisée (cf. figure 4C) jusqu'à ce que les pastilles de résine soient retirées(for example diluted nitric acid for nickel inserts), inserts are then produced (cf. FIG. 4C) until the resin pellets are removed
(cf. figure 4D) . Une pointe 27 apparaît alors à l'extrémité de chaque insert. Le procédé se poursuit alors selon les étapes mentionnées précédemment, à savoir, suppression de la couche de polymère photosensible et gravure sélective des couches métalliques déposées en pleine couche (cf. figure 4E) . A la gravure sélective des couches métalliques succède le dépôt d'un matériau isolant 24 recouvrant les inserts à l'exception des pointes 27 (cf. figure 4F) .(cf. Figure 4D). A point 27 then appears at the end of each insert. The process then continues according to the steps mentioned above, namely, removal of the photosensitive polymer layer and selective etching of the metal layers deposited in full layer (cf. FIG. 4E). The selective etching of the metal layers is followed by the deposition of an insulating material 24 covering the inserts with the exception of the tips 27 (cf. FIG. 4F).
La présence d'un film polymère conducteur anisotrope réalisé directement sur une puce, comme cela est décrit ci-dessus, simplifie considérablement le procédé d'hybridation de la puce sur un substrat. En effet, il n'est alors plus nécessaire de manipuler un film pour l'interposer entre la puce et le substrat. Seuls deux éléments sont à manipuler, la puce et le substrat. De plus, grâce à la couche d'accrochage présente sous les inserts, le contact électrique du film polymère conducteur anisotrope sur la puce est de très bonne qualité. D'autres avantages du procédé selon l'invention peuvent être soulignés. Ainsi, la fabrication d'un film polymère conducteur anisotrope selon le procédé de l'invention ne nécessite-t-il pas d'étape d'alignement critique puisque la redondance des trous effectués lors de l'étape de gravure (cf. figure 3E) conduit à une redondance des inserts conducteurs telle qu'il y a nécessairement des inserts au-dessus des plots à connecter. Un autre avantage consiste en ce que la fabrication d'un film polymère conducteur anisotrope selon le procédé de l'invention permet d'utiliser tout type de polymère, voir même du verre fusible. The presence of an anisotropic conductive polymer film produced directly on a chip, as described above, considerably simplifies the method of hybridization of the chip on a substrate. Indeed, it is no longer necessary to manipulate a film to interpose it between the chip and the substrate. Only two elements are to be handled, the chip and the substrate. In addition, thanks to the bonding layer present under the inserts, the electrical contact of the anisotropic conductive polymer film on the chip is of very good quality. Other advantages of the method according to the invention can be emphasized. Thus, the production of an anisotropic conductive polymer film according to the method of the invention does not require a critical alignment step since the redundancy of the holes made during the etching step (cf. FIG. 3E ) leads to a redundancy of the conductive inserts such that there are necessarily inserts above the pads to be connected. Another advantage consists in that the manufacture of an anisotropic conductive polymer film according to the process of the invention makes it possible to use any type of polymer, even see fusible glass.

Claims

REVENDICATIONS
1. Procédé de fabrication de film polymère conducteur anisotrope sur une tranche de semi- conducteur comprenant, sur une face, une couche de passivation (12) dans laquelle est pratiquée au moins une ouverture laissant apparaître un plot de connexion1. Method for manufacturing anisotropic conductive polymer film on a semiconductor wafer comprising, on one face, a passivation layer (12) in which is formed at least one opening revealing a connection pad
(11), caractérisé en ce qu'il comprend au moins les étapes suivantes : - dépôt d'une couche conductrice (19, 20) sur la couche de passivation (12) et sur le plot de connexion (11) de la tranche de semi-conducteur, dépôt d'une couche de polymère photosensible (21) sur la couche conductrice (20) , - insolation et développement de la couche de polymère photosensible (21) à travers un masque afin de former des trous traversants (22), remplissage des trous traversants (22) par un ou plusieurs matériaux conducteurs de façon à former un insert conducteur (23) dans chaque trou, suppression de la couche de polymère photosensible (21), gravure de la couche conductrice (19, 20) dans les zones situées entre les inserts conducteurs, - dépôt d'une couche de matériau isolant (24) entre les inserts conducteurs.(11), characterized in that it comprises at least the following steps: - deposition of a conductive layer (19, 20) on the passivation layer (12) and on the connection pad (11) of the wafer semiconductor, deposition of a photosensitive polymer layer (21) on the conductive layer (20), - exposure and development of the photosensitive polymer layer (21) through a mask in order to form through holes (22), filling of the through holes (22) with one or more conductive materials so as to form a conductive insert (23) in each hole, removal of the photosensitive polymer layer (21), etching of the conductive layer (19, 20) in the areas located between the conductive inserts, - deposition of a layer of insulating material (24) between the conductive inserts.
2. Procédé selon la revendication 1, caractérisé en ce que la couche conductrice (19, 20) comporte une couche de matériau conducteur et adhérent2. Method according to claim 1, characterized in that the conductive layer (19, 20) comprises a layer of conductive and adherent material
(19) déposée sur la couche de passivation et sur le plot de connexion et au moins une couche métallique(19) deposited on the passivation layer and on the connection pad and at least one metallic layer
(20) déposée sur la couche de matériau conducteur et adhérent . (20) deposited on the layer of conductive and adherent material.
3. Procédé selon la revendication 1 ou 2, caractérisé en ce qu'il comprend, entre l'étape de remplissage des trous traversants (22) et l'étape de suppression de la couche de polymère, les étapes successives suivantes :3. Method according to claim 1 or 2, characterized in that it comprises, between the step of filling the through holes (22) and the step of removing the polymer layer, the following successive steps:
- dépôt d'une résine photosensible sur la couche de polymère photosensible dans laquelle sont formés .les inserts conducteurs, insolation et développement de la résine photosensible à travers un masque de sorte que seule une pastille de résine (26) demeure au sommet d'une première extrémité de chaque insert, gravure chimique isotrope des premières extrémités des inserts jusqu'au retrait des pastilles de résine de sorte qu'une pointe (27) apparaisse sur la première extrémité de chaque insert.- depositing a photosensitive resin on the layer of photosensitive polymer in which the conductive inserts are formed, exposure and development of the photosensitive resin through a mask so that only one resin pellet (26) remains at the top of a first end of each insert, isotropic chemical etching of the first ends of the inserts until the resin pellets are removed so that a point (27) appears on the first end of each insert.
4. Procédé selon l'une quelconque des revendications 1 à 3, caractérisé en ce que le remplissage des trous traversants est effectué par croissance électrolytique.4. Method according to any one of claims 1 to 3, characterized in that the filling of the through holes is carried out by electrolytic growth.
5. Procédé selon l'une quelconque des revendications précédentes, caractérisé en ce que la gravure de la couche conductrice (19, 20) est une gravure humide ou une gravure sèche.5. Method according to any one of the preceding claims, characterized in that the etching of the conductive layer (19, 20) is a wet etching or a dry etching.
6. Procédé de fabrication de puce semi- conductrice, caractérisé en ce qu'il comprend un procédé de fabrication de film polymère conducteur anisotrope sur une tranche de semi-conducteur selon l'une des revendications 1 à 5 et une étape de découpe d'une structure obtenue par ledit procédé de fabrication de film polymère conducteur anisotrope. 6. A method of manufacturing semiconductor chip, characterized in that it comprises a method of manufacturing anisotropic conductive polymer film on a semiconductor wafer according to one of claims 1 to 5 and a step of cutting out a structure obtained by said process for manufacturing anisotropic conductive polymer film.
7. Puce semi-conductrice comprenant, sur une face, une couche de passivation (12) dans laquelle est pratiquée au moins une ouverture laissant apparaître un plot de connexion (11), caractérisée en ce qu'elle comprend, sur la couche de passivation (12) et le plot de connexion (11) , un film polymère conducteur anisotrope constitué d' inserts conducteurs (15) enserrés dans un matériau isolant (14) , un insert conducteur (15) ayant une première extrémité faisant saillie hors du matériau isolant (14) et une deuxième extrémité mise en contact, par l'intermédiaire d'un plot conducteur (16) , soit de la couche de passivation7. Semiconductor chip comprising, on one side, a passivation layer (12) in which is formed at least one opening revealing a connection pad (11), characterized in that it comprises, on the passivation layer (12) and the connection pad (11), an anisotropic conductive polymer film consisting of conductive inserts (15) enclosed in an insulating material (14), a conductive insert (15) having a first end protruding from the insulating material (14) and a second end brought into contact, via a conductive pad (16), or the passivation layer
(12), soit du plot de connexion (11) selon que la deuxième extrémité de l' insert est respectivement en regard, soit de la couche de passivation (12) , soit du plot de connexion (11) .(12), either of the connection pad (11) depending on whether the second end of the insert is respectively opposite, either of the passivation layer (12), or of the connection pad (11).
8. Puce semi-conductrice selon la revendication 7, caractérisée en ce que chaque élément conducteur (16) comprend un matériau conducteur adhérent (18) et un matériau métallique (17) .8. Semiconductor chip according to claim 7, characterized in that each conductive element (16) comprises an adherent conductive material (18) and a metallic material (17).
9. Puce semi-conductrice selon la revendication 7 ou 8, caractérisée en ce que les premières extrémités sont en forme de pointes (27) .9. Semiconductor chip according to claim 7 or 8, characterized in that the first ends are in the form of points (27).
10. Puce semi-conductrice selon l'une quelconque des revendications 7 à 9, caractérisée en ce que le matériau isolant est un polyimide, un matériau thermoplastique, une résine photosensible ou une colle.10. Semiconductor chip according to any one of claims 7 to 9, characterized in that the insulating material is a polyimide, a thermoplastic material, a photosensitive resin or an adhesive.
11. Puce semi-conductrice selon l'une quelconque des revendications 7 à 9, caractérisée en ce que le matériau isolant est un verre fusible. 11. Semiconductor chip according to any one of claims 7 to 9, characterized in that the insulating material is a fusible glass.
EP03748222A 2002-07-24 2003-07-22 Method for making an anisotropic conductive polymer film on a semiconductor wafer Withdrawn EP1523762A2 (en)

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FR0209378A FR2842943B1 (en) 2002-07-24 2002-07-24 METHOD FOR MANUFACTURING ANISOTROPIC CONDUCTIVE POLYMER FILM ON SEMICONDUCTOR WAFER
FR0209378 2002-07-24
PCT/FR2003/002312 WO2004012226A2 (en) 2002-07-24 2003-07-22 Method for making an anisotropic conductive polymer film on a semiconductor wafer

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Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8518304B1 (en) 2003-03-31 2013-08-27 The Research Foundation Of State University Of New York Nano-structure enhancements for anisotropic conductive material and thermal interposers
FR2857780B1 (en) * 2003-07-18 2005-09-09 Commissariat Energie Atomique METHOD FOR MANUFACTURING ANISOTROPIC CONDUCTIVE FILM ON A SUBSTRATE
FR2866753B1 (en) * 2004-02-25 2006-06-09 Commissariat Energie Atomique MICROELECTRONIC INTERCONNECTION DEVICE WITH LOCALIZED CONDUCTIVE RODS
US7785494B2 (en) * 2007-08-03 2010-08-31 Teamchem Company Anisotropic conductive material
KR101485105B1 (en) * 2008-07-15 2015-01-23 삼성전자주식회사 Semiconductor packages
US9677042B2 (en) 2010-10-08 2017-06-13 Terumo Bct, Inc. Customizable methods and systems of growing and harvesting cells in a hollow fiber bioreactor system
KR101513642B1 (en) * 2013-08-21 2015-04-20 엘지전자 주식회사 A device of a semiconductor
US9617506B2 (en) 2013-11-16 2017-04-11 Terumo Bct, Inc. Expanding cells in a bioreactor
EP3613841B1 (en) 2014-03-25 2022-04-20 Terumo BCT, Inc. Passive replacement of media
EP3198006B1 (en) 2014-09-26 2021-03-24 Terumo BCT, Inc. Scheduled feed
CN107113984B (en) * 2014-12-19 2019-06-04 富士胶片株式会社 Multi-layered wiring board
WO2017004592A1 (en) 2015-07-02 2017-01-05 Terumo Bct, Inc. Cell growth with mechanical stimuli
US11965175B2 (en) 2016-05-25 2024-04-23 Terumo Bct, Inc. Cell expansion
US11685883B2 (en) 2016-06-07 2023-06-27 Terumo Bct, Inc. Methods and systems for coating a cell growth surface
US11104874B2 (en) 2016-06-07 2021-08-31 Terumo Bct, Inc. Coating a bioreactor
US11624046B2 (en) 2017-03-31 2023-04-11 Terumo Bct, Inc. Cell expansion
EP3656842A1 (en) 2017-03-31 2020-05-27 Terumo BCT, Inc. Cell expansion
KR102608888B1 (en) * 2019-06-04 2023-12-01 (주)포인트엔지니어링 Anodic oxidation for electric contacting and opto electronic display and manufacturing method of opto electronic

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5543585A (en) * 1994-02-02 1996-08-06 International Business Machines Corporation Direct chip attachment (DCA) with electrically conductive adhesives
FR2726397B1 (en) * 1994-10-28 1996-11-22 Commissariat Energie Atomique ANISOTROPIC CONDUCTIVE FILM FOR MICROCONNECTICS
FR2766618B1 (en) * 1997-07-22 2000-12-01 Commissariat Energie Atomique METHOD FOR MANUFACTURING ANISOTROPIC CONDUCTIVE FILM WITH CONDUCTIVE INSERTS
JP2001223240A (en) * 2000-02-10 2001-08-17 Nitto Denko Corp Semiconductor device
US6803303B1 (en) * 2002-07-11 2004-10-12 Micron Technology, Inc. Method of fabricating semiconductor component having encapsulated, bonded, interconnect contacts

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2004012226A2 *

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