CN104576576A - Semiconductor package piece and manufacturing method thereof - Google Patents

Semiconductor package piece and manufacturing method thereof Download PDF

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Publication number
CN104576576A
CN104576576A CN201310513715.2A CN201310513715A CN104576576A CN 104576576 A CN104576576 A CN 104576576A CN 201310513715 A CN201310513715 A CN 201310513715A CN 104576576 A CN104576576 A CN 104576576A
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CN
China
Prior art keywords
perforate
inner diameter
diameter
semiconductor package
negative dielectric
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Granted
Application number
CN201310513715.2A
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Chinese (zh)
Other versions
CN104576576B (en
Inventor
蔡崇宣
谢爵安
约翰·R·杭特
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to CN201310513715.2A priority Critical patent/CN104576576B/en
Priority to CN201710898783.3A priority patent/CN107658284B/en
Publication of CN104576576A publication Critical patent/CN104576576A/en
Application granted granted Critical
Publication of CN104576576B publication Critical patent/CN104576576B/en
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13008—Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention relates to a semiconductor package piece and a manufacturing method thereof. The semiconductor package piece comprises a chip, a conductive layer, a negative dielectric layer and an electrical contact. The chip is provided with an active surface. The conductive layer is electrically connected with the active surface. The negative dielectric layer is covered with the conductive layer and provided with an open hole, a part of the open hole is exposed out of the conductive layer, the open hole is provided with a minimum inside diameter, a top inside diameter and a bottom inside diameter, and the minimum inside diameter is located between the bottom inside diameter and the top inside diameter. The electrical contact is formed in the open hole.

Description

Semiconductor package part and manufacture method thereof
Technical field
The invention relates to a kind of semiconductor package part and manufacture method thereof, and relate to semiconductor package part and manufacture method thereof that its perforate a kind of has outstanding madial wall especially.
Background technology
Traditional semiconductor package part at least comprises several defeated in/out contact, and semiconductor package part can be made to be electrically connected at a external circuit board by this little defeated in/out contact.But semiconductor package part is located in the external circuit board process, defeated in/out contact can be stressed and cause defeated in/out contact easily to destroy, as be full of cracks, fracture or damage.
Summary of the invention
The present invention has about a kind of semiconductor package part and manufacture method thereof, can improve semiconductor package part and be located in the process of another electronic component, the problem that its defeated in/out contact easily destroys.
According to the present invention, a kind of semiconductor package part is proposed.Semiconductor package part comprises a chip, a conductive layer, a negative dielectric layer and an electrical contact.Chip has an active surface.Conductive layer is electrically connected at active surface.Negative dielectric layer covers conductive layer and has a perforate, and a part for conductive layer is exposed in perforate, and perforate has a minimum diameter, a top internal diameter and a bottom inner diameter, and minimum diameter is between bottom inner diameter and top internal diameter.Electrical contact is formed in perforate.
According to the present invention, a kind of manufacture method of semiconductor package part is proposed.Manufacture method comprises the following steps.There is provided a chip, chip has an active surface, and is formed with a conductive layer above the active surface of chip, and conductive layer is electrically connected at active surface; Form a negative dielectric material and cover conductive layer; There is provided a light shield, light shield comprises a light shielding part and a GTG transmittance section, and the light transmittance of GTG transmittance section is cumulative toward the direction away from light shielding part from light shielding part, and GTG transmittance section defines the profile of a perforate; Light therethrough light shield is used to irradiate negative dielectric material, to define the profile of this perforate in this negative dielectric material; Developing manufacture process is carried out to this negative dielectric material, to form the negative dielectric layer that has perforate, wherein a part for conductive layer is exposed in perforate, and perforate has a minimum diameter, a top internal diameter and a bottom inner diameter, minimum diameter is between bottom inner diameter and top internal diameter, the region of the corresponding light shielding part in region of the minimum diameter of perforate, and the common region of the corresponding light shielding part in the region of the bottom inner diameter of perforate and GTG transmittance section; And, form an electrical contact in perforate.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate appended accompanying drawing, be described in detail below:
Accompanying drawing explanation
Fig. 1 illustrates the cutaway view of the semiconductor package part according to one embodiment of the invention.
Fig. 2 illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.
Fig. 3 illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.
Fig. 4 illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.
Fig. 5 A to 5E illustrates the process drawing of the semiconductor package part of Fig. 1.
Fig. 6 illustrates the process drawing of the semiconductor package part of Fig. 3.
Fig. 7 illustrates the light transmittance curve figure of the light shield according to another embodiment of the present invention.
[main element symbol description]
100,200,300,400: semiconductor package part
10: light shield
11: light shielding part
12: GTG transmittance section
110: chip
110u: active surface
120: conductive layer
130: negative dielectric layer
130 ': negative dielectric material
130a: perforate
130a1: opening
130w: madial wall
130u: upper surface
131,331: perforate protuberance
131 ', 132 ': portion of material
132: engaging recessed part
140: electrical contact
141: holding section
142: protuberance
C1, C2: dotted line
Db': region
DL: lower inner diameter
Dm: minimum diameter
Dt: top internal diameter
Db: bottom inner diameter
H1, H2: outstanding length
L: light
S1: light transmittance curve
ST1, ST2: stress distribution
T 0: initial light transmission
X 0, X l: distance
Embodiment
Please refer to Fig. 1, it illustrates the cutaway view of the semiconductor package part according to one embodiment of the invention.Semiconductor package part 100 comprises chip 110, conductive layer 120, negative dielectric layer 130 and at least one electrical contact 140.
Chip 110 has active surface 110u, and conductive layer 120 is formed and is electrically connected at active surface 110u.Conductive layer 120 comprises at least one connection pad and/or at least one cabling.In one embodiment, conductive layer 120 can be rerouting line layer (Redistribution Layer, RDL), and it is that chip 110 after unification redistributes and formed after support plate (not illustrating) is upper.In another embodiment, conductive layer 120 also just can be formed on wafer (wafer) before chip unification.
Negative dielectric layer 130 is outermost layer structure or the outermost layer dielectric layer of semiconductor package part 100, and it covers conductive layer 120 and has at least one perforate 130a.Perforate 130a exposes a part for conductive layer 120, the conductive layer 120 that electrical contact 140 can be made to be electrically connected at expose.
Due to the minus photoresistance characteristic of negative dielectric layer 130, therefore the perforate 130a of the madial wall with curved surface profile can be formed.In the present embodiment, the madial wall 130w of perforate 130a gives prominence to toward the zone line of perforate 130a, and forms perforate protuberance 131.Look toward overlooking direction, perforate protuberance 131 is in closed ring.Engaging recessed part 132 is formed between perforate protuberance 131 and bottom inner diameter Db, the portion of material of electrical contact 140 blocks in engaging recessed part 132, electrical contact 140 can be avoided to depart from perforate 130a easily, and then avoid causing electrical contact 140 to rupture, promote reliability further.
Perforate 130a has minimum diameter Dm, top internal diameter Dt and bottom inner diameter Db.Minimum diameter Dm is between bottom inner diameter Db and top internal diameter Dt, and it is the minimum diameter of perforate protuberance 131.Bottom inner diameter Db refers to the internal diameter of the bottommost of perforate 130a, maybe can say it is the internal diameter in the region of exposing conductive layer 120 in perforate 130a.In the present embodiment, the internal diameter of perforate 130a from bottom inner diameter Db part toward the direction convergent of minimum diameter Dm part, and forms perforate protuberance 131, and it has an outstanding length H1.
In addition, in developing manufacture process or baking processing procedure, in negative dielectric layer 130, the Material shrinkage of the opening 130a1 of adjacent openings 130a sink, and makes the internal diameter of perforate 130a from minimum diameter Dm part toward the direction flaring of top internal diameter Dt part.Because the Material shrinkage of adjacent openings 130a1 sink in negative dielectric layer 130, make the enlarged areas of opening 130a1.Thus, in the processing procedure forming electrical contact 140, the opening 130a1 that the electrical contact 140 in flowable state expands by this easily enters in perforate 130a.In the present embodiment, top internal diameter Dt equals bottom inner diameter Db haply; In another embodiment, can, by the light transmittance curve S1 of design light shield 10 (Fig. 5 B or Fig. 7), top internal diameter Dt be made to be greater than or less than bottom inner diameter Db.
Electrical contact 140 is output or the input contact of semiconductor package part 100.Electrical contact 140 is such as soldered ball.In the manufacture craft of electrical contact 140, can adopt is such as plant the glomerate tin solder of playing skill art shape in perforate 130a, and then solidifies tin solder by back welding process (reflow), and forms electrical contact 140.In another embodiment, electrical contact 140 also can be conductive pole and projection.
Electrical contact 140 is electrically connected at conductive layer 120 by perforate 130a.Electrical contact 140 comprises holding section 141 and protuberance 142, and wherein holding section 141 is formed in perforate 130a, and protuberance 142 protrudes from perforate 130a.The portion of material of holding section 141 is sticked in engaging recessed part 132, makes electrical contact 140 be subject to restraining of the perforate protuberance 131 of negative dielectric layer 130, and is more firmly formed in perforate 130a.With regard to stress distribution, if omit perforate protuberance 131, then the maximum stress that electrical contact 140 bears distributes ST1 quite close to the contact-making surface between electrical contact 140 and conductive layer 120.Review the embodiment of the present invention, when electrical contact 140 is stressed (being such as that semiconductor package part 100 is located in another semiconductor package part, substrate or circuit boards with electrical contact 140), perforate protuberance 131 can share the stressed of electrical contact 140, the maximum stress distribution ST2 that electrical contact 140 is born toward the directional spreding of perforate protuberance 131, and then can reduce the stress of electrical contact 140 and the contact-making surface of conductive layer 120.So, the stressed rear easy destruction of electrical contact 140 can be avoided and the reliability of electrical contact 140 can be promoted.
Although the quantity of the electrical contact 140 of the semiconductor package part 100 of the present embodiment is for an explanation, so its quantity can also be two or more than two.
Please refer to Fig. 2, it illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.Semiconductor package part 200 comprises chip 110, conductive layer 120, negative dielectric layer 130 and electrical contact 140.Negative dielectric layer 130 has at least one perforate 130a, perforate 130a exposed portion conductive layer 120.
The madial wall 130w of perforate 130a gives prominence to toward the zone line of perforate 130a, and forms perforate protuberance 131.Compared to Fig. 1, the outstanding length H2 of the perforate protuberance 131 of the present embodiment is shorter than the outstanding length H1 of the perforate protuberance 131 of Fig. 2, so can increase the volume of perforate 130a, to hold the material of more electrical contacts 140.The shorter perforate protuberance 131 of the present embodiment can complete by design light shield light transmittance, and this illustrates middle description in processing procedure after holding.
Please refer to Fig. 3, it illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.Semiconductor package part 300 comprises chip 110, conductive layer 120, negative dielectric layer 130 and electrical contact 140.Negative dielectric layer 130 has at least one perforate 130a, perforate 130a exposed portion conductive layer 120.
In the present embodiment, perforate 130a has lower inner diameter D l, it is between bottom inner diameter Db part and minimum diameter Dm part.The internal diameter of perforate 130a is from bottom inner diameter Db toward lower inner diameter D ldirection flaring, then from lower inner diameter D ltoward the direction convergent of minimum diameter Dm, so make the madial wall 130w of perforate 130a form two perforate protuberances 131 and 331, wherein form engaging recessed part 132 between perforate protuberance 131 and 331.The holding section 141 of electrical contact 140 is formed in engaging recessed part 132, and electrical contact 140 is more firmly formed in perforate 130a.
Please refer to Fig. 4, it illustrates the cutaway view of the semiconductor package part according to another embodiment of the present invention.Semiconductor package part 400 comprises chip 110, conductive layer 120, negative dielectric layer 130 and electrical contact 140.Negative dielectric layer 130 has at least one perforate 130a and exposes conductive layer 120.
In the present embodiment, the madial wall 130w of perforate 130a is a planar wall, and its direction toward the upper surface 130u of negative dielectric layer 130 extends.Perforate 130a has minimum diameter Dm, top internal diameter Dt and bottom inner diameter Db.The internal diameter of perforate 130a from bottom inner diameter Db part toward the direction convergent of minimum diameter Dm, and forms perforate protuberance 131.In developing process or baking process, in negative dielectric layer 130, the Material shrinkage of the opening 130a1 of adjacent openings 130a sink, and makes perforate 130a internal diameter from minimum diameter Dm part toward the direction flaring of top internal diameter Dt part.
In another embodiment, the madial wall 130w of perforate 130a can be the madial wall with Throwing thing line profile.But as long as the perforate 130a with perforate protuberance 131 utilizing negative dielectric layer 130 to be formed, its madial wall 130w can have any geometric profile, as by plane, curved surface or its combination the geometric profile that forms.
Please refer to Fig. 5 A to 5E, it illustrates the process drawing of the semiconductor package part of Fig. 1.
As shown in Figure 5A, provide chip 110, chip 110 has active surface 110u.Be formed with conductive layer 120 above the active surface 110u of chip 110, conductive layer 120 is electrically connected at active surface 110u.
Adopting is such as coating technique, forms negative dielectric material 130 ' and covers conductive layer 120.Negative dielectric material 130 ' is a light-sensitive material, and the portion of material of its irradiation can be retained on product, and another part material of non-irradiation is removed in developing manufacture process.Above-mentioned coating technique is such as printing (printing), spin coating (spinning) or spraying (spraying).
As shown in Figure 5 B, light shield 10 is provided.Light shield 10 is such as gray-level mask, the vicissitudinous light transmittance of its tool.Specifically, light shield 10 comprises light shielding part 11 and GTG transmittance section 12, and wherein GTG transmittance section 12 connects light shielding part 11.Using the center of the light shielding part 11 of light shield 10 as starting point (x=0), x is between-X 0to X 0part be defined as the light shielding part 11 of light shield 10, and x is between X 0to X lpart be defined as the GTG transmittance section 12 of light shield 10.The profile of light transmittance change definable perforate 130a (5C figure) of GTG transmittance section 12.
The light transmittance of at least two local of GTG transmittance section 12 is different.Such as, the light transmittance of the GTG transmittance section 12 of the present embodiment is cumulative toward the direction away from light shielding part 11 from light shielding part 11, and the right embodiment of the present invention is not limit by this.In the present embodiment, initial light transmission T 0(x=X 0place) about 40%, and it is larger away from the light transmittance of light shielding part 11 GTG transmittance sections 12 to heal, until x=X lpart, its light transmittance is 100%.In another embodiment, initial light transmission T 0can 40% be less than or greater than.In addition, x is between+X lwith-X lbetween the region Db ' combination zone of GTG transmittance section 12 (light shielding part 11 with) define the scope of the bottom inner diameter Db (Fig. 5 D) of perforate 130a.That is, by designing the size of the region Db ' of light shield 10, the size of the bottom inner diameter Db defining perforate 130a is gone.
In the present embodiment, the center of the relative light shielding part 11 of light transmittance curve S1 of the GTG transmittance section 12 of light shield 10 is symmetrical, so makes the center of the relative perforate 130a of the medial side wall profiles of the perforate 130a formed according to this haply symmetrically.So this is not used to limit the embodiment of the present invention, in another embodiment, the light transmittance curve S1 of GTG transmittance section 12 is asymmetric relative to the center of light shielding part 11, namely, the two GTG transmittance sections 12 being positioned at light shielding part 11 2 side have different light transmittance curve S1, so, the medial side wall profiles of the perforate 130a formed according to this is also asymmetric relative to the center of perforate 130a.
As shown in Figure 5 C, negative dielectric material 130 ' is irradiated with light L through light shield 10.As shown in the dotted line C1 of Fig. 5 C, the portion of material 131 ' of negative dielectric material 130 ' is subject to light L and irradiates, and another part material 132 ' (region of dotted line inside) is not subject to light L irradiates, the portion of material 132 ' not wherein being subject to light L irradiation can be removed in follow-up developing manufacture process, and the portion of material 131 ' being subject to light L irradiation then retains in developing manufacture process.In addition, the region that the light transmittance of GTG transmittance section 12 is larger, can allow stronger light pass through, and be irradiated to the material of more or darker negative dielectric material 130 '.
As shown in Figure 5 D, can adopt is such as developing manufacture process, remove the portion of material 132 ' (Fig. 5 C) not being subject to light irradiation of negative dielectric material 130 ', to form negative dielectric layer 130, wherein removed portion of material 132 ' part forms perforate 130a.In developing manufacture process, in negative dielectric material 130 ', the upper surface 130u of the opening 130a1 of adjacent openings 130a can sink because of shrinking, and thus causes the top internal diameter Dt ' of the opening 130a1 of perforate 130a to expand.Thus, in the processing procedure forming electrical contact 140, the opening 130a1 that the electrical contact 140 in flowable state expands by this easily enters in perforate 130a.
As shown in fig. 5e, baking negative dielectric layer 130, to solidify negative dielectric layer 130.In baking processing procedure, the material of the opening 130a1 of the adjacent openings 130a of negative dielectric layer 130 can shrink once again, in negative dielectric material 130 ', the upper surface 130u of the opening 130a1 of adjacent openings 130a can sink because of shrinking once again, and then causes the opening 130a1 of perforate 130a again to expand.Such as, be retracted to the madial wall 130w of the perforate 130a of solid line from dotted line C2, and top internal diameter Dt ' (figure) is extended to Dt.
Then, electrical contact 140 can be formed in perforate 130a.
The manufacture method of the semiconductor package part 200 of Fig. 2 is similar to the manufacture method of semiconductor package part 100, unlike, the initial light transmission T of the light shield 10 that the perforate 130a forming semiconductor package part 200 adopts 0(x=L 0place) than the initial light transmission T forming the light shield 10 that the perforate 130a of semiconductor package part 100 adopts 0height, therefore can form shorter perforate protuberance 131.Say further, can by design initial light transmission T 0value form the perforate protuberance 131 of different outstanding length.In addition, by the light transmittance distribution curve of design light shield 10, the madial wall 130w of perforate 130a can be made to form different geometric profile.
Please refer to Fig. 6, it illustrates the process drawing of the semiconductor package part of Fig. 3.In the present embodiment, conductive layer 120 scope is greater than the scope (x=0 ~ X of the GTG transmittance section 12 of light shield 10 lx is illustrated in Fig. 5 B), make the negative dielectric material 130 ' that the light L being irradiated to conductive layer 120 is irradiated to after being reflected by conductive layer 120, and then the negative dielectric material by reverberation is irradiated to is remained after developing manufacture process, and form perforate protuberance 331 (Fig. 3).
Please refer to Fig. 7, it illustrates the light transmittance curve figure of the light shield according to another embodiment of the present invention.The light transmittance curve S1 of light shield 10 can by straight line, curve or its formed, to form the perforate 130a of the madial wall 130w with corresponding profile, as the perforate 130a of above-mentioned semiconductor package part 300 and 400.
In sum, although the present invention with preferred embodiment disclose as above, so itself and be not used to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when doing various change and retouching.Therefore, protection scope of the present invention is when being as the criterion depending on the accompanying claim person of defining.

Claims (11)

1. a semiconductor package part, comprising:
One chip, has an active surface;
One conductive layer, is electrically connected at this active surface;
One negative dielectric layer, cover this conductive layer and have a perforate, a part for this conductive layer is exposed in this perforate, and this perforate has a minimum diameter, a top internal diameter and a bottom inner diameter, and this minimum diameter is between this bottom inner diameter and this top internal diameter; And
One electrical contact, is formed in this perforate.
2. semiconductor package part as claimed in claim 1, it is characterized in that, the internal diameter of this perforate is from this bottom inner diameter part toward the direction convergent of this minimum diameter part.
3. semiconductor package part as claimed in claim 1, it is characterized in that, the internal diameter of this perforate is from this minimum diameter part toward the direction flaring of this top internal diameter part.
4. semiconductor package part as claimed in claim 1, it is characterized in that, this perforate has a lower inner diameter, this lower inner diameter part between this bottom inner diameter part and this minimum diameter part, the direction flaring of internal diameter from this bottom inner diameter toward this lower inner diameter of this perforate and the direction convergent from this lower inner diameter toward this minimum diameter.
5. semiconductor package part as claimed in claim 1, it is characterized in that, this top internal diameter is greater than this bottom inner diameter.
6. semiconductor package part as claimed in claim 1, it is characterized in that, the madial wall of this perforate is a planar wall.
7. semiconductor package part as claimed in claim 1, it is characterized in that, the madial wall of this perforate is a curved wall.
8. a manufacture method for semiconductor package part, comprising:
There is provided a chip, this chip has an active surface, and is formed with a conductive layer above this active surface of this chip, and this conductive layer is electrically connected at this active surface;
Form a negative dielectric material and cover this conductive layer;
There is provided a light shield, this light shield comprises a light shielding part and a GTG transmittance section, and the light transmittance of this GTG transmittance section is cumulative toward the direction away from this light shielding part from this light shielding part, and this GTG transmittance section defines the profile of a perforate;
This light shield of light therethrough is used to irradiate this negative dielectric material, to define the profile of this perforate in this negative dielectric material;
Developing manufacture process is carried out to this negative dielectric material, to form the negative dielectric layer that has this perforate, wherein a part for this conductive layer is exposed in this perforate, and this perforate has a minimum diameter, a top internal diameter and a bottom inner diameter, this minimum diameter is between this bottom inner diameter and this top internal diameter, the region of this minimum diameter of this perforate is to should the region of light shielding part, and the region of this bottom inner diameter of this perforate is to should the combination zone of light shielding part and this GTG transmittance section; And
Form an electrical contact in this perforate.
9. manufacture method as claimed in claim 8, it is characterized in that, the scope of this conductive layer is greater than the scope of this GTG transmittance section; Irradiate in the step of this negative dielectric material in this light shield of use light therethrough, this negative dielectric material that this light being irradiated to this conductive layer is irradiated to after reflection, make in carrying out in the step of developing manufacture process to this negative dielectric material, this perforate forms a lower inner diameter, this lower inner diameter part between this bottom inner diameter part and this minimum diameter part, the direction flaring of internal diameter from this bottom inner diameter toward this lower inner diameter of this perforate and the direction convergent from this lower inner diameter toward this minimum diameter.
10. manufacture method as claimed in claim 8, is characterized in that, more comprise:
Toast this negative dielectric layer, and expand this top internal diameter.
11. manufacture methods as claimed in claim 8, is characterized in that, the light transmittance curve of this light shield by straight line, curve or its formed.
CN201310513715.2A 2013-10-25 2013-10-25 Semiconductor package assembly and a manufacturing method thereof Active CN104576576B (en)

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