TWI620300B - Chip package structure and manufacturing method thereof - Google Patents

Abstract

A chip package structure and a method of fabricating the same. The chip package structure includes a wiring board, a wafer, a housing, an antenna pattern, a wire pattern, and a shielding layer. The wafer is disposed on the circuit board. The housing is disposed on the circuit board and covers the wafer, wherein the housing includes a top cover and a sidewall, and the housing contains catalyst particles. The antenna pattern is disposed in an outer surface of the top cover. The wire pattern is disposed in an outer surface of the sidewall and electrically connected to the antenna pattern and the circuit board. The shielding layer is disposed at least in an inner surface of the top cover.

Description

Chip package structure and method of manufacturing same

The present invention relates to a chip package structure, and more particularly to a chip package structure having a case including an antenna pattern and a mask layer.

For the current chip package structure having an antenna layer, in the manufacturing process, the antenna layer and the wafer are usually disposed on the circuit board at the same time, and then the antenna layer and the wafer are covered by a molding compound. .

However, in the above-described chip package structure, since the antenna layer and the wafer are simultaneously disposed on the circuit board, a large-area circuit board is required to satisfy the structural design requirement. As a result, the product having the chip package structure has a large size, and thus it is not easy to meet the demand for miniaturization and weight reduction of electronic products.

The present invention provides a chip package structure having a housing including an antenna pattern and a shielding layer.

The present invention provides a method of fabricating a chip package structure that covers a housing including an antenna pattern and a shielding layer on a wafer.

The chip package structure of the present invention includes a wiring board, a wafer, a housing, an antenna pattern, a wire pattern, and a shielding layer. The wafer is disposed on the circuit board. The housing is disposed on the circuit board and covers the wafer, wherein the housing includes a top cover and a sidewall, and the housing contains catalyst particles. The antenna pattern is disposed in an outer surface of the top cover. The wire pattern is disposed in an outer surface of the sidewall and electrically connected to the antenna pattern and the circuit board. The shielding layer is disposed at least in an inner surface of the top cover.

In an embodiment of the wafer package structure of the present invention, the shielding layer is disposed, for example, in the entire inner surface of the housing.

In an embodiment of the chip package structure of the present invention, the thickness of the shielding layer is, for example, not more than 30 μm.

In an embodiment of the chip package structure of the present invention, an encapsulant is further included. The encapsulant encapsulates the wafer.

In an embodiment of the wafer package structure of the present invention, the catalyst particles are, for example, metal particles, graphite particles, or a combination thereof.

A method of fabricating a chip package structure of the present invention includes the steps of: forming a case, the case including a top cover and a sidewall, wherein the case contains catalyst particles; and forming an antenna pattern in an outer surface of the top cover a trench, a conductive pattern trench is formed in an outer surface of the sidewall, and a shielding pattern trench is formed in at least an inner surface of the top cover, and simultaneously exposing the catalyst particle; and the antenna pattern trench, Forming a conductive layer in the wire pattern trench and the shielding pattern trench, wherein an antenna pattern is formed in the antenna pattern trench, and a wire pattern is formed in the wire pattern trench, wherein the shielding pattern trench is formed Forming a shielding layer; disposing the wafer on the circuit board; disposing the housing on the circuit board and covering the wafer, and electrically connecting the conductor pattern to the antenna pattern and the circuit board.

In an embodiment of the method of fabricating a chip package structure of the present invention, the method of forming the case is, for example, an injection molding process.

In an embodiment of the method of fabricating a chip package structure of the present invention, the method of forming the antenna pattern trench, the wire pattern trench, and the shielding pattern trench is, for example, performing a laser engraving process.

In an embodiment of the method of fabricating a chip package structure of the present invention, the method of forming the conductive layer is, for example, performing a chemical deposition process or an electroplating process.

In an embodiment of the method of fabricating a chip package structure of the present invention, the method of disposing the case on the circuit board is, for example, a surface mounting technology (SMT) process.

In an embodiment of the method of fabricating a chip package structure of the present invention, the mask pattern trench is formed, for example, in the entire inner surface of the housing.

In an embodiment of the method of fabricating the chip package structure of the present invention, the thickness of the shielding layer is, for example, not more than 30 μm.

In an embodiment of the method of fabricating a chip package structure of the present invention, after the wafer is disposed on the circuit board and before the housing is disposed on the circuit board, the cover is further formed The encapsulant of the wafer.

Based on the above, in the present invention, the casing is formed using a material containing catalyst particles, and the antenna particles and the shielding layer are formed in the casing by using the catalyst particles as a seed layer, so that the process steps can be simplified and formed. The antenna pattern and the shielding layer may have a relatively thin thickness. In addition, in the present invention, both the antenna pattern and the shielding layer are disposed above the wafer, so that it is not necessary to occupy an additional area of the wiring board, so that the formed chip package structure can meet the demand for miniaturization.

The above described features and advantages of the invention will be apparent from the following description.

In the following embodiments, after the antenna pattern and the shielding layer are formed on the casing, the casing is joined to the wiring board on which the wafer is placed. The manufacturing procedure of the casing and the procedure of arranging the wafer on the wiring board can be carried out separately, and the present invention does not limit the order of the two.

1A to 1E are schematic cross-sectional views showing a manufacturing process of a chip package structure according to an embodiment of the present invention. First, please form the housing 100 as shown in FIG. 1A. The housing 100 is used to cover the wafers disposed on the circuit board. The material of the casing 100 is, for example, an insulating material such as plastic. Further, the casing 100 contains catalyst particles 102. The catalyst particles 102 are, for example, metal particles, graphite particles, or a combination thereof. The method of forming the casing 100 is, for example, an injection molding process using an insulating material in which the catalyst particles 102 are mixed. Therefore, the catalyst particles 102 can be uniformly dispersed in the casing 100. The housing 100 includes a top cover 100a and a side wall 100b. In the present embodiment, the casing 100 is a rectangular casing (as shown in FIGS. 2A and 2B), and thus has four side walls 100b connected to the top cover 100a, but the present invention is not limited thereto. In other embodiments, the housing 100 may also be a housing having other shapes, depending on actual needs.

Then, referring to FIG. 1B, an antenna pattern trench 104 is formed in the outer surface of the top cover 100a, a wire pattern trench 106 is formed in the outer surface of the sidewall 100b, and a mask pattern trench 108 is formed in the inner surface of the top cover 100a. Wherein the wire pattern trench 106 is connected to the antenna pattern trench 104. Herein, the "inner surface" indicates a surface adjacent to the space covered by the casing 100, and the "outer surface" is the surface of the casing 100 opposite to the "inner surface". The method of forming the antenna pattern groove 104, the wire pattern groove 106, and the shielding pattern groove 108 is, for example, a laser engraving process for the housing 100. During engraving of the housing 100 with a laser, the laser can remove portions of the housing 100. At this time, in the engraved area, the catalyst particles 102 contained in the casing 100 are exposed and absorb the energy of the laser to be "activated". As shown in FIG. 1B, at the sidewalls and bottom of the antenna pattern trench 104, the wire pattern trench 106, and the mask pattern trench 108, the catalyst particles 102 are exposed.

The antenna pattern trenches 104, the line pattern trenches 106 and the masking pattern trenches 108 are regions in which the antenna pattern, the conductor pattern and the shielding layer are subsequently formed, and the exposed catalyst particles 102 can be formed as an antenna pattern, a conductor pattern and The seed layer of the masking layer. Therefore, the depth of the trench formed by the laser engraving can be controlled according to the desired antenna pattern, the wire pattern, and the thickness of the shielding layer. In the present embodiment, the depth of the antenna pattern trench 104, the line pattern trench 106, and the mask pattern trench 108 does not exceed 30 μm. That is, the thickness of the antenna pattern, the wiring pattern, and the shielding layer which are subsequently formed in the antenna pattern trench 104, the line pattern trench 106, and the mask pattern trench 108 does not exceed 30 μm. In this thickness range, the antenna pattern, the wire pattern and the shielding layer can have the required electrical properties without wasting excessive material due to the excessive thickness.

Next, referring to FIG. 1C, a conductive layer is formed in the antenna pattern trench 104, the wire pattern trench 106, and the shielding pattern trench 108. The method of forming the conductive layer is, for example, a chemical deposition process or an electroplating process using the activated catalyst particles 102 (exposed to the trench) as a seed layer. The conductive layer formed in the antenna pattern trench 104 is used as the antenna pattern 110, and the conductive layer formed in the conductive pattern trench 106 is used as the conductive pattern 112, and the conductive layer formed in the shielding pattern trench 108 is used as the shielding layer. 114. The wire pattern 112 is connected to the antenna pattern 110, so that the antenna pattern 110 can be electrically connected to other elements by the wire pattern 112. The shielding layer 114 is used to prevent the components covered by the housing 100 from being affected by electromagnetic effects from the antenna pattern 110 and other electromagnetic waves from the outside to prevent the electronic signal from being disturbed and causing signal loss.

In the present embodiment, the shape of the antenna pattern 110 is not limited by the one shown in FIG. 2A. In other embodiments, the antenna pattern 110 can be formed into any shape depending on actual needs. Further, in the present embodiment, the wire pattern 112 is formed only in one side wall 100b, but the present invention is not limited thereto. In other embodiments, the wire pattern 112 may also be formed in the plurality of sidewalls 100b to be connected to the antenna pattern 110. In addition, in the present embodiment, the shielding layer 114 is formed only in the inner surface of the top cover 100a, but the present invention is not limited thereto. In other embodiments, the shielding layer 114 may also be formed in the entire inner surface of the housing 100, that is, in the inner surface of the top cover 100a and the inner surface of all the side walls 100b to further improve the electromagnetic shielding of the shielding layer 114. The effect is shown in Figure 3.

Referring to FIG. 1D, the wafer 116 is disposed on the circuit board 118. In the present embodiment, the wafer 116 is connected to the pads 122 of the circuit board 118 via the wires 120 by wire bonding, so that the wafer 116 is electrically connected to the circuit board 118. In other embodiments, the wafer 116 can also be electrically connected to the circuit board 118 by means of a flip chip. In addition, solder balls 126 are formed on the pads 124 at the bottom of the wiring board 118. Solder balls 126 serve as contacts for connecting circuit board 118 to external components.

Thereafter, referring to FIG. 1E, the housing 100 is disposed on the circuit board 118, and the housing 100 is covered with the wafer 116 to complete the wafer package structure 10 of the present embodiment. The method of arranging the housing 100 on the wiring board 118 is, for example, a surface following technical process. After the housing 100 is disposed on the circuit board 118, the wire pattern 112 can be connected to the pads of the circuit board 118 to electrically connect the antenna pattern 110 to the circuit board 118. In the chip package structure 10, since the shielding layer 114 is located between the antenna pattern 110 and the wafer 116, the wafer 116 can be prevented from being affected by the electromagnetic effect from the antenna pattern 110 and other electromagnetic waves from the outside to prevent the electronic signal from being disturbed and causing the signal. loss.

In the present embodiment, after the wafer 116 is placed on the circuit board 118, the housing 100 can be directly disposed on the wiring board 118 without previously forming an encapsulant to cover the wafer 118. In other embodiments, after the wafer 116 is disposed on the circuit board 118, the encapsulant covering the wafer 116 may be formed on the circuit board 118, and then the housing 100 may be disposed on the circuit board 118.

In addition, in the present embodiment, the antenna pattern 110 and the shielding layer 114 are both located above the wafer 116, so that it is not necessary to additionally use other areas of the wiring board 118 to set the antenna pattern and the shielding layer. As such, the chip package structure 10 can be of a smaller size to meet the needs of miniaturization.

While the present invention has been described above with reference to the embodiments of the present invention, it is not intended to limit the present invention, and it is possible to make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧ Chip package structure
100‧‧‧shell
100a‧‧‧Top cover
100b‧‧‧ side wall
102‧‧‧catalyst particles
104‧‧‧Antenna pattern groove
106‧‧‧ wire pattern groove
108‧‧‧Shading pattern groove
110‧‧‧Antenna pattern
112‧‧‧Wire pattern
114‧‧‧Shielding layer
116‧‧‧ wafer
118‧‧‧PCB
120‧‧‧ wire
122, 124‧‧‧ pads
126‧‧‧ solder balls

1A-1E are schematic cross-sectional views showing a manufacturing process of a chip package structure according to an embodiment of the invention. 2A and 2B are perspective views of a housing in accordance with an embodiment of the present invention. 3 is a cross-sectional view of a housing in accordance with another embodiment of the present invention.

Claims (13)

A chip package structure comprising: a circuit board; a wafer disposed on the circuit board; a housing disposed on the circuit board and covering the wafer, wherein the housing includes a top cover and a side wall, and The housing contains catalytic particles; an antenna pattern disposed in an outer surface of the top cover; a wire pattern disposed in an outer surface of the sidewall, and electrically connecting the antenna pattern and the circuit board; And a shielding layer disposed at least in an inner surface of the top cover. The chip package structure of claim 1, wherein the shielding layer is disposed in an entire inner surface of the housing. The wafer package structure of claim 1, wherein the thickness of the shielding layer does not exceed 30 μm. The chip package structure of claim 1, further comprising an encapsulant that encapsulates the wafer. The wafer package structure of claim 1, wherein the catalyst particles comprise metal particles, graphite particles, or a combination thereof. A method of manufacturing a chip package structure, comprising: forming a case, the case comprising a top cover and a sidewall, wherein the case contains catalyst particles; forming an antenna pattern groove in an outer surface of the top cover, Forming a wire pattern groove in an outer surface of the sidewall and forming a shielding pattern groove in at least an inner surface of the top cover, and simultaneously exposing the catalyst particle; the antenna pattern groove, the wire Forming a conductive layer in the pattern trench and the shielding pattern trench, wherein an antenna pattern is formed in the antenna pattern trench, a wire pattern is formed in the wire pattern trench, and a shielding is formed in the shielding pattern trench a layer; a wafer is disposed on the circuit board; and the housing is disposed on the circuit board and covers the wafer, and the wire pattern is electrically connected to the antenna pattern and the circuit board. The method of manufacturing a chip package structure according to claim 6, wherein the method of forming the case comprises performing an injection molding process. The method of fabricating a chip package structure according to claim 6, wherein the method of forming the antenna pattern trench, the wire pattern trench, and the shielding pattern trench comprises performing a laser engraving process. The method of fabricating a chip package structure according to claim 6, wherein the method of forming the conductive layer comprises performing a chemical deposition process or an electroplating process. The method of fabricating a chip package structure according to claim 6, wherein the method of disposing the case on the circuit board comprises performing a surface subsequent technical process. The method of fabricating a chip package structure according to claim 6, wherein the shielding pattern groove is formed in an entire inner surface of the casing. The method of fabricating a chip package structure according to claim 6, wherein the thickness of the shielding layer does not exceed 30 μm. The method of manufacturing a chip package structure according to claim 6, wherein after the wafer is disposed on the circuit board and before the housing is disposed on the circuit board, the method further includes forming Covering the encapsulant of the wafer.