KR20020036039A - Semiconductor package and method for manufacturing the same - Google Patents
Semiconductor package and method for manufacturing the same Download PDFInfo
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- KR20020036039A KR20020036039A KR1020000065894A KR20000065894A KR20020036039A KR 20020036039 A KR20020036039 A KR 20020036039A KR 1020000065894 A KR1020000065894 A KR 1020000065894A KR 20000065894 A KR20000065894 A KR 20000065894A KR 20020036039 A KR20020036039 A KR 20020036039A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
Description
본 발명은 반도체 패키지 및 그 제조방법에 관한 것으로서, 더욱 상세하게는 전자파의 차폐효과를 얻을 수 있도록 한 새로운 구조의 반도체 패키지 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package having a new structure and a method of manufacturing the same, which are capable of obtaining electromagnetic shielding effects.
통상적으로 반도체 패키지는 회로가 고집적화된 반도체 칩으로부터 전기적 입출력 신호를 외부로 용이하게 인출시키기 위하여 제조된 것으로서, 리드프레임, 인쇄회로기판, 회로필름등의 부재를 이용하여 다양한 구조로 제조되고 있다.BACKGROUND ART Conventionally, semiconductor packages are manufactured to easily draw electrical input / output signals to the outside from a highly integrated semiconductor chip, and are manufactured in various structures using members such as lead frames, printed circuit boards, and circuit films.
각종 전자기기의 마더보드에는 상기와 같은 다수개의 반도체 패키지 뿐만아니라, 각종 신호 교환용 기기들이 한꺼번에 설치되는 바, 이러한 반도체 패키지와 기기들은 전기적인 작동중에 전자파를 발생하는 것을 알려져 있다.As well as a plurality of semiconductor packages as described above, various signal exchange devices are installed on the motherboard of various electronic devices, and these semiconductor packages and devices are known to generate electromagnetic waves during electrical operation.
통상 전계(電界)와 자계(磁界)의 합성파를 전자파라고 정의하는데, 즉 도체를 통하여 전류가 흐르게 되면, 이 전류에 의하여 형성되는 전계와 자계를 합쳐서 전자파라고 부른다.Normally, a synthesized wave of an electric field and a magnetic field is defined as an electromagnetic wave. That is, when a current flows through a conductor, the electric field formed by this current and the magnetic field are called an electromagnetic wave.
이러한 전자파들은 인체에 매우 유해한 것으로 밝혀지고 있고, 특히 소형 핸드폰, 카폰등의 무선통신기기는 인체에 직접 접촉시켜 사용함에 따라, 더욱 유해한 것을 밝혀지고 있다.These electromagnetic waves have been found to be very harmful to the human body, and in particular, wireless communication devices such as small cell phones, car phones, etc. are found to be more harmful as used in direct contact with the human body.
또한, 각종 전자기기의 마더보드에 좁은 간격으로 실장된 반도체 패키지와 기기들로부터 전자파가 발산되면, 그 주변에 실장된 반도체 패키지에까지 직간접으로 영향이 미치게 되어, 칩 회로에 손상을 입히는 것으로 밝혀졌다.In addition, when electromagnetic waves are emitted from semiconductor packages and devices mounted on the motherboard of various electronic devices at narrow intervals, the semiconductor packages mounted on the surroundings are directly or indirectly affected, thereby damaging the chip circuit.
따라서, 본 발명은 상기와 같은 점을 감안하여 반도체 패키지의 표면을 전기적으로 그라운딩시켜 마더보드에 실장된 패키지간의 전자파 차폐효과를 얻을 수 있도록 한 새로운 구조의 반도체 패키지 및 그 제조방법을 제공하는데 그 목적이 있다.Accordingly, in view of the above, the present invention provides a semiconductor package having a new structure and a method of manufacturing the same, in which the surface of the semiconductor package is electrically grounded to obtain an electromagnetic shielding effect between the packages mounted on the motherboard. There is this.
도 1은 본 발명에 따른 반도체 패키지 및 그 제조방법을 나타내는 단면도,1 is a cross-sectional view showing a semiconductor package and a method of manufacturing the same according to the present invention;
도 2는 본 발명에 따른 반도체 패키지의 싱귤레이션 공정이 끝난 상태를 나타내는 단면도,2 is a cross-sectional view showing a state in which a singulation process of a semiconductor package according to the present invention is finished;
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10 : 전도성의 차폐층12 : 인쇄회로기판10 conductive shielding layer 12 printed circuit board
14 : 와이어 본딩용 전도성패턴16 : 반도체 칩14 conductive pattern for wire bonding 16 semiconductor chip
18 : 전도성물질20 : 몰딩수지18: conductive material 20: molding resin
22 : 와이어24 : 인출단자22: wire 24: withdrawal terminal
26 : 수지층28 : 커버코트26: resin layer 28: cover coat
30 : 홀32 : 볼랜드용 전도성패턴30: hole 32: conductive pattern for borland
34 : 전자파 접지용 전도성패턴100 : 반도체 패키지34: conductive pattern for electromagnetic ground 100: semiconductor package
상기한 목적을 달성하기 위한 본 발명의 반도체 패키지는:The semiconductor package of the present invention for achieving the above object is:
반도체 칩이 실장되는 인쇄회로기판과, 반도체 칩의 본딩패드과 인쇄회로기판의 와이어 본딩용 전도성패턴간에 연결된 와이어와, 상기 반도체 칩과 와이어와 전도성패턴등을 몰딩하고 수지와, 상기 인쇄회로기판의 저면으로 노출된 볼랜드용 전도성패턴에 부착된 인출단자를 포함하는 반도체 패키지에 있어서,A printed circuit board on which the semiconductor chip is mounted, a wire connected between a bonding pad of the semiconductor chip and a conductive pattern for wire bonding of the printed circuit board, molded the semiconductor chip, the wire and the conductive pattern, and a resin; In the semiconductor package comprising a lead terminal attached to the conductive pattern for the borland exposed to,
상기 인쇄회로기판의 수지층 상면 테두리 부분에 위치한 전도성패턴을 노출시켜 전기적 접속 가능한 전도성물질로 접촉시키고, 상기 반도체 패키지의 몰딩면에 걸쳐 상기 전도성물질과 접촉되게 전도성의 차폐층을 도포한 것을 특징으로 한다.The conductive pattern located on the upper edge of the resin layer of the printed circuit board is exposed to contact with an electrically connectable conductive material, and a conductive shielding layer is coated to contact the conductive material over the molding surface of the semiconductor package. do.
상기한 목적을 달성하기 위한 본 발명의 반도체 패키지 제조방법은:The semiconductor package manufacturing method of the present invention for achieving the above object is:
다수개의 반도체 패키지 영역이 스트립 형태로 형성되어 있는 인쇄회로기판을 제공하는 단계와; 인쇄회로기판의 칩탑재영역에 반도체 칩을 부착하는 단계와; 상기 반도체 칩의 본딩패드와 상기 인쇄회로기판의 와이어 본딩용 전도성패턴간을 와이어로 본딩하는 단계와; 상기 다수개의 반도체 패키지 영역을 수지로 한꺼번에 몰딩하는 단계와; 상기 인쇄회로기판의 저면으로 노출된 볼랜드용 전도성패턴에 인출단자를 부착하는 단계로 이루어진 반도체 패키지 제조방법에 있어서,Providing a printed circuit board having a plurality of semiconductor package regions formed in a strip shape; Attaching a semiconductor chip to a chip mounting region of a printed circuit board; Bonding a wire between a bonding pad of the semiconductor chip and a conductive pattern for wire bonding of the printed circuit board; Molding the plurality of semiconductor package regions with resin at one time; In the semiconductor package manufacturing method comprising the step of attaching the lead terminal to the conductive pattern for the ball land exposed to the bottom surface of the printed circuit board,
상기 반도체 패키지 영역라인을 따라 몰딩된 수지를 관통하는 홀을 가공하되, 상기 인쇄회로기판의 상면 테두리면에 위치된 전도성패턴이 노출되도록 홀을 가공하는 단계와; 상기 홀을 통하여 노출된 전도성패턴과 전기적으로 접속 가능하도록 홀에 전도성 물질을 채우는 단계와; 상기 홀에 채워진 전도성물질의 상면과 일체로 접촉되면서 상기 각 반도체 패키지 영역의 전체 몰딩면에 걸쳐 전도성의 차폐층을 형성하는 단계와; 상기 홀에 채워진 전도성물질을 종방향으로 이등분시키며 낱개의 반도체 패키지로 소잉하는 단계를 더 포함하는 것을 특징으로 한다.Processing holes penetrating the resin molded along the semiconductor package region line, and processing the holes to expose the conductive patterns on the upper edge of the printed circuit board; Filling a conductive material in the hole to be electrically connected to the conductive pattern exposed through the hole; Forming a conductive shielding layer over the entire molding surface of each semiconductor package region while integrally contacting the upper surface of the conductive material filled in the hole; And dividing the conductive material filled in the hole in the longitudinal direction and sawing into a single semiconductor package.
여기서 본 발명의 실시예를 첨부한 도면에 의거하여 더욱 상세하게 설명하면 다음과 같다.Hereinafter, the embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도 1은 본 발명에 따른 반도체 패키지 및 그 제조방법을 나타내는 단면도로서, 상기 인쇄회로기판(12)은 다수개의 반도체 패키지 영역이 스트립 또는 매트릭스 형태로 배열된 것을 사용한다.1 is a cross-sectional view illustrating a semiconductor package and a method of manufacturing the same according to the present invention, wherein the printed circuit board 12 uses a plurality of semiconductor package regions arranged in a strip or matrix form.
상기 인쇄회로기판(12)의 구조를 살펴보면, 베이스층으로서 가운데층을 이루는 수지층(26)과, 상기 수지층(26)의 상하면에 에칭 처리된 전도성패턴과, 이 전도성패턴중 와이어 본딩용 전도성패턴(14)과 볼랜드용 전도성패턴(32)을 외부로 노출시키며 수지층(26)의 상하면에 도포된 커버코트(28)로 구성되어 있다.Looking at the structure of the printed circuit board 12, a resin layer 26 forming a middle layer as a base layer, a conductive pattern etched on the upper and lower surfaces of the resin layer 26, and conductive for wire bonding among the conductive patterns The cover 14 is formed on the upper and lower surfaces of the resin layer 26 while exposing the pattern 14 and the conductive pattern 32 for borland to the outside.
특히, 상기 수지층(26) 상면의 와이어 본딩용 전도성패턴(14)과 저면의 볼랜드용 전도성패턴(32)은 수지층(26)을 관통하며 그 내면이 전도성물질로 코팅된 비아홀(36)에 의하여 전기적 접속 가능하게 연결되어 있다.In particular, the conductive pattern 14 for wire bonding on the upper surface of the resin layer 26 and the conductive pattern 32 for borland on the bottom surface of the via layer 36 penetrate the resin layer 26 and have an inner surface coated with a conductive material. Are electrically connected.
상기와 같은 구조로 이루어진 인쇄회로기판을 사용하여 본 발명의 반도체 패키지 제조방법을 순서대로 설명하면 다음과 같다.Referring to the method of manufacturing a semiconductor package of the present invention using a printed circuit board having the above structure in order as follows.
먼저, 상기 인쇄회로기판(12)의 각 칩탑재영역에 반도체 칩(16)을 접착수단으로 부착하는 공정을 진행한 다음, 상기 반도체 칩(16)의 본딩패드와 인쇄회로기판(12)의 와이어 본딩용 전도성패턴(14)간을 와이어(22)로 본딩하는 공정을 진행시키게 된다.First, a process of attaching the semiconductor chip 16 to each chip mounting area of the printed circuit board 12 by an adhesive means is performed, and then a bonding pad of the semiconductor chip 16 and a wire of the printed circuit board 12 are carried out. The bonding between the conductive patterns 14 for bonding with the wires 22 is performed.
다음 공정으로, 상기 반도체 칩(16)과 와이어(22)와 와이어 본딩용 전도성패턴(14)등을 수지(20)로 몰딩하는 공정을 진행하게 되는데, 상기 인쇄회로기판(12)의 전체 반도체 패키지 영역을 한꺼번에 몰딩하게 된다.Next, the process of molding the semiconductor chip 16, the wire 22, the conductive pattern 14 for wire bonding, and the like with the resin 20 is performed, and the entire semiconductor package of the printed circuit board 12 is performed. It will mold the regions at once.
이어서, 상기 인쇄회로기판(12)의 저면으로 일정한 간격을 유지하며 노출되어 있는 볼랜드용 전도성패턴(32)에 솔더볼과 같은 인출단자(24)를 부착시키게 된다.Subsequently, the lead terminals 24, such as solder balls, are attached to the conductive patterns 32 for the borland exposed to the bottom surface of the printed circuit board 12 while maintaining a predetermined interval.
여기서, 각 반도체 패키지 영역 라인에 해당되는 몰딩수지(20)면에 홀(30)을 가공하는 공정을 진행하게 되는데, 상기 인쇄회로기판(12) 상면 테두리 부위에 위치한 전도성패턴이 노출되는 깊이로 가공하게 된다.Here, the process of processing the hole 30 on the molding resin 20 surface corresponding to each semiconductor package region line is processed, the process to a depth to expose the conductive pattern located on the upper edge portion of the printed circuit board 12. Done.
이때, 상기 가공된 홀(30)을 통하여 노출된 전도성패턴은 전자파 접지용 전도성패턴(34)으로 정해진다.At this time, the conductive pattern exposed through the processed hole 30 is determined as the conductive pattern 34 for electromagnetic grounding.
이어서, 상기 홀(30)에 전도성물질(18)을 채우는 공정을 진행시키는 바, 상기 몰딩수지(20)의 외곽면과 평행을 이루도록 채운다.Subsequently, a process of filling the hole 30 with the conductive material 18 is performed to fill the hole 30 in parallel with the outer surface of the molding resin 20.
따라서, 상기 홀(30)을 통하여 노출된 인쇄회로기판(10)의 전자파 접지용 전도성패턴(34)과 상기 전도성물질(18)이 서로 전기적으로 접속 가능하게 된다.Therefore, the conductive pattern 34 for electromagnetic grounding of the printed circuit board 10 exposed through the hole 30 and the conductive material 18 may be electrically connected to each other.
다음으로, 상기 전도성물질(18)의 상면과 접촉시키면서 상기 전체 반도체 패키지 몰딩면에 걸쳐 전도성의 차폐층(10)을 도포시킨다.Next, the conductive shielding layer 10 is coated over the entire semiconductor package molding surface while being in contact with the top surface of the conductive material 18.
한편, 상기 홀(30)에 채워진 전도성물질(18)과, 상기 전도성의 차폐층(10)은 서로 같은 재질을 사용함이 바람직하고, 서로 전기적인 접속이 이루어진다면 서로 다른 재질을 사용하여도 무방하다.On the other hand, the conductive material 18 filled in the hole 30 and the conductive shielding layer 10 is preferably used the same material, and if the electrical connection is made to each other may be different materials. .
마지막으로, 상기 각 반도체 패키지 영역라인을 따라 상기 전도성물질(18)을 종방향으로 이등분시키며 낱개의 반도체 패키지로 싱귤레이션하는 단계가 진행되어, 첨부한 도 2에 도시한 바와 같은 본 발명의 반도체 패키지(100)로 제조된다.Lastly, the conductive material 18 is bisected longitudinally along the respective semiconductor package region lines and singulated into a single semiconductor package, thereby providing a semiconductor package as shown in FIG. 2. It is made of 100.
따라서, 마더보드에 실장된 주변의 반도체 패키지와 각종 기기들로부터 발산되는 전자파는 상기 전도성의 차폐층(10)과, 전도성물질(18)과, 이 전도성물질(18)과 닿아 있는 전자파 접지용 전도성패턴(34)과, 비아홀(30)과, 볼랜드용 전도성패턴(32)과, 인출단자(24)를 통하여 빠져나가 마더보드상에 접지되어 제거된다.Therefore, electromagnetic waves emitted from the surrounding semiconductor package and various devices mounted on the motherboard are electrically conductive for grounding the electromagnetic wave that is in contact with the conductive shielding layer 10, the conductive material 18, and the conductive material 18. Through the pattern 34, the via hole 30, the borland conductive pattern 32, and the lead terminal 24, the pattern 34 is removed and grounded on the motherboard.
이상에서 본 바와 같이, 본 발명에 따른 반도체 패키지 및 그 제조방법에 의하면, 반도체 패키지의 일면에 전도성의 차폐층을 설치하여, 마더보드에 실장된 주변의 반도체 패키지 및 기기들로부터 발생되는 전자파를 용이하게 그라운드 처리하여 제거할 수 있는 효과가 있다.As described above, according to the semiconductor package and the method of manufacturing the same according to the present invention, by providing a conductive shielding layer on one surface of the semiconductor package, electromagnetic waves generated from the surrounding semiconductor package and devices mounted on the motherboard easily This can be removed by grounding.
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