KR101247343B1 - Method for manufacturing a semiconductor package having a anti- electromagnetic wave means - Google Patents

Method for manufacturing a semiconductor package having a anti- electromagnetic wave means Download PDF

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KR101247343B1
KR101247343B1 KR1020110100356A KR20110100356A KR101247343B1 KR 101247343 B1 KR101247343 B1 KR 101247343B1 KR 1020110100356 A KR1020110100356 A KR 1020110100356A KR 20110100356 A KR20110100356 A KR 20110100356A KR 101247343 B1 KR101247343 B1 KR 101247343B1
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substrate
cutting
semiconductor package
semiconductor chip
semiconductor
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Korean (ko)
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부경택
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에스티에스반도체통신 주식회사
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    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor package having electromagnetic wave shielding unit is provided to prevent a short circuit by using a shielding layer. CONSTITUTION: A semiconductor chip is mounted on a substrate(S100). A molding process for sealing the semiconductor chip and the substrate is performed(S200). A first cutting process for cutting only the molding part is performed(S300). A conductive material is formed on the cutting surface of the molding part(S400) to form a shielding layer. A second cutting process is performed on the molding part(S500) to separate a semiconductor package. [Reference numerals] (AA) Start; (BB) End; (S100) Mounting a semiconductor chip on a substrate for package; (S200) Performing a molding process for sealing the semiconductor chip; (S300) Performing a first cutting process for cutting only a molding part; (S400) Forming a shielding layer on the surface of the molding part with a conductive material; (S500) Separating a semiconductor package by a second cutting process

Description

전자파 차폐 수단을 갖는 반도체 패키지 제조방법{Method for manufacturing a semiconductor package having a anti- electromagnetic wave means}Method for manufacturing a semiconductor package having a anti-electromagnetic wave means

본 발명은 반도체 패키지 제조 방법에 관한 것으로, 더욱 상세하게는 고주파가 발생하는 환경에서 전자파 간섭 및 전자파 내성에 강한 차폐 수단을 갖는 반도체 패키지의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor package, and more particularly, to a method for manufacturing a semiconductor package having a shielding means resistant to electromagnetic interference and electromagnetic resistance in an environment where high frequency is generated.

최근들어 모바일 폰(Mobile phone), 엠.피.쓰리(MP3) 플레이어 및 노트북과 같이 휴대 가능한 전자제품의 수요가 급격히 늘어나면서, 반도체 패키지의 형태 역시 박형화, 소형화, 다기능화로 변화되고 있는 추세이다.In recent years, as the demand for portable electronic products such as mobile phones, MP3 players, and notebooks has increased rapidly, the shape of the semiconductor package is also changing to thinner, smaller, and more versatile.

이러한 반도체 패키지에 대한 요구를 충족하기 위하여 CSP(Chip Scale Package), QFN(Quad Flat Non-leads) 패키지와 같이 얇고 작은 크기를 갖는 반도체 패키지의 사용이 현저하게 증가되고 있다. 이와 동시에 다기능화 기능을 충족시키기 위하여 반도체 패키지 내에 높은 밀도의 I/O 단자(Input/Output terminals)를 집어넣으려는 다양한 시도가 이루어지고 있다.In order to meet the demand for such semiconductor packages, the use of semiconductor packages having thin and small sizes such as chip scale packages (CSPs) and quad flat non-leads (QFN) packages has increased significantly. At the same time, various attempts have been made to insert high density input / output terminals into a semiconductor package to satisfy the multifunctionality.

한편, 전자파 간섭이 심한 고주파 환경에 사용되는 반도체 패키지는, 안정적인 동작을 위해 고주파에 대한 내성을 강화시켜야 한다. 일반적으로 고주파 영역에 사용되는 반도체 패키지의 구조는, 인쇄회로기판(PCB) 형태의 기판 위에 반도체 칩을 탑재한 후, 상기 반도체 칩을 덮는 금속 케이스(metal case)를 씌우는 구조가 널리 채택되고 있다. On the other hand, semiconductor packages used in high frequency environments with high electromagnetic interference have to enhance resistance to high frequencies for stable operation. In general, a structure of a semiconductor package used in a high frequency region has been widely adopted in which a semiconductor chip is mounted on a printed circuit board (PCB) type substrate and then covered with a metal case covering the semiconductor chip.

하지만 금속 케이스를 갖는 반도체 패키지는 몰딩 공정에서 성형성이 떨어지는 단점과, 금속 케이스를 기판에 부착하는 별도의 장비와 추가 공정이 필요하며, 금속 케이스가 기판과 완전하게 밀착하지 못하여 전자파 차폐의 한계를 갖는 문제점이 존재한다. 이 외에 금속 케이스 자체가 외부의 충격에 취약한 단점을 지니고 있다.However, the semiconductor package having a metal case has a disadvantage of poor moldability in the molding process, a separate equipment and an additional process for attaching the metal case to the substrate, and the limitation of electromagnetic shielding due to the metal case being incomplete contact with the substrate. There is a problem. In addition, the metal case itself has a disadvantage of being vulnerable to external shocks.

한편, 이러한 문제점을 극복하기 위해 금속 케이스를 사용하지 않고, 반도체 패키지가 최종적으로 만들어진 상태에서 외부에서 도전성 물질을 도포하는 방식으로 전자파를 차폐할 수 있는 차폐막을 형성하는 방식이 소개된 바 있다. 하지만 이 방법 역시 도전성 물질을 도포할 때 반도체 패키지에서 합선 발생의 위험이 있는 영역에 부분적으로 보호 필름을 사용하야 하는 단점과, 이러한 보호 필름을 부착하는 별도 공정을 진행해야 하는 어려움이 존재한다. 이와 함께 스트립(strip) 상태의 기판으로부터 개별 반도체 패키지를 분리하면, 기판의 측면에 인쇄회로패턴의 회로선 일부가 노출되는 경우가 있다. 노출된 회로선에 차폐막 형성을 위한 도전성 물질이 도포되면 합선(short)의 위험이 발생하기 때문에 구조적인 제약이 존재한다.On the other hand, to overcome this problem, a method of forming a shielding film capable of shielding electromagnetic waves by introducing a conductive material from the outside in a state where the semiconductor package is finally made without using a metal case has been introduced. However, this method also has a disadvantage in that a protective film must be partially used in a region where a short circuit occurs in a semiconductor package when applying a conductive material, and there is a difficulty in carrying out a separate process of attaching the protective film. In addition, when the individual semiconductor packages are separated from the substrate in a strip state, a part of circuit lines of the printed circuit pattern may be exposed on the side of the substrate. When the conductive material for forming the shielding film is applied to the exposed circuit line, there is a structural limitation because there is a risk of short circuit.

본 발명이 이루고자 하는 기술적 과제는, 상술한 문제점을 해결하기 위해, 기존에 사용하는 반도체 패키지 제조공정에서 간단한 공정의 전환에 의해, 반도체 패키지 외부에 차폐막을 형성함으로써 전자파 간섭으로부터 반도체 패키지 동작의 신뢰성을 높일 수 있는 전자파 차폐 수단을 갖는 반도체 패키지 제조방법을 제공하는데 있다.The technical problem to be solved by the present invention is to solve the above-mentioned problems, and to reduce the reliability of the semiconductor package operation from electromagnetic interference by forming a shielding film outside the semiconductor package by switching a simple process in a conventional semiconductor package manufacturing process. The present invention provides a method for manufacturing a semiconductor package having an electromagnetic shielding means that can be increased.

상기 기술적 과제를 달성하기 위해 본 발명에 의한 전자파 차폐 수단을 갖는 반도체 패키지 제조방법은, 반도체 칩을 기판에 탑재하는 단계; 상기 반도체 칩 및 기판 상부를 밀봉하는 몰딩 공정을 수행하는 단계; 상기 기판에서 반도체 패키지를 분리하는 1차 커팅 공정을 진행하되 몰딩부만을 커팅하는 1차 부분 커팅을 진행하는 단계; 상기 1차 부분 커팅이 진행된 몰딩부 표면에 도전성 물질을 형성하는 단계; 및 상기 1차 부분 커팅이 진행된 영역에 2차 커팅을 수행하여 기판으로부터 반도체 패키지를 완전히 분리하는 단계를 구비하는 것을 특징으로 한다. According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor package having an electromagnetic shielding means including mounting a semiconductor chip on a substrate; Performing a molding process of sealing an upper portion of the semiconductor chip and the substrate; Performing a first cutting process of separating a semiconductor package from the substrate, but performing a first partial cutting of cutting only a molding part; Forming a conductive material on a surface of the molding part subjected to the first partial cutting; And separating the semiconductor package from the substrate by performing the second cutting on the region where the first partial cutting has been performed.

본 발명의 바람직한 실시예에 의하면, 상기 반도체 칩을 기판에 탑재하는 단계 후, 상기 반도체 칩을 와이어로 상기 기판과 연결하는 공정을 더 진행할 수 있다. According to a preferred embodiment of the present invention, after the step of mounting the semiconductor chip on the substrate, the process of connecting the semiconductor chip with the substrate by a wire can be further proceeded.

또한 본 발명의 바람직한 실시예에 의하면, 상기 1차 부분 커팅을 진행하는 방법은, 상기 기판 내에 포함된 인쇄회로패턴이 노출되지 않도록 진행하거나, 상기 기판 내에 포함된 인쇄회로패턴 중에서 접지용 패턴이 외부로 노출되도록 진행할 수 있다.In addition, according to a preferred embodiment of the present invention, in the method of performing the first partial cutting, the printed circuit pattern included in the substrate is not exposed, or the grounding pattern among the printed circuit patterns included in the substrate is external. May be exposed to.

바람직하게는, 상기 1차 부분 커팅에 의해 노출된 접지용 패턴은, 상기 기판 하부에 형성된 접지 단자용 솔더볼 패드와 연결된 것이 적합하다.Preferably, the grounding pattern exposed by the first partial cutting is connected to the solder ball pad for grounding terminal formed under the substrate.

한편, 상기 몰딩부 표면에 도전성 물질을 형성하는 방법은, 상기 기판 상부에서 도전성 물질을 도포 방식으로 형성하는 것이 바람직하다.On the other hand, the method of forming a conductive material on the molding portion surface, it is preferable to form a conductive material on the upper substrate by a coating method.

또한, 상기 몰딩부 표면에 도전성 물질을 형성하는 방법은, 상기 기판 하부에 보호 필름을 형성하는 단계; 및 상기 기판에 무전해 도금 공정을 진행하여 형성할 수도 있다. In addition, the method of forming a conductive material on the surface of the molding portion, forming a protective film on the lower substrate; And an electroless plating process on the substrate.

따라서, 상술한 본 발명에 의하면, 고주파 환경에 사용되는 반도체 패키지에서 별도의 금속 케이스를 사용하거나, 보호 필름을 부착하는 추가 공정을 진행하지 않고도 반도체 칩이 위치한 몰딩부 표면에 차폐막을 효과적으로 형성할 수 있다. 이에 따라, 반도체 패키지의 제조 공정이 단순화되며, 별도의 추가 재료를 사용하지 않기 때문에 비용 절감 및 생산성을 개선하는 효과를 얻을 수 있다.Therefore, according to the present invention described above, it is possible to effectively form a shielding film on the surface of the molding part in which the semiconductor chip is located without using a separate metal case or performing an additional process of attaching a protective film in a semiconductor package used in a high frequency environment. have. Accordingly, the manufacturing process of the semiconductor package is simplified, and since no additional material is used, cost reduction and productivity may be improved.

도 1은 본 발명의 바람직한 실시예에 의한 전자파 차폐 수단을 갖는 반도체 패키지 제조방법을 설명하기 위한 플로차트(flowchart)이다.
도 2 내지 도 6은 본 발명의 바람직한 실시예에 의한 전자파 차폐 수단을 갖는 반도체 패키지 제조방법을 설명하기 위한 단면도들이다.
도 7은 본 발명의 바람직한 실시예에 따라 제조된 전자파 차폐 수단을 갖는 반도체 패키지의 단면도이다.
도 8은 도 7의 변형예를 설명하기 위한 전자파 차폐 수단을 갖는 반도체 패키지의 단면도이다.1 is a flowchart for explaining a method of manufacturing a semiconductor package having an electromagnetic shielding means according to a preferred embodiment of the present invention.
2 to 6 are cross-sectional views illustrating a method of manufacturing a semiconductor package having an electromagnetic shielding means according to a preferred embodiment of the present invention.
7 is a cross-sectional view of a semiconductor package having electromagnetic shielding means manufactured according to a preferred embodiment of the present invention.
FIG. 8 is a cross-sectional view of a semiconductor package having electromagnetic shielding means for explaining the modification of FIG. 7.

본 발명의 구성 및 효과를 충분히 이해하기 위하여, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예들을 설명한다. 그러나 본 발명은 이하에서 개시되는 실시예들에 한정되는 것이 아니라, 여러가지 형태로 구현될 수 있고 다양한 변경을 가할 수 있다. 단지, 본 실시예들에 대한 설명은 본 발명의 개시가 완전하도록 하며, 본 발명이 속하는 기술 분야의 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위하여 제공되는 것이다. 첨부된 도면에서 구성 요소들은 설명의 편의를 위하여 그 크기가 실제보다 확대하여 도시한 것이며, 각 구성 요소의 비율은 과장되거나 축소될 수 있다. In order to fully understand the constitution and effects of the present invention, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below, but may be embodied in various forms and various modifications may be made. It should be understood, however, that the description of the embodiments is provided to enable the disclosure of the invention to be complete, and will fully convey the scope of the invention to those skilled in the art. In the accompanying drawings, the constituent elements are shown enlarged for the sake of convenience of explanation, and the proportions of the constituent elements may be exaggerated or reduced.

제 1, 제 2 등의 용어는 다양한 구성요소들을 설명하는데 사용될 수 있지만, 상기 구성요소들은 상기 용어들에 의해 한정되어서는 않된다. 상기 용어들은 하나의 구성요소를 다른 구성요소로부터 구별하는 목적으로만 사용될 수 있다. 예를 들어, 본 발명의 권리 범위를 벗어나지 않으면서 제 1 구성요소는 제 2 구성요소로 명명될 수 있고, 유사하게 제 2 구성요소도 제 1 구성요소로 명명될 수 있다. Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms may be used only for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

본 발명의 실시예들에서 사용되는 용어들은 다르게 정의되지 않는 한, 해당 기술 분야에서 통상의 지식을 가진 자에게 통상적으로 알려진 의미로 해석될 수 있다.The terms used in the embodiments of the present invention may be construed as commonly known to those skilled in the art unless otherwise defined.

이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 설명함으로써 본 발명을 상세히 설명한다. 각 도면에 제시된 동일한 참조부호는 동일한 부재를 나타낸다. Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

도 1은 본 발명의 바람직한 실시예에 의한 전자파 차폐 수단을 갖는 반도체 패키지 제조방법을 설명하기 위한 플로차트(flowchart)이다.1 is a flowchart for explaining a method of manufacturing a semiconductor package having an electromagnetic shielding means according to a preferred embodiment of the present invention.

도 1을 참조하면, 먼저 반도체 칩을 패키지용 기판에 탑재(S100)한다. 상기 반도체 칩은 고주파 환경에서 동작 특성이 예민하게 영향을 받는 반도체 소자일 수 있다. 상기 패키지용 기판은 인쇄회로기판 형태의 기판을 의미한다. 또한 상기 기판의 구조는 기판 상부에는 반도체 칩의 패드와 연결될 수 있는 본드 핑거(finger) 및 칩 탑재부가 형성되고, 기판 하부에는 솔더볼과 같은 외부연결단자가 부착될 수 있는 패드가 형성된 것이 사용될 수 있다.Referring to FIG. 1, a semiconductor chip is first mounted on a package substrate (S100). The semiconductor chip may be a semiconductor device in which operating characteristics are sensitively affected in a high frequency environment. The package substrate means a substrate in the form of a printed circuit board. In addition, the structure of the substrate may be a bond finger (finger) and a chip mounting portion that can be connected to the pad of the semiconductor chip is formed on the substrate, the pad formed on the bottom of the substrate can be attached to an external connection terminal such as solder ball may be used. .

상기 반도체 칩은 접착 테이프 혹은 접착제를 사용하여 기판 위에 탑재될 수 있으며, 플립 칩(flip-chip)인 경우 범프(bump)를 통해 탑재될 수도 있다. 반도체 패키지가 멀티칩 패키지인 경우, 쓰루 실리콘 비아(TSV: Through Silicon Via)를 통해 반도체 칩이 탑재될 수도 있다. 이때 접착 테이프를 통해 반도체 칩이 기판 위에 탑재된 경우, 반도체 칩의 본드 패드와 기판의 본드 핑거를 와이어로 연결하는 와이어 본딩 공정을 추가로 진행할 수 있다.The semiconductor chip may be mounted on a substrate using an adhesive tape or an adhesive, or in the case of a flip-chip, may be mounted through a bump. When the semiconductor package is a multichip package, the semiconductor chip may be mounted through a through silicon via (TSV). In this case, when the semiconductor chip is mounted on the substrate through the adhesive tape, a wire bonding process of connecting the bond pad of the semiconductor chip and the bond finger of the substrate may be further performed.

계속해서, 상기 기판에 탑재된 반도체 칩을 에폭시 몰드 컴파운드(EMC)와 같은 봉지재로 밀봉하는 몰딩 공정을 수행(S200)한다. 그 후, 몰딩부만을 부분적으로 자르는 1차 커팅을 수행(S200)한다. 이어서 기판 위로 노출된 몰딩부 표면에 도전성 물질로 차폐막을 형성(S400)한다. 상기 차폐막을 형성하는 방식은, 도포 혹은 무전해 도금 방식이 이용될 수 있으며, 이에 대해서는 추후 도면을 참조하여 상세하게 설명한다.Subsequently, a molding process of sealing the semiconductor chip mounted on the substrate with an encapsulant such as epoxy mold compound (EMC) is performed (S200). Thereafter, primary cutting is performed to partially cut only the molding part (S200). Subsequently, a shielding layer is formed of a conductive material on the surface of the molding part exposed on the substrate (S400). As the method of forming the shielding film, a coating or an electroless plating method may be used, which will be described in detail later with reference to the drawings.

마지막으로 전자파에 대한 차폐막이 형성된 결과물에 2차 커팅, 예컨대 인쇄회로기판 형태의 기판을 완전히 절단하는 공정을 쏘우 블레이드(saw blade) 혹은 레이저 커팅(LASER cutting) 등을 이용하여 수행한다.Finally, a second cutting process, for example, a completely cut substrate in the form of a printed circuit board, is performed on a resultant film on which electromagnetic shielding is formed by using a saw blade or laser cutting.

도 2 내지 도 6은 본 발명의 바람직한 실시예에 의한 전자파 차폐 수단을 갖는 반도체 패키지 제조방법을 설명하기 위한 단면도들이다.2 to 6 are cross-sectional views illustrating a method of manufacturing a semiconductor package having an electromagnetic shielding means according to a preferred embodiment of the present invention.

도 2 및 도 3을 참조하면, 인쇄회로기판(PCB) 위에 다수의 반도체 패키지가 매트릭스 (matrix) 형태로 들어갈 수 있도록 설계된 스트립 형태(strip type)의 기판(100)을 준비한다. 상기 기판(100)의 상부면은 반도체 칩이 탑재될 수 있는 칩 탑재부, 반도체 칩의 본드패드가 연결될 수 있는 인쇄회로패턴인 본드 핑거(bond finger)가 형성된 것일 수 있다. 이어서 반도체 칩(102)을 접착테이프 혹은 에폭시와 같은 접착제를 사용하여 상기 기판(100)의 칩 탑재부에 부착한다. 2 and 3, a strip type substrate 100 designed to allow a plurality of semiconductor packages to enter a matrix on a printed circuit board (PCB) is prepared. The upper surface of the substrate 100 may have a chip mounting portion on which a semiconductor chip may be mounted, and a bond finger which is a printed circuit pattern to which a bond pad of the semiconductor chip may be connected. The semiconductor chip 102 is then attached to the chip mounting portion of the substrate 100 using an adhesive such as adhesive tape or epoxy.

한편, 반도체 칩(102)을 기판(100) 위에 탑재하는 방식은 본 발명에서는 예시적으로 제시하였으나, 본 발명의 사상은 이에 제한되지 않고 많은 변형이 가능하다. 가령, 접착 테이프를 사용하는 대신에 플립 칩의 범프를 통해 상기 반도체 칩(102)의 본드 패드와 기판(100)의 본드 핑거를 서로 연결할 수도 있다. 또한 복수의 반도체 칩(102)들이 수직으로 적층된 구조일 경우, 내부에 형성된 쓰루 실리콘 비아(TSV)를 통해 반도체 칩(102)들과 기판(100)을 서로 연결할 수도 있다. 이어서 도 2와 같이 와이어(104), 예컨대 금선을 사용해서 상기 반도체 칩(102)의 본드 패드와 상기 기판(100)의 본드 핑거를 서로 연결하는 와이어 본딩 공정을 진행한다.Meanwhile, the method of mounting the semiconductor chip 102 on the substrate 100 has been exemplarily shown in the present invention, but the spirit of the present invention is not limited thereto and many modifications are possible. For example, instead of using an adhesive tape, the bond pads of the semiconductor chip 102 and the bond fingers of the substrate 100 may be connected to each other through bumps of the flip chip. In addition, when the plurality of semiconductor chips 102 are stacked vertically, the semiconductor chips 102 and the substrate 100 may be connected to each other through a through silicon via (TSV) formed therein. Subsequently, as shown in FIG. 2, a wire bonding process of connecting the bond pad of the semiconductor chip 102 and the bond finger of the substrate 100 to each other using a wire 104, for example, a gold wire, is performed.

도 4 및 도 5를 참조하면, 상기 와이어 본딩이 진행된 결과물에 에폭시 몰드 컴파운드(EMC)와 같은 봉지재(106)를 사용하여 상기 반도체 칩(102)과 기판(100)의 상부를 덮는 몰딩 공정을 진행한다. 상기 봉지재(106)는 각각의 반도체 칩(102)을 하나씩 덮는 형태가 아니라, 기판(100) 상부 전체를 덮는 방식으로 몰딩 공정이 이루어지는 것이 적합하다. 상기 몰딩 공정이 완료된 후, 기판(100) 하부에 솔더볼(108)을 부착하는 공정을 추가로 진행할 수 있다. 4 and 5, a molding process of covering the upper portion of the semiconductor chip 102 and the substrate 100 using an encapsulant 106 such as an epoxy mold compound (EMC) on the result of the wire bonding is performed. Proceed. The encapsulant 106 is not formed to cover each of the semiconductor chips 102 one by one, it is preferable that the molding process is performed in such a manner that covers the entire upper portion of the substrate (100). After the molding process is completed, a process of attaching the solder ball 108 to the lower portion of the substrate 100 may be further performed.

이어서 도 5와 같이 다이아몬드 재질의 쏘우 블레이드(saw blade)를 사용하여 1차 부분 커팅(110)을 진행한다. 상기 1차 부분 커팅(110)은 상기 봉지재(106)가 몰딩된 결과물에서 봉지재(106) 부분만을 절단하는 방식으로 진행하는 것이 바람직하다. 따라서 기판(100)은 절단되지 않은 상태로 그대로 남아 있기 때문에 반도체 패키지의 제조공정에서 기판(100) 취급의 불편함을 없앨 수 있다.Subsequently, the first partial cutting 110 is performed using a saw blade made of diamond as shown in FIG. 5. The first partial cutting 110 may be performed by cutting only the portion of the encapsulant 106 from the result of the encapsulant 106 being molded. Therefore, since the substrate 100 remains uncut, the inconvenience of handling the substrate 100 in the manufacturing process of the semiconductor package can be eliminated.

도 6을 참조하면, 상기 1차 부분 커팅(110)이 진행된 결과물에서 봉지재(106) 표면에 도전성 물질을 이용하여 차폐막(112)을 형성한다. 상기 차폐막(112)은 도전성 물질이면 사용이 가능하다. 도전성 물질의 일 예로서, 구리, 알루미늄과 같은 금속 혹은 구리, 알루미늄의 금속 화합물이 사용될 수 있다. 통상적으로 금속은 내부에 이동성 자유전자를 포함하고 있기 때문에 전자파의 반사에 매우 효과적으로 작용한다. 그러나 금속은 무겁기 때문에 벌크재료, 섬유, 입자 등에 코팅하여 사용할 수도 있다. 상기 차폐막(112)을 형성하는 방식은 코팅, 무전해도금, 진공증착 등의 방법이 사용될 수 있다.Referring to FIG. 6, the shielding layer 112 is formed on the surface of the encapsulant 106 by using a conductive material in the result of the first partial cutting 110. The shielding film 112 may be used as long as it is a conductive material. As an example of the conductive material, a metal such as copper or aluminum or a metal compound of copper or aluminum may be used. Since metals generally contain mobile free electrons, they are very effective in reflecting electromagnetic waves. However, since the metal is heavy, it can be used by coating on bulk materials, fibers, particles, and the like. The shielding layer 112 may be formed by coating, electroless plating, vacuum deposition, or the like.

코팅이나 진공증착 방식을 사용하여 차폐막(112)을 형성할 때에는, 별도의 보호 필름 없이 차폐막(112)을 형성해도 무방하다. 하지만, 무전해 도금을 통해 봉지재(106) 표면에 차폐막(112)을 형성할 경우, 기판(100) 하부 인쇄회로패턴(미도시)과, 솔더볼(108)에 합선(short)이 발생하는 것을 방지하기 위해 별도의 보호 필름을 사용하여 덮은 상태에서 무전해 도금을 진행하는 것이 바람직하다.When the shielding film 112 is formed using a coating or vacuum deposition method, the shielding film 112 may be formed without a separate protective film. However, when the shielding film 112 is formed on the surface of the encapsulant 106 through electroless plating, a short circuit occurs in the printed circuit pattern (not shown) and the solder ball 108 under the substrate 100. In order to prevent it, it is preferable to carry out electroless plating in the state covered using a separate protective film.

도 7은 본 발명의 바람직한 실시예에 따라 제조된 전자파 차폐 수단을 갖는 반도체 패키지의 단면도이다.7 is a cross-sectional view of a semiconductor package having electromagnetic shielding means manufactured according to a preferred embodiment of the present invention.

도 7을 참조하면, 상술한 도 6의 차폐막(112)을 형성한 결과물에서 2차 커팅 공정을 진행하여 기판(100)을 완전히 절단하여 스트립 형태의 인쇄회로기판에서 단위 반도체 패키지를 분리한 단면도이다.Referring to FIG. 7, a cross-sectional view of separating a unit semiconductor package from a strip-shaped printed circuit board by completely cutting the substrate 100 by performing a second cutting process on the result of forming the shielding film 112 of FIG. 6 described above. .

본 발명에 의한 전자파 차폐 수단을 갖는 반도체 패키지의 구조적 특징은, 기판(100) 위에 반도체 칩(102)이 탑재되고, 다시 반도체 칩(102)은 와이어(104)를 통해 기판(100)과 전기적으로 연결된다. 그리고 기판(100) 상부면의 반도체 칩(102) 및 와이어(104)는 봉지재(106)에 의해 밀봉되며, 상기 봉지재(106)만을 감싸는 차폐막(112)이 금속 혹은 금속화합물을 통해 형성되어 있다. The structural feature of the semiconductor package having the electromagnetic wave shielding means according to the present invention is that the semiconductor chip 102 is mounted on the substrate 100, and the semiconductor chip 102 is electrically connected to the substrate 100 through the wire 104. Connected. The semiconductor chip 102 and the wire 104 of the upper surface of the substrate 100 are sealed by the encapsulant 106, and a shielding film 112 covering only the encapsulant 106 is formed through a metal or a metal compound. have.

한편, 상기 차폐막(112)은 2차 커팅을 진행하기 전에 기판(100) 상부에서만 형성되었기 때문에, 기판(100)의 측면이나 하부면에는 차폐막(112)이 형성되지 않은 특징을 갖는다. 따라서 기판(100) 측면에 인쇄회로패턴과 같은 도전성 패턴이 존재하더라도 이곳에서 합선(short)이 발생하지 않는다. 이와 함께, 별도의 금속케이스를 부착하는 공정을 진행할 필요가 없기 때문에 공정을 단순화시켜 생산성을 향상시킨다.On the other hand, since the shielding film 112 is formed only on the upper portion of the substrate 100 before the secondary cutting, the shielding layer 112 is not formed on the side or bottom surface of the substrate 100. Therefore, even if a conductive pattern such as a printed circuit pattern exists on the side of the substrate 100, a short circuit does not occur there. In addition, since it is not necessary to proceed with the process of attaching a separate metal case, the process is simplified to improve productivity.

도 8은 도 7의 변형예를 설명하기 위한 전자파 차폐 수단을 갖는 반도체 패키지의 단면도이다.FIG. 8 is a cross-sectional view of a semiconductor package having electromagnetic shielding means for explaining the modification of FIG. 7.

도 8을 참조하면, 도 7의 전자파 차폐막(112)을 갖는 반도체 패키지는, 1차 부분 커팅을 진행할 때 기판(100) 표면에 별도의 인쇄회로패턴이 존재하지 않았다. 하지만 본 변형예는 1차 부분 커팅이 진행된 기판(100) 표면(도5의 110)에 접지용 패턴(114)이 노출되도록 한다. 따라서 후속공정에서 형성된 차폐막(112)은 접지용 패턴(114)과 기판의 관통홀을 통해 접지 기능의 솔더볼(108G)이 부착되는 솔더볼 패드와 전기적으로 연결된다. 이에 따라 차폐막(112)이 반도체 패키지의 접지 단자(108G)와 서로 연결되기 때문에 전자파의 차폐 능력을 더욱 개선시킬 수 있는 장점이 있다.Referring to FIG. 8, the semiconductor package having the electromagnetic shielding film 112 of FIG. 7 does not have a separate printed circuit pattern on the surface of the substrate 100 when the first partial cutting is performed. However, the present modified example exposes the grounding pattern 114 to the surface of the substrate 100 (110 in FIG. 5) where the first partial cutting has been performed. Therefore, the shielding film 112 formed in a subsequent process is electrically connected to the solder ball pad to which the solder ball 108G of the ground function is attached through the grounding pattern 114 and the through hole of the substrate. Accordingly, since the shielding film 112 is connected to the ground terminal 108G of the semiconductor package, there is an advantage of further improving the shielding ability of electromagnetic waves.

본 발명은 상기한 실시예에 한정되지 않으며, 본 발명이 속한 기술적 사상 내에서 당 분야의 통상의 지식을 가진 자에 의해 많은 변형이 가능함이 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical spirit to which the present invention belongs.

100: 기판, 102: 반도체 칩,
104: 와이어, 106: 봉지재,
108: 솔더볼, 110: 1차 부분 커팅부,
112: 차폐막, 114: 접지용 패턴.100: substrate, 102: semiconductor chip,
104: wire, 106: encapsulant,
108: solder ball, 110: primary cut portion,
112: shielding film, 114: grounding pattern.

Claims (7)

반도체 칩을 기판에 탑재하는 단계;
상기 반도체 칩 및 기판 상부를 밀봉하는 몰딩 공정을 수행하는 단계;
상기 기판에서 반도체 패키지를 분리하는 1차 커팅 공정을 진행하되 몰딩부만을 커팅하는 1차 부분 커팅을 진행하는 단계;
상기 1차 부분 커팅이 진행된 몰딩부 표면에 도전성 물질을 형성하는 단계; 및
상기 1차 부분 커팅이 진행된 영역에 2차 커팅을 수행하여 기판으로부터 반도체 패키지를 완전히 분리하는 단계를 구비하되,
상기 1차 부분 커팅을 진행하는 방법은,
상기 기판 내에 포함된 인쇄회로패턴이 노출되지 않도록 진행하는 것을 특징으로 하는 전자파 차폐 수단을 갖는 반도체 패키지 제조방법.Mounting a semiconductor chip on a substrate;
Performing a molding process of sealing an upper portion of the semiconductor chip and the substrate;
Performing a first cutting process of separating a semiconductor package from the substrate, but performing a first partial cutting of cutting only a molding part;
Forming a conductive material on a surface of the molding part subjected to the first partial cutting; And
Comprising a second cutting in the area where the first partial cutting has been performed to completely separate the semiconductor package from the substrate,
The method of performing the first partial cutting,
The method of manufacturing a semiconductor package having an electromagnetic shielding means, characterized in that the progress of the printed circuit pattern contained in the substrate is not exposed. 제1항에 있어서,
상기 반도체 칩을 기판에 탑재하는 단계 후,
상기 반도체 칩을 와이어로 상기 기판과 연결하는 공정을 더 진행하는 것을 특징으로 하는 전자파 차폐 수단을 갖는 반도체 패키지 제조방법. The method of claim 1,
After mounting the semiconductor chip on a substrate,
And further comprising connecting the semiconductor chip to the substrate by a wire. 삭제delete 삭제delete 삭제delete 제1항에 있어서,
상기 몰딩부 표면에 도전성 물질을 형성하는 방법은,
상기 기판 상부에서 도전성 물질을 도포 방식으로 형성하는 것을 특징으로 하는 전자파 차폐 수단을 갖는 반도체 패키지 제조방법. The method of claim 1,
Forming a conductive material on the molding surface,
A method of manufacturing a semiconductor package having electromagnetic shielding means, characterized in that the conductive material is formed on the substrate by coating. 반도체 칩을 기판에 탑재하는 단계;
상기 반도체 칩 및 기판 상부를 밀봉하는 몰딩 공정을 수행하는 단계;
상기 기판에서 반도체 패키지를 분리하는 1차 커팅 공정을 진행하되 몰딩부만을 커팅하는 1차 부분 커팅을 진행하는 단계;
상기 1차 부분 커팅이 진행된 몰딩부 표면에 도전성 물질을 형성하는 단계; 및
상기 1차 부분 커팅이 진행된 영역에 2차 커팅을 수행하여 기판으로부터 반도체 패키지를 완전히 분리하는 단계를 구비하되,
상기 몰딩부 표면에 도전성 물질을 형성하는 방법은,
상기 기판 하부에 보호 필름을 형성하는 단계; 및
상기 기판에 무전해 도금 공정을 진행하여 형성하는 단계를 구비하는 것을 특징으로 하는 전자파 차폐 수단을 갖는 반도체 패키지 제조방법.Mounting a semiconductor chip on a substrate;
Performing a molding process of sealing an upper portion of the semiconductor chip and the substrate;
Performing a first cutting process of separating a semiconductor package from the substrate, but performing a first partial cutting of cutting only a molding part;
Forming a conductive material on a surface of the molding part subjected to the first partial cutting; And
Comprising a second cutting in the area where the first partial cutting has been performed to completely separate the semiconductor package from the substrate,
Forming a conductive material on the molding surface,
Forming a protective film under the substrate; And
And forming an electroless plating process on the substrate.
KR1020110100356A 2011-09-30 2011-09-30 Method for manufacturing a semiconductor package having a anti- electromagnetic wave means KR101247343B1 (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016047880A1 (en) * 2014-09-23 2016-03-31 제너셈(주) Method for treating semiconductor package with emi shield
US9837361B2 (en) 2014-10-20 2017-12-05 Samsung Electronics Co., Ltd. Semiconductor package with electromagnetic shielding member
US10468353B2 (en) 2016-09-07 2019-11-05 Samsung Electronics Co., Ltd. Semiconductor packages and methods of fabricating the same
US10624248B2 (en) 2016-04-08 2020-04-14 Samsung Electronics Co., Ltd. EMI shielding structure and manufacturing method therefor
KR20210071477A (en) 2019-12-06 2021-06-16 광주대학교산학협력단 A packaging method for semiconductor components
WO2022146233A1 (en) * 2020-12-30 2022-07-07 Ams Sensors Singapore Pte. Ltd. Method of shielding electronic modules from radio frequency electromagnetic radiation

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020036039A (en) * 2000-11-07 2002-05-16 마이클 디. 오브라이언 Semiconductor package and method for manufacturing the same
KR20110020548A (en) * 2009-08-24 2011-03-03 주식회사 하이닉스반도체 Semiconductor package and method for fabricating the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020036039A (en) * 2000-11-07 2002-05-16 마이클 디. 오브라이언 Semiconductor package and method for manufacturing the same
KR20110020548A (en) * 2009-08-24 2011-03-03 주식회사 하이닉스반도체 Semiconductor package and method for fabricating the same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016047880A1 (en) * 2014-09-23 2016-03-31 제너셈(주) Method for treating semiconductor package with emi shield
US9583447B2 (en) 2014-09-23 2017-02-28 Genesem Inc. EMI shielding method of semiconductor packages
US9837361B2 (en) 2014-10-20 2017-12-05 Samsung Electronics Co., Ltd. Semiconductor package with electromagnetic shielding member
US10624248B2 (en) 2016-04-08 2020-04-14 Samsung Electronics Co., Ltd. EMI shielding structure and manufacturing method therefor
US10468353B2 (en) 2016-09-07 2019-11-05 Samsung Electronics Co., Ltd. Semiconductor packages and methods of fabricating the same
US10629544B2 (en) 2016-09-07 2020-04-21 Samsung Electronics Co., Ltd. Semiconductor packages
KR20210071477A (en) 2019-12-06 2021-06-16 광주대학교산학협력단 A packaging method for semiconductor components
WO2022146233A1 (en) * 2020-12-30 2022-07-07 Ams Sensors Singapore Pte. Ltd. Method of shielding electronic modules from radio frequency electromagnetic radiation

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