JPH08288686A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH08288686A JPH08288686A JP7095461A JP9546195A JPH08288686A JP H08288686 A JPH08288686 A JP H08288686A JP 7095461 A JP7095461 A JP 7095461A JP 9546195 A JP9546195 A JP 9546195A JP H08288686 A JPH08288686 A JP H08288686A
- Authority
- JP
- Japan
- Prior art keywords
- package
- substrate
- epoxy resin
- glass epoxy
- metal coating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
ボールグリッドアレイパッケージの半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a ball grid array package semiconductor device.
【0002】[0002]
【従来の技術】従来のボールグリッドアレイ(Ball
Grid Array)パッケージの半導体装置(以
下、BGAと記す)は、図3に示すように、まず、配線
2を施したガラスエポキシ樹脂基板(以下、基板と記
す)1の表面に導電性の接着剤で半導体チップ3を接着
搭載し、半導体チップ3上にある接点パッド(以下、パ
ッドと記す)と配線2とを金線等の金属線4を超音波熱
圧着で電気的に接合する。次に、半導体チップ3と金属
線4を保護するためにエポキシ系の樹脂5で基板1の表
面を封止し基板1の裏面にハンダボール6を設ける。ハ
ンダボール6はBGAを装置基板に実装する際にリフロ
ーの熱で溶けてハンダ付けされる。BGAはQFP(Q
uad Flat Package)と比較するとリー
ド曲がりの心配ない分取り扱いが容易であり、同等のピ
ン数では実装面積が小さくなる等の利点があるため使用
率が上がってきているが、基板1の吸湿性が大きいこと
と基板1と樹脂5との密着性が低いためにBGAの信頼
性を低下させ問題になっている。2. Description of the Related Art A conventional ball grid array (Ball)
As shown in FIG. 3, a semiconductor device (hereinafter, referred to as BGA) of a grid array package first has a conductive adhesive on the surface of a glass epoxy resin substrate (hereinafter, referred to as substrate) 1 on which wiring 2 is formed. Then, the semiconductor chip 3 is adhesively mounted, and the contact pads (hereinafter, referred to as pads) on the semiconductor chip 3 and the wiring 2 are electrically joined by a metal wire 4 such as a gold wire by ultrasonic thermocompression bonding. Next, in order to protect the semiconductor chip 3 and the metal wires 4, the front surface of the substrate 1 is sealed with an epoxy resin 5 and solder balls 6 are provided on the back surface of the substrate 1. The solder balls 6 are melted by the heat of reflow and soldered when the BGA is mounted on the device substrate. BGA is QFP (Q
Compared with uad Flat Package), handling is easier because there is no concern about lead bending, and the usage rate is increasing due to the advantage that the mounting area becomes smaller with an equivalent number of pins, but the hygroscopicity of substrate 1 Since it is large and the adhesion between the substrate 1 and the resin 5 is low, the reliability of the BGA is reduced, which is a problem.
【0003】[0003]
【発明が解決しようとする課題】従来のBGAは基板の
吸湿性が高く、基板と樹脂との密着性が低いため保管時
の条件が厳しく厳重なドライパックをする必要があり、
そのため包装資材コストが高くユーザー側での使い勝手
が悪い。また、いくら厳重なドライパックを施しても一
度開封するとすぐに吸湿するのでリフローの際パッケー
ジにクラックが生じる等の問題がある。In the conventional BGA, the hygroscopicity of the substrate is high and the adhesion between the substrate and the resin is low, so that it is necessary to form a dry pack under severe storage conditions.
Therefore, the packaging material cost is high and the usability for the user is poor. In addition, even if a strict dry pack is applied, the package absorbs moisture as soon as it is opened, so that there is a problem that the package is cracked during reflow.
【0004】本発明の目的は、基板の吸湿性が低く、厳
重なドライパックの必要がなく、リフローの際パッケー
ジにクラックの発生のない半導体装置を提供することに
ある。An object of the present invention is to provide a semiconductor device which has a low hygroscopicity of a substrate, does not require a strict dry pack, and has no cracks in the package during reflow.
【0005】[0005]
【課題を解決するための手段】本発明は、配線が施され
たガラスエポキシ樹脂基板と、このガラスエポキシ樹脂
基板に導電性接着剤で接着された多数の接点パッドが形
成された半導体チップと、この半導体チップの前記接点
パッドと前記ガラスエポキシ樹脂基板の前記配線とを接
続する金線を含む金属線と、前記半導体チップをコーテ
ィングする樹脂と、前記ガラスエポキシ樹脂基板の裏面
に設けられ実装基板に実装するためのハンダホールとを
有するボールグリッドアレイパッケージの半導体装置に
おいて、前記ガラスエポキシ樹脂基板表面が露出しない
ように金属被膜が前記ガラスエポキシ樹脂基板と、前記
樹脂と前記ガラスエポキシ樹脂基板との境界部とを含ん
で被覆しているか、または、ガラスエポキシ樹脂基板と
樹脂との全表面を被覆している。SUMMARY OF THE INVENTION The present invention comprises a glass epoxy resin substrate provided with wiring, and a semiconductor chip having a large number of contact pads bonded to the glass epoxy resin substrate with a conductive adhesive. A metal wire including a gold wire connecting the contact pad of the semiconductor chip and the wiring of the glass epoxy resin substrate, a resin coating the semiconductor chip, and a mounting substrate provided on the back surface of the glass epoxy resin substrate. In a semiconductor device of a ball grid array package having a solder hole for mounting, a metal coating is formed on the glass epoxy resin substrate so that the surface of the glass epoxy resin substrate is not exposed, and a boundary between the resin and the glass epoxy resin substrate. Part of the glass epoxy resin substrate or the entire surface of the resin. It is overturned.
【0006】[0006]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will now be described with reference to the drawings.
【0007】図1は本発明の第1の実施例の断面図であ
る。本発明の第1の実施例は、図1に示すように、ま
ず、配線2を施した基板1の表面に導電性の接着剤で半
導体チップ3を接着し、半導体チップ3上にあるパッド
と配線2とを金線等の金属線4を超音波熱圧着等で電気
的に接合する。次に、半導体チップ3と金属線4を保護
するためにエポキシ系の樹脂5で基板1の表面を封止す
る。次に、樹脂5の表面と後にハンダボール6を接着す
る基板1裏面の配線2の部分をゴムパッド等でマスク
し、パッケージ表面にニッケル等の金属を5〜10μm
程度の厚みに無電界めっきを施し金属被膜7を形成す
る。このとき、樹脂5の表面をマスクする場合は樹脂5
と基板1の境目までめっきできるように幅0.5〜1m
mぐらい残してマスクし境目がめっきで被覆されるよう
にする。また、基板1裏面の配線2の部分をマスクする
場合は0.8〜1.0mm程度の直径にすればハンダボ
ール6と金属被膜7がショートする心配がなくなる。次
に、めっき後ゴムパッドをはずすとハンダボール6との
接着部分以外は基板1の表面の露出する部分が無くなっ
ている。最後に、はんだボール6を導電性接着剤で基板
1の裏面に接着し、吸湿性の低い半導体装置を得る。FIG. 1 is a sectional view of a first embodiment of the present invention. In the first embodiment of the present invention, as shown in FIG. 1, first, a semiconductor chip 3 is bonded to the surface of a substrate 1 provided with wiring 2 with a conductive adhesive, and a pad on the semiconductor chip 3 is formed. A metal wire 4 such as a gold wire is electrically joined to the wiring 2 by ultrasonic thermocompression bonding or the like. Next, the surface of the substrate 1 is sealed with an epoxy resin 5 to protect the semiconductor chip 3 and the metal wire 4. Next, the front surface of the resin 5 and the wiring 2 on the rear surface of the substrate 1 to which the solder balls 6 are to be bonded are masked with a rubber pad or the like, and a metal such as nickel is applied to the package surface by 5 to 10 μm.
The metal coating 7 is formed by performing electroless plating with a thickness of about the same. At this time, when the surface of the resin 5 is masked, the resin 5
0.5 to 1m wide so that it can be plated to the boundary between
Leave about m and mask so that the boundary is covered with plating. When masking the portion of the wiring 2 on the back surface of the substrate 1, the diameter of about 0.8 to 1.0 mm eliminates the risk of short circuit between the solder ball 6 and the metal coating 7. Next, when the rubber pad is removed after plating, the exposed portion of the surface of the substrate 1 is removed except for the portion bonded to the solder ball 6. Finally, the solder balls 6 are adhered to the back surface of the substrate 1 with a conductive adhesive to obtain a semiconductor device having low hygroscopicity.
【0008】図2は本発明の第2の実施例の断面図であ
る。本発明の第2の実施例は、図2に示すように、第1
の実施例と同様に、まず、配線2を施した基板1の表面
に導電性の接着剤で半導体チップ3を接着し、半導体チ
ップ3上にあるパッドと配線2とを金等の金属線4を超
音波熱圧着で電気的に接合する。次に、半導体チップ3
と金属線4を保護するためにエポキシ系の樹脂5で基板
1の表面を封止する。次に、ハンダボール6を接着する
基板1裏面の配線2の部分をゴムパッド等でマスクし、
パッケージ表面にニッケル等の金属を5〜10μm程度
の厚みに無電解めっきを施し金属被膜7を形成する。基
板1裏面の配線2の部分をマスクする場合は0.8〜
1.0mm程度の直径にすればハンダボール6と金属被
膜7がショートする心配が無くなる。次に、めっき後ゴ
ムパッドをはずすとハンダボール6の接着部分以外は基
板1の表面に露出する部分が無くなっている。最後に、
ハンダボール6を導電性接着剤で基板1の裏面に接着
し、吸湿性の低い半導体装置を得る。本実施例では、パ
ッケージ全体が金属被膜7で覆われているので、さら
に、電磁波をシールどし、パッケージの熱抵抗を小さく
できる効果も得られる。FIG. 2 is a sectional view of the second embodiment of the present invention. The second embodiment of the present invention, as shown in FIG.
Similar to the embodiment of the first embodiment, first, the semiconductor chip 3 is adhered to the surface of the substrate 1 on which the wiring 2 is formed with a conductive adhesive, and the pad on the semiconductor chip 3 and the wiring 2 are connected to the metal wire 4 such as gold. Are electrically joined by ultrasonic thermocompression bonding. Next, the semiconductor chip 3
Then, in order to protect the metal wire 4, the surface of the substrate 1 is sealed with an epoxy resin 5. Next, the portion of the wiring 2 on the back surface of the substrate 1 to which the solder ball 6 is adhered is masked with a rubber pad or the like,
A metal film 7 is formed by electroless plating a metal such as nickel to a thickness of about 5 to 10 μm on the surface of the package. 0.8 when masking the wiring 2 on the back surface of the substrate 1
When the diameter is about 1.0 mm, there is no fear that the solder ball 6 and the metal coating 7 will be short-circuited. Next, when the rubber pad is removed after plating, the exposed portion on the surface of the substrate 1 is eliminated except for the adhesive portion of the solder ball 6. Finally,
The solder ball 6 is adhered to the back surface of the substrate 1 with a conductive adhesive to obtain a semiconductor device having low hygroscopicity. In this embodiment, since the entire package is covered with the metal coating 7, the effect of sealing electromagnetic waves and reducing the thermal resistance of the package can be obtained.
【0009】[0009]
【発明の効果】以上説明したように本発明の第1の実施
例では、BGAの基板部分に金属被膜を施したのでパッ
ケージの吸湿性を低くすることができ、出荷時のドライ
パック包装の簡略化ができる。また、リフロー回数も増
やすことができるため、ユーザーの実装時の制限が緩和
される効果が得られる。更に、基板と樹脂との界面を金
属被膜でカバーすることで基板と樹脂との剥離を防ぎパ
ッケージの信頼性を向上させる効果が得られる。As described above, in the first embodiment of the present invention, since the BGA substrate portion is provided with the metal coating, the hygroscopicity of the package can be lowered, and the dry pack packaging at the time of shipping can be simplified. Can be converted. In addition, since the number of reflows can be increased, the effect of relaxing the restrictions at the time of mounting by the user can be obtained. Furthermore, by covering the interface between the substrate and the resin with a metal coating, the effect of preventing the substrate from separating from the resin and improving the reliability of the package can be obtained.
【0010】一方、第2の実施例では、第1の実施例で
得られる効果に加え、パッケージ全体を金属被膜で覆う
ことにより、外部からの電磁波をシールドするため、電
磁波による誤動作等を防ぐ効果が得られる。また、パッ
ケージ内部の半導体チップから発生する電磁波を外部に
もらさない働きもあるので環境への影響を抑える効果が
得られる。更に、パッケージ表面の熱伝導が良くなるた
め、パッケージの熱抵抗が小さくなる効果も得られる。On the other hand, in the second embodiment, in addition to the effect obtained in the first embodiment, the electromagnetic wave from the outside is shielded by covering the entire package with a metal film, so that the malfunction due to the electromagnetic wave is prevented. Is obtained. In addition, since it also works to prevent the electromagnetic waves generated from the semiconductor chip inside the package from being exposed to the outside, the effect of suppressing the influence on the environment can be obtained. Furthermore, since the heat conduction on the package surface is improved, the effect of reducing the thermal resistance of the package can be obtained.
【図1】本発明の第1の実施例の断面図である。FIG. 1 is a cross-sectional view of a first embodiment of the present invention.
【図2】本発明の第2の実施例の断面図である。FIG. 2 is a sectional view of a second embodiment of the present invention.
【図3】従来の半導体装置の一例の断面図である。FIG. 3 is a cross-sectional view of an example of a conventional semiconductor device.
1 基板 2 配線 3 半導体チップ 4 金属線 5 樹脂 6 ハンダボール 7 金属被膜 1 substrate 2 wiring 3 semiconductor chip 4 metal wire 5 resin 6 solder ball 7 metal coating
Claims (3)
と、このガラスエポキシ樹脂基板に導電性接着剤で接着
された多数の接点パッドが形成された半導体チップと、
この半導体チップの前記接点パッドと前記ガラスエポキ
シ樹脂基板の前記配線とを接続する金線を含む金属線
と、前記半導体チップをコーティングする樹脂と、前記
ガラスエポキシ樹脂基板の裏面に設けられ実装基板に実
装するためのハンダホールとを有するボールグリッドア
レイパッケージの半導体装置において、前記ガラスエポ
キシ樹脂基板表面が露出しないように金属被膜にて被覆
されていることを特徴とする半導体装置。1. A glass epoxy resin substrate on which wiring is provided, and a semiconductor chip having a large number of contact pads bonded to the glass epoxy resin substrate with a conductive adhesive.
A metal wire including a gold wire connecting the contact pad of the semiconductor chip and the wiring of the glass epoxy resin substrate, a resin coating the semiconductor chip, and a mounting substrate provided on the back surface of the glass epoxy resin substrate. A semiconductor device of a ball grid array package having a solder hole for mounting, wherein the glass epoxy resin substrate surface is covered with a metal film so as not to be exposed.
と、樹脂の前記ガラスエポキシ樹脂基板との境界部とを
含んで被覆していることを特徴とする請求項1記載の半
導体装置。2. The semiconductor device according to claim 1, wherein the metal coating covers the glass epoxy resin substrate and a boundary portion between the resin and the glass epoxy resin substrate.
と樹脂との全表面を被覆していることを特徴とする請求
項1記載の半導体装置。3. The semiconductor device according to claim 1, wherein the metal coating covers the entire surfaces of the glass epoxy resin substrate and the resin.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7095461A JPH08288686A (en) | 1995-04-20 | 1995-04-20 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7095461A JPH08288686A (en) | 1995-04-20 | 1995-04-20 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH08288686A true JPH08288686A (en) | 1996-11-01 |
Family
ID=14138317
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7095461A Pending JPH08288686A (en) | 1995-04-20 | 1995-04-20 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH08288686A (en) |
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US6838748B2 (en) * | 2002-05-22 | 2005-01-04 | Sharp Kabushiki Kaisha | Semiconductor element with electromagnetic shielding layer on back/side face(s) thereof |
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US7829981B2 (en) | 2008-07-21 | 2010-11-09 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with electromagnetic interference shielding |
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US8093690B2 (en) | 2008-10-31 | 2012-01-10 | Advanced Semiconductor Engineering, Inc. | Chip package and manufacturing method thereof |
KR20120060486A (en) * | 2010-12-02 | 2012-06-12 | 삼성전자주식회사 | Stacked Package Structure |
TWI382519B (en) * | 2008-04-21 | 2013-01-11 | Advanced Semiconductor Eng | Electronic element packaging module by using a cap |
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