CN107658284B - Semiconductor package and method of manufacturing the same - Google Patents

Semiconductor package and method of manufacturing the same Download PDF

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Publication number
CN107658284B
CN107658284B CN201710898783.3A CN201710898783A CN107658284B CN 107658284 B CN107658284 B CN 107658284B CN 201710898783 A CN201710898783 A CN 201710898783A CN 107658284 B CN107658284 B CN 107658284B
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China
Prior art keywords
opening
inner diameter
semiconductor package
conductive layer
negative dielectric
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CN201710898783.3A
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Chinese (zh)
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CN107658284A (en
Inventor
蔡崇宣
谢爵安
约翰·R·杭特
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to CN201710898783.3A priority Critical patent/CN107658284B/en
Publication of CN107658284A publication Critical patent/CN107658284A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13008—Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape

Abstract

A semiconductor package and a method of manufacturing the same. The semiconductor package comprises a chip, a conductive layer, a negative dielectric layer and an electrical contact. The chip has an active surface. The conductive layer is electrically connected to the active surface. The negative dielectric layer covers the conductive layer and has an opening exposing a portion of the conductive layer, the opening having a minimum inner diameter, a top inner diameter, and a bottom inner diameter, the minimum inner diameter being between the bottom inner diameter and the top inner diameter. The electrical contact is formed in the opening.

Description

Semiconductor package and method of manufacturing the same
The present application is a divisional application of an invention patent application with an application number of "201310513715.2" entitled "semiconductor package and method for manufacturing the same", which is filed on 25.10.2013 by the applicant.
Technical Field
The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor package having an opening with a protruding inner sidewall and a method for manufacturing the same.
Background
The conventional semiconductor package at least includes a plurality of input/output contacts, through which the semiconductor package is electrically connected to an external circuit board. However, during the process of mounting the semiconductor package on the external circuit board, the input/output contact is stressed, so that the input/output contact is easily damaged, such as cracking, breaking or damaging.
Disclosure of Invention
The invention relates to a semiconductor package and a manufacturing method thereof, which can solve the problem that an output/input contact of the semiconductor package is easy to damage in the process of arranging the semiconductor package on another electronic element.
According to the present invention, a semiconductor package is provided. The semiconductor package comprises a chip, a conductive layer, a negative dielectric layer and an electrical contact. The chip is provided with an active surface. The conductive layer is electrically connected to the active surface. The negative dielectric layer covers the conductive layer and has an opening exposing a portion of the conductive layer, the opening having a minimum inner diameter, a top inner diameter, and a bottom inner diameter, the minimum inner diameter being between the bottom inner diameter and the top inner diameter. The electrical contact is formed in the opening.
According to the present invention, a method for manufacturing a semiconductor package is provided. The manufacturing method includes the following steps. Providing a chip, wherein the chip is provided with an active surface, a conductive layer is formed above the active surface of the chip, and the conductive layer is electrically connected with the active surface; forming a negative dielectric material to cover the conductive layer; providing a photomask, wherein the photomask comprises a light shielding part and a gray-scale light transmitting part, the light transmittance of the gray-scale light transmitting part is gradually increased from the light shielding part to the direction far away from the light shielding part, and the gray-scale light transmitting part defines the shape of an opening; irradiating a negative dielectric material through a mask with light to define the shape of the opening in the negative dielectric material; developing the negative dielectric material to form a negative dielectric layer with an opening, wherein the opening exposes a part of the conductive layer and has a minimum inner diameter, a top inner diameter and a bottom inner diameter, the minimum inner diameter is positioned between the bottom inner diameter and the top inner diameter, the area of the minimum inner diameter of the opening corresponds to the area of the light shielding part, and the area of the bottom inner diameter of the opening corresponds to the common area of the light shielding part and the gray-scale light transmitting part; and forming an electrical contact in the opening.
In order to make the aforementioned and other objects of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below:
drawings
Fig. 1 is a cross-sectional view of a semiconductor package according to an embodiment of the invention.
Fig. 2 is a cross-sectional view of a semiconductor package according to another embodiment of the invention.
Fig. 3 is a cross-sectional view of a semiconductor package according to another embodiment of the invention.
Fig. 4 is a cross-sectional view of a semiconductor package according to another embodiment of the invention.
Fig. 5A to 5E are process diagrams illustrating the semiconductor package of fig. 1.
Fig. 6 is a process diagram of the semiconductor package of fig. 3.
FIG. 7 is a graph illustrating transmittance of a mask according to another embodiment of the invention.
[ description of main element symbols ]
100. 200, 300, 400: semiconductor package
10: light shield
11: light shielding part
12: gray-scale light-transmitting part
110: chip and method for manufacturing the same
110 u: active surface
120: conductive layer
130: negative dielectric layer
130': negative dielectric material
130 a: opening holes
130a 1: opening of the container
130 w: inner side wall
130 u: upper surface of
131. 331: apertured tab
131 ', 132': part of the material
132: engaging recess
140: electrical contact
141: engaging part
142: projection part
C1, C2: dotted line
Db': region(s)
D L lower inside diameter
Dm: minimum inner diameter
And Dt: top inside diameter
Db: bottom inside diameter
H1, H2: length of protrusion
L light ray
S1: curve of light transmittance
ST1, ST 2: distribution of stress
T0: initial light transmittance
X0、XL: distance between two adjacent plates
Detailed Description
Referring to fig. 1, a cross-sectional view of a semiconductor package according to an embodiment of the invention is shown. The semiconductor package 100 includes a chip 110, a conductive layer 120, a negative dielectric layer 130, and at least one electrical contact 140.
The chip 110 has an active surface 110u, the conductive layer 120 is formed and electrically connected to the active surface 110u, the conductive layer 120 includes at least one pad and/or at least one trace, in one embodiment, the conductive layer 120 may be a Redistribution layer (Redistribution L layer, RD L) formed after the singulated chip 110 is redistributed on a carrier (not shown), in another embodiment, the conductive layer 120 may also be formed on a wafer (wafer) before the chip is singulated.
The negative dielectric layer 130 is an outermost structure or an outermost dielectric layer of the semiconductor package 100, covers the conductive layer 120 and has at least one opening 130 a. The opening 130a exposes a portion of the conductive layer 120, so that the electrical contact 140 is electrically connected to the exposed conductive layer 120.
Due to the negative photoresist characteristic of the negative dielectric layer 130, the opening 130a having the inner sidewall with a curved profile can be formed. In this embodiment, the inner sidewall 130w of the opening 130a protrudes toward the middle region of the opening 130a to form the opening protrusion 131. The opening projection 131 has a closed ring shape as viewed in a plan view. The opening protrusion 131 and the bottom inner diameter Db form a fastening recess 132 therebetween, and a portion of the material of the electrical contact 140 is fastened in the fastening recess 132, so as to prevent the electrical contact 140 from being easily separated from the opening 130a, thereby preventing the electrical contact 140 from being broken, and further improving reliability.
The opening 130a has a minimum inside diameter Dm, a top inside diameter Dt, and a bottom inside diameter Db. The minimum inside diameter Dm is between the bottom inside diameter Db and the top inside diameter Dt, which is the minimum inside diameter of the apertured protrusion 131. The bottom inner diameter Db refers to an inner diameter of the bottommost portion of the opening 130a, or an inner diameter of an area of the opening 130a where the conductive layer 120 is exposed. In the present embodiment, the inner diameter of the opening 130a is tapered from the bottom inner diameter Db to the minimum inner diameter Dm to form the opening protrusion 131 having a protrusion length H1.
In addition, during the developing process or the baking process, the material of the opening 130a1 adjacent to the opening 130a in the negative dielectric layer 130 shrinks and sinks, so that the inner diameter of the opening 130a gradually expands from the minimum inner diameter Dm to the top inner diameter Dt. The area of the opening 130a1 is enlarged due to shrinkage and sagging of the material of the negative dielectric layer 130 adjacent to the opening 130a 1. Thus, during the process of forming the electrical contact 140, the electrical contact 140 in a flowing state can easily enter the opening 130a through the enlarged opening 130a 1. In this embodiment, the top inner diameter Dt is substantially equal to the bottom inner diameter Db; in another embodiment, the transmittance curve S1 of the mask 10 (FIG. 5B or FIG. 7) can be designed such that the top inner diameter Dt is greater than or less than the bottom inner diameter Db.
The electrical contacts 140 are output or input contacts of the semiconductor package 100. The electrical contacts 140 are solder balls, for example. In the process of fabricating the electrical contact 140, ball-shaped solder can be formed in the opening 130a by using, for example, a ball-planting technique, and then the ball-shaped solder is solidified by reflow process (reflow) to form the electrical contact 140. In another embodiment, the electrical contacts 140 may also be conductive pillars and bumps.
The electrical contacts 140 are electrically connected to the conductive layer 120 through the openings 130 a. The electrical contact 140 includes an engaging portion 141 and a protruding portion 142, wherein the engaging portion 141 is formed in the opening 130a, and the protruding portion 142 protrudes from the opening 130 a. Part of the material of the engaging portion 141 is engaged in the engaging recess 132, so that the electrical contact 140 is constrained by the opening protrusion 131 of the negative dielectric layer 130 and is more stably formed in the opening 130 a. In terms of stress distribution, if the opening protrusion 131 is omitted, the maximum stress distribution ST1 borne by the electrical contact 140 is relatively close to the contact surface between the electrical contact 140 and the conductive layer 120. In contrast to the embodiment of the present invention, when the electrical contact 140 is stressed (for example, when the semiconductor package 100 is disposed on another semiconductor package, a substrate or a circuit board with the electrical contact 140), the opening protrusion 131 can share the stress of the electrical contact 140, so that the maximum stress distribution ST2 borne by the electrical contact 140 is distributed toward the opening protrusion 131, and the stress on the contact surface between the electrical contact 140 and the conductive layer 120 can be reduced. Thus, the electrical contact 140 is prevented from being easily damaged after being stressed, and the reliability of the electrical contact 140 can be improved.
Although the number of the electrical contacts 140 of the semiconductor package 100 of the present embodiment is illustrated as one, the number may be two or more.
Referring to fig. 2, a cross-sectional view of a semiconductor package according to another embodiment of the invention is shown. The semiconductor package 200 includes a chip 110, a conductive layer 120, a negative dielectric layer 130, and an electrical contact 140. The negative dielectric layer 130 has at least one opening 130a, and the opening 130a exposes a portion of the conductive layer 120.
The inner sidewall 130w of the opening 130a protrudes toward the middle region of the opening 130a to form an opening protrusion 131. Compared to fig. 1, the protrusion length H2 of the opening protrusion 131 of the present embodiment is shorter than the protrusion length H1 of the opening protrusion 131 of fig. 2, so that the volume of the opening 130a can be increased to accommodate more material of the electrical contact 140. The shorter opening protrusions 131 of the present embodiment can be achieved by designing the transmittance of the mask, which will be described later in the process description.
Referring to fig. 3, a cross-sectional view of a semiconductor package according to another embodiment of the invention is shown. The semiconductor package 300 includes a chip 110, a conductive layer 120, a negative dielectric layer 130, and an electrical contact 140. The negative dielectric layer 130 has at least one opening 130a, and the opening 130a exposes a portion of the conductive layer 120.
In this embodiment, the opening 130a has a lower inner diameter DLBetween the location of the bottom inside diameter Db and the location of the smallest inside diameter Dm. The inner diameter of the opening 130a is from the bottom inner diameter Db to the lower inner diameter DLIs gradually enlarged from the lower inner diameter DLThe inner wall 130w of the opening 130a forms two opening protrusions 131 and 331 by tapering toward the minimum inner diameter Dm, wherein a fastening recess 132 is formed between the two opening protrusions 131 and 331. The engaging portion 141 of the electrical contact 140 is formed in the engaging recess 132, so that the electrical contact 140 is more stably formed in the opening 130 a.
Referring to fig. 4, a cross-sectional view of a semiconductor package according to another embodiment of the invention is shown. The semiconductor package 400 includes a chip 110, a conductive layer 120, a negative dielectric layer 130, and an electrical contact 140. The negative dielectric layer 130 has at least one opening 130a exposing the conductive layer 120.
In the present embodiment, the inner sidewall 130w of the opening 130a is a planar wall extending toward the upper surface 130u of the negative dielectric layer 130. The opening 130a has a minimum inside diameter Dm, a top inside diameter Dt, and a bottom inside diameter Db. The bore 130a tapers from the bottom inner diameter Db to the minimum inner diameter Dm to form a bore protrusion 131. During the developing process or the baking process, the material of the opening 130a1 adjacent to the opening 130a in the negative dielectric layer 130 shrinks and sinks, so that the inner diameter of the opening 130a gradually expands from the minimum inner diameter Dm to the top inner diameter Dt.
In another embodiment, the inner sidewalls 130w of the opening 130a may be inner sidewalls having a parabolic profile. However, the inner sidewall 130w of the opening 130a having the opening protrusion 131 formed by the negative dielectric layer 130 may have any geometric profile, such as a geometric profile composed of a plane, a curved surface, or a combination thereof.
Referring to fig. 5A to 5E, a process of manufacturing the semiconductor package of fig. 1 is illustrated.
As shown in fig. 5A, a chip 110 is provided, the chip 110 having an active face 110 u. A conductive layer 120 is formed on the active surface 110u of the chip 110, and the conductive layer 120 is electrically connected to the active surface 110 u.
A negative dielectric material 130' is formed overlying the conductive layer 120 using, for example, a coating technique. The negative dielectric material 130' is a photosensitive material, and a portion of the irradiated material remains on the product while another portion of the non-irradiated material is removed during the development process. The coating technique is, for example, printing (printing), spin coating (spinning) or spray coating (spraying).
As shown in fig. 5B, a mask 10 is provided. The mask 10 is, for example, a gray-scale mask having a variable light transmittance. Specifically, the mask 10 includes a light-shielding portion 11 and a gray-scale light-transmitting portion 12, wherein the gray-scale light-transmitting portion 12 is connected to the light-shielding portion 11. With the center of the light shielding portion 11 of the mask 10 as a starting point (X is 0), X is between-X0To X0Is defined as the light shielding portion 11 of the mask 10, and X is between X0To XLIs defined as a gray-scale light-transmitting portion 12 of the mask 10. The change in transmittance of the gray-scale light-transmitting portion 12 may define the shape of the opening 130a (fig. 5C).
The gray-scale light-transmitting portion 12 has different light transmittances in at least two parts. For example, the light transmittance of the gray-scale light-transmitting portion 12 of the present embodiment increases from the light-shielding portion 11 to a direction away from the light-shielding portion 11However, the embodiment of the invention is not limited thereto. In this example, the initial transmittance T0(x＝X0Where) about 40%, and the farther from the light shielding portion 11, the greater the light transmittance of the grayscale light-transmitting portion 12, until X ═ XLHere, the light transmittance was 100%. In another embodiment, the initial transmittance T0And may be less than or greater than 40%. In addition, X is between + XLand-XLThe region Db' (combined region of the light-shielding portion 11 and the gray-scale light-transmitting portion 12) between them defines the range of the bottom inner diameter Db (fig. 5D) of the opening 130 a. That is, the dimension of the bottom inner diameter Db of the opening 130a can be defined by designing the dimension of the region Db' of the mask 10.
In this embodiment, the transmittance curve S1 of the gray-scale light-transmitting portion 12 of the mask 10 is symmetrical with respect to the center of the light-shielding portion 11, such that the inner sidewall profile of the formed opening 130a is substantially symmetrical with respect to the center of the opening 130 a. However, not limiting the embodiment of the invention, in another embodiment, the transmittance curve S1 of the gray-scale transmissive portion 12 is asymmetric with respect to the center position of the light shielding portion 11, that is, the two gray-scale transmissive portions 12 at two sides of the light shielding portion 11 have different transmittance curves S1, so that the inner sidewall profile of the formed opening 130a is also asymmetric with respect to the center position of the opening 130 a.
As shown in fig. 5C, the negative dielectric material 130 'is irradiated by a light L through the mask 10. as shown by a dotted line C1 in fig. 5C, a portion 131' of the negative dielectric material 130 'is irradiated by the light L, while another portion 132' (the area inside the dotted line) is not irradiated by the light L, wherein the portion 132 'not irradiated by the light L can be removed in the subsequent developing process, and the portion 131' irradiated by the light L remains in the developing process.
As shown in fig. 5D, a portion 132 ' (fig. 5C) of the negative dielectric material 130 ' not exposed to the light is removed by, for example, a developing process to form the negative dielectric material 130, wherein the opening 130a is formed in the removed portion 132 '. During the developing process, the upper surface 130u of the negative dielectric material 130 'adjacent to the opening 130a1 of the opening 130a may sag due to shrinkage, thereby causing the top inner diameter Dt' of the opening 130a1 of the opening 130a to expand. Thus, during the process of forming the electrical contact 140, the electrical contact 140 in a flowing state can easily enter the opening 130a through the enlarged opening 130a 1.
As shown in fig. 5E, the negative dielectric layer 130 is baked to cure the negative dielectric layer 130. During the baking process, the material of the opening 130a1 of the negative dielectric layer 130 adjacent to the opening 130a contracts again, and the upper surface 130u of the opening 130a1 of the negative dielectric layer 130' adjacent to the opening 130a sinks due to the contraction again, thereby causing the opening 130a1 of the opening 130a to expand again. For example, from dashed line C2, to the inner sidewall 130w of solid line aperture 130a, and the top inner diameter Dt' (of the figure) expands to Dt.
Then, the electrical contacts 140 may be formed in the openings 130 a.
The manufacturing method of the semiconductor package 200 of fig. 2 is similar to the manufacturing method of the semiconductor package 100, except that the initial transmittance T of the mask 10 used to form the opening 130a of the semiconductor package 200 is set0(x＝L0Where) is lower than the initial transmittance T of the mask 10 used to form the opening 130a of the semiconductor package 1000High, and thus a shorter apertured protrusion 131 may be formed. Further, the initial transmittance T can be designed0To form apertured projections 131 of different projection lengths. In addition, by designing the transmittance profile of the mask 10, the inner sidewall 130w of the opening 130a can be formed with different geometric profiles.
Referring to fig. 6, a process diagram of manufacturing the semiconductor package of fig. 3 is shown. In this embodiment, the range of the conductive layer 120 is larger than the range of the gray-scale light-transmitting portion 12 of the mask 10 (X is 0 to X)LX is shown in fig. 5B), such that the light ray L irradiated to the conductive layer 120 irradiates the negative dielectric material 130' after being reflected by the conductive layer 120, and the negative dielectric material irradiated by the reflected light remains after the developing process, thereby forming the opening protrusion 331 (fig. 3).
Referring to fig. 7, a graph of transmittance of a mask according to another embodiment of the invention is shown. The transmittance curve S1 of the mask 10 may be composed of straight lines, curved lines or a combination thereof to form the opening 130a having the inner sidewall 130w with corresponding profile, such as the opening 130a of the semiconductor packages 300 and 400.
While the invention has been described with reference to the preferred embodiments, it is to be understood that the invention is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention should be determined by the appended claims.

Claims (5)

1. A semiconductor package, comprising:
a chip having an active surface;
a conductive layer electrically connected to the active surface;
a negative dielectric layer covering the conductive layer and having an opening exposing a portion of the conductive layer, the opening having a minimum inner diameter, a top inner diameter, a lower inner diameter between the bottom inner diameter and the top inner diameter, and a bottom inner diameter between the bottom inner diameter and the minimum inner diameter; and
an electrical contact formed in the opening, wherein the inner diameter of the opening gradually expands from the inner diameter of the bottom portion to the inner diameter of the lower portion and gradually decreases from the inner diameter of the lower portion to the minimum inner diameter.
2. The semiconductor package according to claim 1, wherein the opening has an inner diameter that tapers from the minimum inner diameter to the top inner diameter.
3. The semiconductor package according to claim 1, wherein the top inner diameter is larger than the bottom inner diameter.
4. The semiconductor package according to claim 1, wherein the inner sidewall of the opening is a planar wall.
5. The semiconductor package according to claim 1, wherein the inner sidewall of the opening is a curved wall.
CN201710898783.3A 2013-10-25 2013-10-25 Semiconductor package and method of manufacturing the same Active CN107658284B (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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KR100430203B1 (en) * 1999-10-29 2004-05-03 가부시키가이샤 히타치세이사쿠쇼 Semiconductor device and manufacturing method of the same
JP3863161B2 (en) * 2004-01-20 2006-12-27 松下電器産業株式会社 Semiconductor device
US20050260790A1 (en) * 2004-05-24 2005-11-24 Goodner Michael D Substrate imprinting techniques
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CN103247569B (en) * 2012-02-14 2018-04-10 联华电子股份有限公司 Wear the preparation method and structure of silicon conducting body
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