CN104576576B - Semiconductor package assembly and a manufacturing method thereof - Google Patents

Semiconductor package assembly and a manufacturing method thereof Download PDF

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Publication number
CN104576576B
CN104576576B CN201310513715.2A CN201310513715A CN104576576B CN 104576576 B CN104576576 B CN 104576576B CN 201310513715 A CN201310513715 A CN 201310513715A CN 104576576 B CN104576576 B CN 104576576B
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China
Prior art keywords
perforate
diameter
inner diameter
negative dielectric
semiconductor package
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CN201310513715.2A
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Chinese (zh)
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CN104576576A (en
Inventor
蔡崇宣
谢爵安
约翰·R·杭特
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to CN201310513715.2A priority Critical patent/CN104576576B/en
Priority to CN201710898783.3A priority patent/CN107658284B/en
Publication of CN104576576A publication Critical patent/CN104576576A/en
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13008—Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape

Abstract

A kind of semiconductor package assembly and a manufacturing method thereof.Semiconductor package part includes chip, conductive layer, negative dielectric layer and electrical contact.Chip has active surface.Conductive layer is electrically connected at active surface.Negative dielectric layer covers conductive layer and with perforate, and a part for conductive layer is exposed in perforate, and perforate has minimum diameter, top internal diameter and bottom inner diameter, and minimum diameter is located between bottom inner diameter and top internal diameter.Electrical contact is formed in perforate.

Description

Semiconductor package assembly and a manufacturing method thereof
Technical field
Have the invention relates to a kind of semiconductor package assembly and a manufacturing method thereof, and in particular to its a kind of perforate There is the semiconductor package assembly and a manufacturing method thereof of prominent madial wall.
Background technology
Traditional semiconductor package part at least includes several defeated in/out contacts, and semiconductor package part can be made a little defeated by this In/out contact is electrically connected at a external circuit board.However, semiconductor package part is located at during the external circuit board, defeated in/out Contact can stress and cause defeated in/out contact to be easily destroyed, such as cracking, fracture or damage.
The content of the invention
The present invention is related to a kind of semiconductor package assembly and a manufacturing method thereof, can improve semiconductor package part located at another electricity During subcomponent, the problem of its defeated in/out contact is easily destroyed.
According to the present invention it is proposed that a kind of semiconductor package part.Semiconductor package part includes a chip, a conductive layer, one negative Type dielectric layer and an electrical contact.Chip has an active surface.Conductive layer is electrically connected at active surface.Negative dielectric layer covering is led Electric layer and with a perforate, a part for conductive layer is exposed in perforate, and perforate has a minimum diameter, a top internal diameter and a bottom Internal diameter, minimum diameter is located between bottom inner diameter and top internal diameter.Electrical contact is formed in perforate.
According to the present invention it is proposed that a kind of manufacture method of semiconductor package part.Manufacture method comprises the following steps.There is provided one Chip, chip, which has, is formed with a conductive layer above an active surface, and the active surface of chip, conductive layer is electrically connected at actively Face；Form negative dielectric material covering conductive layer；A light shield is provided, light shield includes a light shielding part and a GTG transmittance section, ash The light transmittance of rank transmittance section is cumulative toward the direction away from light shielding part from light shielding part, and GTG transmittance section defines the profile of a perforate；Make Negative dielectric material is irradiated through light shield with light, with the profile of the perforate defined in the negative dielectric material；To the minus Dielectric material carries out developing manufacture process, has the negative dielectric layer of perforate to form one, a part for conductive layer is exposed in wherein perforate, And perforate has a minimum diameter, a top internal diameter and a bottom inner diameter, minimum diameter be located at bottom inner diameter and top internal diameter it Between, the region of the region correspondence light shielding part of the minimum diameter of perforate, and the region of the bottom inner diameter of perforate correspondence light shielding part and ash The common region of rank transmittance section；And, an electrical contact is formed in perforate.
For the above of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate appended accompanying drawing, make Describe in detail as follows：
Brief description of the drawings
Fig. 1 illustrates the sectional view of the semiconductor package part according to one embodiment of the invention.
Fig. 2 illustrates the sectional view of the semiconductor package part according to another embodiment of the present invention.
Fig. 3 illustrates the sectional view of the semiconductor package part according to another embodiment of the present invention.
Fig. 4 illustrates the sectional view of the semiconductor package part according to another embodiment of the present invention.
Fig. 5 A to 5E illustrate the process drawing of Fig. 1 semiconductor package part.
Fig. 6 illustrates the process drawing of Fig. 3 semiconductor package part.
Fig. 7 illustrates the light transmittance curve figure of the light shield according to another embodiment of the present invention.
【Main element symbol description】
100、200、300、400：Semiconductor package part
10：Light shield
11：Light shielding part
12：GTG transmittance section
110：Chip
110u：Active surface
120：Conductive layer
130：Negative dielectric layer
130’：Negative dielectric material
130a：Perforate
130a1：Opening
130w：Madial wall
130u：Upper surface
131、331：Perforate protuberance
131’、132’：Portion of material
132：Engaging recessed part
140：Electrical contact
141：Holding section
142：Protuberance
C1、C2：Dotted line
Db'：Region
DL：Lower inner diameter
Dm：Minimum diameter
Dt：Top internal diameter
Db：Bottom inner diameter
H1、H2：Prominent length
L：Light
S1：Light transmittance curve
ST1、ST2：Stress distribution
T0：Initial light transmission
X0、XL：Distance
Embodiment
Fig. 1 is refer to, it illustrates the sectional view of the semiconductor package part according to one embodiment of the invention.Semiconductor package part 100 include chip 110, conductive layer 120, negative dielectric layer 130 and at least one electrical contact 140.
Chip 110 has active surface 110u, and conductive layer 120 forms and is electrically connected at active surface 110u.Conductive layer 120 is wrapped Include an at least connection pad and/or an at least cabling.In one embodiment, conductive layer 120 can reroute road floor （Redistribution Layer,RDL）, it redistributes the shape after on support plate (not illustrating) for the chip 110 after unification Into.In another embodiment, conductive layer 120 can be also formed on wafer (wafer) before chip unification.
Negative dielectric layer 130 is the outermost Rotating fields or outermost layer dielectric layer of semiconductor package part 100, and it covers conductive layer 120 and with an at least perforate 130a.Perforate 130a exposes a part for conductive layer 120, can be electrically connected with electrical contact 140 In the conductive layer 120 exposed.
Due to the minus photoresistance characteristic of negative dielectric layer 130, therefore the perforate of the madial wall with curved surface profile can be formed 130a.In the present embodiment, perforate 130a madial wall 130w is protruded toward perforate 130a intermediate region, and forms perforate protuberance 131.Looked toward overlook direction, perforate protuberance 131 is in closed ring.Formed between perforate protuberance 131 and bottom inner diameter Db Engaging recessed part 132, the portion of material of electrical contact 140 is blocked in engaging recessed part 132, and electrical contact 140 can be avoided to take off easily Hole 130a is left, and then avoids causing electrical contact 140 to be broken, reliability is further lifted.
Perforate 130a has minimum diameter Dm, top internal diameter Dt and bottom inner diameter Db.Minimum diameter Dm is located at bottom inner diameter Between Db and top internal diameter Dt, it is the minimum diameter of perforate protuberance 131.Bottom inner diameter Db refers to perforate 130a most bottom The internal diameter in portion, or can say be the region for exposing conductive layer 120 in perforate 130a internal diameter.In the present embodiment, perforate 130a's is interior Footpath is tapered toward the direction in place of minimum diameter Dm in place of bottom inner diameter Db, and constitutes perforate protuberance 131, and it has one to protrude Length H1.
In addition, in developing manufacture process or baking processing procedure, adjacent openings 130a opening 130a1 in negative dielectric layer 130 Material shrinkage sink, and makes perforate 130a internal diameter in place of minimum diameter Dm toward the direction flaring in place of top internal diameter Dt.Due to Adjacent openings 130a1 Material shrinkage sink in negative dielectric layer 130, expands opening 130a1 area.Consequently, it is possible to In the processing procedure for forming electrical contact 140, it can be easily accessible in the electrical contact 140 of flowable state by this opening 130a1 expanded In perforate 130a.In the present embodiment, top internal diameter Dt is approximately equal to bottom inner diameter Db；, can be by design in another embodiment The light transmittance curve S1 of light shield 10 (Fig. 5 B or Fig. 7), makes top internal diameter Dt be more than or less than bottom inner diameter Db.
Output or input contact of the electrical contact 140 for semiconductor package part 100.Electrical contact 140 is, for example, soldered ball. , can be using being, for example, to plant the glomerate tin solder of playing skill art shape in perforate 130a, then in the manufacture craft of electrical contact 140 Solidify tin solder by back welding process (reflow) again, and form electrical contact 140.In another embodiment, electrical contact 140 Can be conductive pole and projection.
Electrical contact 140 is electrically connected at conductive layer 120 by perforate 130a.Electrical contact 140 include holding section 141 and Protuberance 142, wherein holding section 141 is formed in perforate 130a, and protuberance 142 protrudes from perforate 130a.Holding section 141 Portion of material is sticked in engaging recessed part 132, electrical contact 140 is arrested by the perforate protuberance 131 of negative dielectric layer 130 Beam, and be more securely formed in perforate 130a.For stress distribution, if omitting perforate protuberance 131, electrical contact Contact surface between the 140 maximum stress distribution fairly close electrical contacts 140 of ST1 born and conductive layer 120.Review the present invention Embodiment, (is, for example, that semiconductor package part 100 is located at another semiconductor package with electrical contact 140 when 140 stress of electrical contact In piece installing, substrate or circuit boards), perforate protuberance 131 can share the stress of electrical contact 140, hold electrical contact 140 The maximum stress received is distributed ST2 toward the directional spreding of perforate protuberance 131, and then can reduce electrical contact 140 and conductive layer 120 Contact surface stress.In this way, can avoid that the reliable of electrical contact 140 is easily destroyed and can lifted after the stress of electrical contact 140 Degree.
Although the quantity of the electrical contact 140 of the semiconductor package part 100 of the present embodiment be exemplified by one illustrate, so its Quantity can also be two or more than two.
Fig. 2 is refer to, it illustrates the sectional view of the semiconductor package part according to another embodiment of the present invention.Semiconductor packages Part 200 includes chip 110, conductive layer 120, negative dielectric layer 130 and electrical contact 140.Negative dielectric layer 130 has at least one Perforate 130a, perforate 130a exposed portion conductive layer 120.
Perforate 130a madial wall 130w is protruded toward perforate 130a intermediate region, and forms perforate protuberance 131.Compare In Fig. 1, the prominent length H1 of perforate protuberances 131 of the prominent length H2 than Fig. 2 of the perforate protuberance 131 of the present embodiment is short, Perforate 130a volume can so be increased, to accommodate the material of more electrical contacts 140.The shorter perforate of the present embodiment is protruded Portion 131 can by design light shield light transmittance complete, this hold after processing procedure explanation described in.
Fig. 3 is refer to, it illustrates the sectional view of the semiconductor package part according to another embodiment of the present invention.Semiconductor packages Part 300 includes chip 110, conductive layer 120, negative dielectric layer 130 and electrical contact 140.Negative dielectric layer 130 has at least one Perforate 130a, perforate 130a exposed portion conductive layer 120.
In the present embodiment, perforate 130a has lower inner diameter DL, its in place of the bottom inner diameter Db with minimum diameter Dm it Between.Perforate 130a internal diameter is from bottom inner diameter Db toward lower inner diameter DLDirection flaring, then from lower inner diameter DLToward minimum Internal diameter Dm direction is tapered, so makes perforate 130a madial wall 130w two perforate protuberances 131 and 331 of formation, wherein perforate Engaging recessed part 132 is formed between protuberance 131 and 331.The holding section 141 of electrical contact 140 is formed in engaging recessed part 132, Electrical contact 140 is set more securely to be formed in perforate 130a.
Fig. 4 is refer to, it illustrates the sectional view of the semiconductor package part according to another embodiment of the present invention.Semiconductor packages Part 400 includes chip 110, conductive layer 120, negative dielectric layer 130 and electrical contact 140.Negative dielectric layer 130 has at least one Perforate 130a exposes conductive layer 120.
In the present embodiment, perforate 130a madial wall 130w is a planar wall, and it is toward the upper surface of negative dielectric layer 130 130u direction extension.Perforate 130a has minimum diameter Dm, top internal diameter Dt and bottom inner diameter Db.Perforate 130a internal diameter from Direction in place of bottom inner diameter Db toward minimum diameter Dm is tapered, and forms perforate protuberance 131.In developing process or baking process In, adjacent openings 130a opening 130a1 Material shrinkage sink in negative dielectric layer 130, makes perforate 130a internal diameters from minimum Toward the direction flaring in place of top internal diameter Dt in place of internal diameter Dm.
In another embodiment, perforate 130a madial wall 130w can be the madial wall with Throwing thing line profiles.However, only If the perforate 130a with perforate protuberance 131 formed using negative dielectric layer 130, its madial wall 130w can have Any geometric profile, as by plane, curved surface or the constituted geometric profile of its combination.
Fig. 5 A to 5E are refer to, it illustrates the process drawing of Fig. 1 semiconductor package part.
As shown in Figure 5A there is provided chip 110, chip 110 has active surface 110u.Above the active surface 110u of chip 110 Conductive layer 120 is formed with, conductive layer 120 is electrically connected at active surface 110u.
Using e.g. coating technique, form negative dielectric material 130 ' and cover conductive layer 120.Negative dielectric material 130 ' For a light-sensitive material, the portion of material of its irradiation can be retained on product, and another part material of non-irradiation is in developing manufacture process In be removed.Above-mentioned coating technique is, for example, printing（printing）, spin coating（spinning）Or spraying（spraying）.
There is provided light shield 10 as shown in Figure 5 B.Light shield 10 is, for example, gray-level mask, and it has the light transmittance of change.It is specific next Say, light shield 10 includes light shielding part 11 and GTG transmittance section 12, the wherein connection of GTG transmittance section 12 light shielding part 11.With the screening of light shield 10 For the center in light portion 11 is as starting point (x=0), x is between-X0To X0Part be defined as the light shielding part 11 of light shield 10, and x is situated between In X0To XLPart be defined as the GTG transmittance section 12 of light shield 10.The light transmittance change definable perforate of GTG transmittance section 12 130a (5C figures) profile.
The local light transmittance of at least the two of GTG transmittance section 12 is different.For example, the GTG transmittance section 12 of the present embodiment is saturating Light rate is cumulative toward the direction away from light shielding part 11 from light shielding part 11, and the right embodiment of the present invention is not limited.In the present embodiment, initially Light transmittance T0(x=X0Place) about 40%, and it is bigger further away from the light transmittance of the then GTG transmittance section 12 of light shielding part 11, until x=XLIt Place, its light transmittance is 100%.In another embodiment, initial light transmission T040% can be less than or greater than.In addition, x is between+XLWith- XLBetween the region Db ' combination zone of GTG transmittance section 12 (light shielding part 11 with) define perforate 130a bottom inner diameter Db (figures Scope 5D).That is, can go to define perforate 130a bottom inner diameter Db by the region Db ' for designing light shield 10 size Size.
In the present embodiment, centers pair of the light transmittance curve S1 with respect to light shielding part 11 of the GTG transmittance section 12 of light shield 10 Claim, so make the perforate 130a formed according to this center of the medial side wall profiles with respect to perforate 130a generally in symmetrical.So This is not used to limit in the embodiment of the present invention, another embodiment, and the light transmittance curve S1 of GTG transmittance section 12 is with respect to light shielding part 11 Center it is asymmetric, i.e. positioned at the side of light shielding part 11 2 two GTG transmittance sections 12 have different light transmittance curve S1, such as This, the perforate 130a formed according to this center of the medial side wall profiles with respect to perforate 130a is also asymmetric.
As shown in Figure 5 C, with light L through the irradiation negative dielectric of light shield 10 material 130 '.As shown in Fig. 5 C dotted line C1, The portion of material 131 ' of negative dielectric material 130 ' is irradiated by light L, and (the area inside dotted line of another part material 132 ' Domain) light L irradiations are not affected by, wherein being not affected by the portion of material 132 ' of light L irradiations can remove in follow-up developing manufacture process, And the portion of material 131 ' irradiated by light L then retains in developing manufacture process.In addition, the light transmittance of GTG transmittance section 12 is bigger Region, stronger light can be allowed to pass through, and be irradiated to the material of more or deeper negative dielectric material 130 '.
As shown in Figure 5 D, can be using e.g. developing manufacture process, remove negative dielectric material 130 ' is not affected by light irradiation Portion of material 132 ' (Fig. 5 C), to form negative dielectric layer 130, wherein the part of removed portion of material 132 ' forms perforate 130a.In developing manufacture process, in negative dielectric material 130 ' adjacent openings 130a opening 130a1 upper surface 130u can because Shrink and sink, thus cause perforate 130a opening 130a1 top internal diameter Dt ' to expand.Consequently, it is possible to be electrically connected with formation In the processing procedure of point 140, it can be easily accessible in the electrical contact 140 of flowable state by this opening 130a1 expanded in perforate 130a.
As shown in fig. 5e, baking negative dielectric layer 130, to solidify negative dielectric layer 130.In baking processing procedure, minus is situated between The adjacent openings 130a of electric layer 130 opening 130a1 material can shrink once again, adjacent openings in negative dielectric material 130 ' 130a opening 130a1 upper surface 130u can sink because of shrinking once again, and then cause perforate 130a opening 130a1 again It is secondary to expand.For example, the perforate 130a of solid line madial wall 130w is retracted to from dotted line C2, and top internal diameter Dt ' (figure) is extended to Dt。
Then, electrical contact 140 can be formed in perforate 130a.
The manufacture method of Fig. 2 semiconductor package part 200 is similar to the manufacture method of semiconductor package part 100, different It is to form the initial light transmission T of light shield 10 that the perforate 130a of semiconductor package part 200 is used0(x=L0Place) partly led than being formed The initial light transmission T for the light shield 10 that the perforate 130a of body packaging part 100 is used0Height, therefore shorter perforate protrusion can be formed Portion 131.Further say, can be by design initial light transmission T0Value form the perforate protuberance 131 of different prominent lengths. In addition, by the light transmittance distribution curve of design light shield 10, perforate 130a madial wall 130w can be made to form different geometric profiles.
Fig. 6 is refer to, it illustrates the process drawing of Fig. 3 semiconductor package part.In the present embodiment, the model of conductive layer 120 Enclose scope (x=0~X of the GTG transmittance section 12 more than light shield 10L, x is illustrated in Fig. 5 B), make the light for being irradiated to conductive layer 120 The negative dielectric material 130 ' that L is irradiated to after being reflected by conductive layer 120, and then make the negative dielectric material that is irradiated to by reflected light Expect in being remained after developing manufacture process, and form perforate protuberance 331 (Fig. 3).
Fig. 7 is refer to, it illustrates the light transmittance curve figure of the light shield according to another embodiment of the present invention.The printing opacity of light shield 10 Rate curve S1 can by straight line, curve or its constituted, with formed with correspondence profile madial wall 130w perforate 130a, such as above-mentioned semiconductor package part 300 and 400 perforate 130a.
In summary, although the present invention is disclosed above with preferred embodiment, so it is not limited to the present invention.This hair Bright those of ordinary skill in the art, without departing from the spirit and scope of the present invention, when can make it is various change with Retouching.Therefore, protection scope of the present invention is worked as and is defined depending on the appended claims person of defining.

Claims (11)

1. a kind of semiconductor package part, including：
One chip, with an active surface；
One conductive layer, is electrically connected at the active surface；
One has the negative dielectric layer of minus photoresistance characteristic, covers the conductive layer and with a perforate, the conduction is exposed in the perforate A part for layer, the perforate has a minimum diameter, a top internal diameter and a bottom inner diameter, and the minimum diameter is located in the bottom Between footpath and the top internal diameter, the perforate with develop or roasting mode be formed at minus photoresistance characteristic a negative dielectric layer In；And
One electrical contact, is formed in the perforate.
2. semiconductor package part as claimed in claim 1, it is characterised in that the internal diameter of the perforate is past in place of the bottom inner diameter Direction in place of the minimum diameter is tapered.
3. semiconductor package part as claimed in claim 1, it is characterised in that the internal diameter of the perforate is past in place of the minimum diameter Direction flaring in place of the top internal diameter.
4. semiconductor package part as claimed in claim 1, it is characterised in that the perforate has in a lower inner diameter, the bottom In place of footpath in place of the bottom inner diameter and between the minimum diameter, the internal diameter of the perforate is from the bottom inner diameter toward the bottom The direction flaring of internal diameter and direction from the lower inner diameter toward the minimum diameter is tapered.
5. semiconductor package part as claimed in claim 1, it is characterised in that the top internal diameter is more than the bottom inner diameter.
6. semiconductor package part as claimed in claim 1, it is characterised in that the madial wall of the perforate is a planar wall.
7. semiconductor package part as claimed in claim 1, it is characterised in that the madial wall of the perforate is a curved wall.
8. a kind of manufacture method of semiconductor package part, including：
A chip is provided, the chip has is formed with a conductive layer above an active surface, and the active surface of the chip, the conduction Layer is electrically connected at the active surface；
Form a negative dielectric material and cover the conductive layer；
A light shield is provided, the light shield includes a light shielding part and a GTG transmittance section, the light transmittance of the GTG transmittance section is from the shading Portion is cumulative toward the direction away from the light shielding part, and the GTG transmittance section defines the profile of a perforate；
The negative dielectric material is irradiated through the light shield using light, with the outer of the perforate defined in the negative dielectric material Shape；
Developing manufacture process is carried out to the negative dielectric material, there is the negative dielectric layer of the perforate to form one, the wherein perforate is revealed Go out a part for the conductive layer, and the perforate has a minimum diameter, a top internal diameter and a bottom inner diameter, minimum diameter position Between the bottom inner diameter and the top internal diameter, the region of the minimum diameter of the perforate to should light shielding part region, and be somebody's turn to do The region of the bottom inner diameter of perforate to should light shielding part and the GTG transmittance section combination zone；And
An electrical contact is formed in the perforate.
9. manufacture method as claimed in claim 8, it is characterised in that the scope of the conductive layer is more than the model of the GTG transmittance section Enclose；In the step of irradiating the negative dielectric material through the light shield using light, the light of the conductive layer is irradiated to anti- Negative dielectric material being irradiated to after penetrating so that in the step of carrying out developing manufacture process to the negative dielectric material, the perforate A lower inner diameter is formed, in place of the lower inner diameter in place of the bottom inner diameter and between the minimum diameter, the perforate Direction flaring of the internal diameter from the bottom inner diameter toward the lower inner diameter and direction from the lower inner diameter toward the minimum diameter is tapered.
10. manufacture method as claimed in claim 8, it is characterised in that further include：
Negative dielectric layer is toasted, and expands the top internal diameter.
11. manufacture method as claimed in claim 8, it is characterised in that the light transmittance curve of the light shield by straight line, curve or its Constituted.
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