CN104576425A - Single-layer substrate packaging process - Google Patents

Single-layer substrate packaging process Download PDF

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Publication number
CN104576425A
CN104576425A CN201410779648.3A CN201410779648A CN104576425A CN 104576425 A CN104576425 A CN 104576425A CN 201410779648 A CN201410779648 A CN 201410779648A CN 104576425 A CN104576425 A CN 104576425A
Authority
CN
China
Prior art keywords
pad
layer substrate
single layer
substrate packaging
packaging technology
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410779648.3A
Other languages
Chinese (zh)
Inventor
黄超
王洪辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nantong Fujitsu Microelectronics Co Ltd
Original Assignee
Nantong Fujitsu Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nantong Fujitsu Microelectronics Co Ltd filed Critical Nantong Fujitsu Microelectronics Co Ltd
Priority to CN201410779648.3A priority Critical patent/CN104576425A/en
Publication of CN104576425A publication Critical patent/CN104576425A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

The invention relates to a single-layer substrate packaging process, which comprises the following steps: forming lower parts of pads on the upper surface of a laminated copper foil; laminating a first glass fiber layer between the lower parts of adjacent pads; coaxially forming upper parts of the pads on the lower parts of the pads, wherein the sectional area of the upper part of each pad is greater than that of the lower part of each pad; etching the laminated copper foil to expose a copper pillar, so that the lower surface of each pad is completely exposed. With adoption of the single-layer substrate packaging process, the resistance to the pads, caused by the tension or thrust transferred by a solder ball is increased, so that the falling-off of pads can be prevented effectively.

Description

Single layer substrate packaging technology
Technical field
The present invention relates to the processing technology in a kind of semiconductor production, particularly a kind of single layer substrate packaging technology.
Background technology
In traditional single layer substrate manufacture process, as shown in Figure 1, pad 1 Direct Electroplating on Copper Foil 2 ', then pressing glass fibre 3 around pad 1.This structure, bottom pad 1 after encapsulation etch process (eroding copper foil layer), all can expose, only have the copper post of pad 1 both sides to be combined with glass fibre 3.When pad 1 is subject to external force collision, the as easy as rolling off a log soldered ball 4 that is inconjunction with of pad 1 comes off (as shown in Figure 2 and Figure 3).
Summary of the invention
Provide hereinafter about brief overview of the present invention, to provide about the basic comprehension in some of the present invention.Should be appreciated that this general introduction is not summarize about exhaustive of the present invention.It is not that intention determines key of the present invention or pith, and nor is it intended to limit the scope of the present invention.Its object is only provide some concept in simplified form, in this, as the preorder in greater detail discussed after a while.
A main purpose of the present invention is to provide a kind of single layer substrate packaging technology, and when can soldered ball be avoided at least to a certain extent to come off, the situation that pad comes off thereupon occurs.
According to an aspect of the present invention, a kind of single layer substrate packaging technology, comprising:
Pad bottom is formed at the upper surface of pressing Copper Foil;
Pressing first glass layer between adjacent pad bottom;
Coaxial formation pad top on described pad bottom, the sectional area on described pad top is greater than the sectional area of described pad bottom;
Copper post is exposed in described pressing Copper Foil etching, pad lower surface is exposed completely.
Adopt single layer substrate packaging technology of the present invention, adding the resistance of pad when being subject to the next pulling force of soldered ball transmission or thrust, effectively can prevent Pad off.
Accompanying drawing explanation
Below with reference to the accompanying drawings illustrate embodiments of the invention, above and other objects, features and advantages of the present invention can be understood more easily.Parts in accompanying drawing are just in order to illustrate principle of the present invention.In the accompanying drawings, same or similar technical characteristic or parts will adopt same or similar Reference numeral to represent.
Fig. 1 is the schematic diagram of existing single layer substrate encapsulating structure;
Fig. 2, Fig. 3 are the schematic diagram of existing single layer substrate encapsulating structure Pad off process;
Fig. 4 is the flow chart of a kind of execution mode of single layer substrate packaging technology of the present invention;
Fig. 5 is the schematic diagram of a kind of execution mode of the single layer substrate encapsulating structure obtained according to single layer substrate packaging technology of the present invention.
Embodiment
With reference to the accompanying drawings embodiments of the invention are described.The element described in an accompanying drawing of the present invention or a kind of execution mode and feature can combine with the element shown in one or more other accompanying drawing or execution mode and feature.It should be noted that for purposes of clarity, accompanying drawing and eliminate expression and the description of unrelated to the invention, parts known to persons of ordinary skill in the art and process in illustrating.
Fig. 4 is the flow chart of a kind of execution mode of single layer substrate packaging technology of the present invention.
In the present embodiment, single layer substrate packaging technology can comprise:
S10: form pad bottom at the upper surface of pressing Copper Foil 2 '.
S20: pressing first glass layer 3 ' between adjacent pad bottom.
S30: coaxial formation pad top in portion under a pad, the sectional area on pad top is greater than the sectional area of pad bottom.Such as, can under a pad portion upper surface welding or plating formed pad top.
S40: copper post is exposed in the etching of pressing Copper Foil 2 ', pad lower surface is exposed completely.
In one embodiment, step S20 can specifically comprise:
S21: between the pad bottom the first glass layer 3 ' being pressed together on adjacent pad.
Preferably, single layer substrate packaging technology can also comprise:
S50: pressing glass fibre 3 around pad 1 upper surface relative with pad 1 lower surface and between the pad top of adjacent pad 1.
As a kind of execution mode, can also comprise after step S30:
S60: implant tin ball (not shown) at pad 1 lower surface.
As a kind of execution mode, single layer substrate packaging technology can also comprise:
S70: the connecting portion 5 being used for being connected with external device (ED) is set at pad 1 upper surface.Such as, the through hole for being connected with chip 6 can be offered on pad.
Fig. 5 is the schematic diagram of a kind of execution mode of the single layer substrate encapsulating structure adopting single layer substrate packaging technology of the present invention to obtain.
In the present embodiment, single layer substrate encapsulating structure comprises pad 1, copper post and the first glass layer 3 '.
First glass layer 3 ' is pressed between the multiple pads on copper post, fixes with the relative position of copper post for making pad 1.
Between multiple pad 1, form the first glass layer 3 ', the fiting effect forming similar " interference fit " between pad 1 can be made.So, when pad is subject to External Force Acting, the first glass layer 3 ' can ensure that the relative position of pad 1 and copper post is fixed within the specific limits.
Similar to the prior art shown in Fig. 1, copper post is pressing Copper Foil 2 ' etching gained.Pad 1 is formed at the upper surface of pressing Copper Foil 2 ', and the upper surface fluid-tight engagement of the lower surface of pad 1 and pressing Copper Foil 2 '.
Copper post be etching pressing Copper Foil 2 ' make pad 1 lower surface expose completely after remainder.
In one embodiment, pad 1 comprises coaxial pad top stacked up and down and pad bottom;
The sectional area of pad bottom is less than the sectional area on pad top.First glass layer 3 ' is pressed between the pad bottom of the multiple adjacent pad 1 on copper post.
Pad top and pad bottom can by welding or plate bondings.
Adopt the pad of structure like this, when pad 1 is when being subject to external tensile force, because the sectional area on pad top is comparatively large, and the pressing of pad lower periphery has the first glass layer 3 ', can bear extraneous pulling force within the specific limits and not come off.
As a kind of preferred version, single layer substrate encapsulating structure also comprises the second glass layer 3.Around the upper surface that second glass layer 3 is pressed on the pad 1 relative with the lower surface of pad 1 and between the pad top of multiple adjacent pad.
Second glass layer 3 can play support and booster action to whole single layer substrate, makes single layer substrate have better integraty.In addition, due to the second glass layer 3 and pad 1 fluid-tight engagement, when after the etching of pressing Copper Foil 2 ', pad 1 still can remain on original position and not depart from or come off.
In one embodiment, single layer substrate encapsulating structure also comprises tin ball 7.Tin ball 7 is welded in the lower surface of pad 1.
Preferably, pad 1 can also be provided with the connecting portion 6 for being connected with external device (ED) 5 (such as chip etc.).In one embodiment, this connecting portion 6 can be through hole.
Adopt single layer substrate packaging technology of the present invention, adding the resistance of pad when being subject to the next pulling force of tin ball transmission or thrust, effectively can prevent Pad off.
In equipment of the present invention and method, obviously, each parts or each step reconfigure after can decomposing, combine and/or decomposing.These decompose and/or reconfigure and should be considered as equivalents of the present invention.Also it is pointed out that the step performing above-mentioned series of processes can order naturally following the instructions perform in chronological order, but do not need necessarily to perform according to time sequencing.Some step can walk abreast or perform independently of one another.Simultaneously, above in the description of the specific embodiment of the invention, the feature described for a kind of execution mode and/or illustrate can use in one or more other execution mode in same or similar mode, combined with the feature in other execution mode, or substitute the feature in other execution mode.
Should emphasize, term " comprises/comprises " existence referring to feature, key element, step or assembly when using herein, but does not get rid of the existence or additional of one or more further feature, key element, step or assembly.
Although described the present invention and advantage thereof in detail, be to be understood that and can have carried out various change when not exceeding the spirit and scope of the present invention limited by appended claim, substituting and conversion.And the scope of the application is not limited only to the specific embodiment of process, equipment, means, method and step described by specification.One of ordinary skilled in the art will readily appreciate that from disclosure of the present invention, can use perform the function substantially identical with corresponding embodiment described herein or obtain and its substantially identical result, existing and that will be developed in the future process, equipment, means, method or step according to the present invention.Therefore, appended claim is intended to comprise such process, equipment, means, method or step in their scope.

Claims (5)

1. a single layer substrate packaging technology, is characterized in that, comprising:
Pad bottom is formed at the upper surface of pressing Copper Foil;
Pressing first glass layer between adjacent pad bottom;
Coaxial formation pad top on described pad bottom, the sectional area on described pad top is greater than the sectional area of described pad bottom;
Copper post is exposed in described pressing Copper Foil etching, pad lower surface is exposed completely.
2. single layer substrate packaging technology according to claim 1, is characterized in that, described " on described pad bottom coaxial formation pad top " specifically comprises:
On described pad bottom, welding or plating form described pad top, make described pad top coaxial with described pad bottom.
3. single layer substrate packaging technology according to claim 1 and 2, is characterized in that, also comprise:
Around the pad upper surface relative with described pad lower surface, and pressing second glass layer between the pad top of adjacent pad.
4. single layer substrate packaging technology according to claim 3, is characterized in that, after described " copper post is exposed in described pressing Copper Foil etching, makes pad lower surface expose completely " step, also comprises:
Tin ball is implanted at the lower surface of described pad.
5. single layer substrate packaging technology according to claim 4, is characterized in that, also comprise:
The connecting portion being used for being connected with external device (ED) is set at pad upper surface.
CN201410779648.3A 2014-12-16 2014-12-16 Single-layer substrate packaging process Pending CN104576425A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410779648.3A CN104576425A (en) 2014-12-16 2014-12-16 Single-layer substrate packaging process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410779648.3A CN104576425A (en) 2014-12-16 2014-12-16 Single-layer substrate packaging process

Publications (1)

Publication Number Publication Date
CN104576425A true CN104576425A (en) 2015-04-29

Family

ID=53092179

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410779648.3A Pending CN104576425A (en) 2014-12-16 2014-12-16 Single-layer substrate packaging process

Country Status (1)

Country Link
CN (1) CN104576425A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101114600A (en) * 2006-07-27 2008-01-30 联华电子股份有限公司 Method and structure for preventing soldering pad stripping
US20080308308A1 (en) * 2007-03-29 2008-12-18 Shinko Electric Industries Co., Ltd. Method of manufacturing wiring board, method of manufacturing semiconductor device and wiring board
US20100096744A1 (en) * 2008-10-21 2010-04-22 International Business Machines Corporation Printed wiring board and method for manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101114600A (en) * 2006-07-27 2008-01-30 联华电子股份有限公司 Method and structure for preventing soldering pad stripping
US20080308308A1 (en) * 2007-03-29 2008-12-18 Shinko Electric Industries Co., Ltd. Method of manufacturing wiring board, method of manufacturing semiconductor device and wiring board
US20100096744A1 (en) * 2008-10-21 2010-04-22 International Business Machines Corporation Printed wiring board and method for manufacturing the same

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CB02 Change of applicant information

Address after: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288

Applicant after: Tongfu Microelectronics Co., Ltd.

Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288

Applicant before: Fujitsu Microelectronics Co., Ltd., Nantong

COR Change of bibliographic data
RJ01 Rejection of invention patent application after publication

Application publication date: 20150429

RJ01 Rejection of invention patent application after publication