CN104573148B

CN104573148B - A kind of method of sequential element leakage power consumption in reduction circuit

Info

Publication number: CN104573148B
Application number: CN201310485457.1A
Authority: CN
Inventors: 周舒哲; 董森华; 陈彬; 燕昭然
Original assignee: Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Beijing Empyrean Technology Co Ltd
Priority date: 2013-10-17
Filing date: 2013-10-17
Publication date: 2017-11-14
Anticipated expiration: 2033-10-17
Also published as: CN104573148A

Abstract

A kind of method of sequential element leakage power consumption in reduction circuit, with the continuous diminution of integrated circuit dimensions, electricity leakage power dissipation ratio in total power consumption is constantly lifted.Clock system is increasingly complicated simultaneously, and sequential device proportion constantly raises, and the electricity leakage power dissipation for effectively reducing sequential device can not be ignored.Using by low threshold voltage（LVT）It is replaced into high threshold voltage（HVT）Technology reduce electricity leakage power dissipation, Major Difficulties are that the temporal constraint of circuit can not be breached.The characteristics of herein according to sequential device, two kinds of Delay Variations are analyzed, one kind is setup constraints, and another kind is time delay of the clock end to output end；The method for establishing contingency table between sequential device is provided, records the information of incidence relation between all sequential devices；The requirement of the constraint of sequential is not violated for optimization circuit, it is proposed that utilize Delay Variation amount（delta）With time delay surplus（slack）Comparison and the method that is filtered to replaceable sequential device of contingency table, reached the purpose for reducing electricity leakage power dissipation.

Description

A kind of method of sequential element leakage power consumption in reduction circuit

Technical field

The method for reducing sequential element leakage power consumption in circuit is that eda tool is not violating the Timing Constraints of circuit Under, by by low threshold voltage（LVT）Sequential device change high threshold voltage into（HVT）Sequential device, to reduce electric leakage work( The method of consumption.The invention belongs to EDA design fields.

Background technology

It is non-to reduce the technology of dynamic power consumption by reducing supply voltage as integrated circuit feature size constantly reduces It is often universal.Meanwhile for the performance of holding circuit, generally from the device of low threshold voltage to realize circuit function.It is however, low The application of the device of threshold voltage so that the ratio accounted in total power consumption of electricity leakage power dissipation is constantly lifted.We can pass through estimation The time delay of circuit, under conditions of temporal constraint is not violated, change the device of a part of low threshold voltage into high threshold voltage Device, with reach reduce electricity leakage power dissipation purpose.

In the case of holding circuit performance, the method that electricity leakage power dissipation is reduced using double Vt technologies has been widely used. On the one hand, the displacement of logical combination device influences smaller on sequential.According to the result of static timing analysis, current device can be learnt The surplus of delay（slack）, while the delay difference that displacement occurs can be calculated（delta）, so that it is determined that the list can be replaced Member.On the other hand, sequential device ratio shared in former circuit is smaller, and sequential is had a great influence.Therefore, engineer When using double Vt replacement techniques drop electricity leakage power dissipation, can usually neglect sequential device.

Under current process node, circuit function becomes increasingly complex, and clock system is more and more huger, the power consumption of sequential device It can not be ignored in circuit.Two features be present in the displacement of sequential device cell：1）The setup times would generally be influenceed simultaneously Time delay with clock signals to Q points, and the cost of time delay also can be bigger than conventional combination device；2）Can between sequential device Can be interrelated, this causes the estimation of delay to need to consider that can relevant sequential device enter line replacement simultaneously.

Herein it is proposed that a kind of method for reducing sequential element leakage power consumption in circuit：By calculating the setup times The change that change and clock signals postpone to Q points, while the annexation established between sequential device, to ensure sequential device Displacement does not interfere with the temporal constraint of circuit simultaneously.

The content of the invention

The present invention proposes a kind of method for reducing sequential element leakage power consumption in circuit, and this method considers sequential device The delay variation feature of displacement, and consider the incidence relation between sequential device.Above feature is illustrated herein, proposes phase The solution answered, it ensure that to greatest extent while replace sequential device without destroying temporal constraint.

Sequential device is also with regard to trigger（Flip Flop）, it is a kind of device for storing data signal, there is input and defeated Go out end, and there is a special input to be used for input clock signal.When received during clock signal, output end just can basis Input signal updates output signal.Between two clock signals, the signal of output end is all without changing.With logical signal Difference be：The output of logical signal is related to current input signal；And the output signal of trigger is and upper one Input signal when clock signal arrives is related.

Fig. 1 is D flip flop, and input signal reaches D ports, and clock signal is reached at triangular marker, output signal Exported from Q or QN ends.D flip flop are rising edge triggerings, i.e., when clock signal is changed into 1 from 0, output end Q signal Can be just opposite with D signal according to the signal update at D ends, QN.

For more preferable calculation delay, generally we can be device setup delay model.Each Time Delay Model, it is generally right Answer a signal paths of device.A NOT gate A- is shown in Fig. 2>Z signal path, and the change rule of the end signal of path two Rule.Due to the particularity of sequential device function, setup delay model would generally be more complicated.Foundation that can not be simple from input to The Time Delay Model of output end, because there is the transmission that clock signal controls data-signal.Generally, we can define two kinds of time delay moulds Type：1）From input to clock end, such as Fig. 3, a setup constraint be present, before referring to that clock signal reaches, data-signal is necessary Ready time-constrain in advance；2）From clock end to output end, such as Fig. 4, this be signal from clock arrive the moment be transferred to it is defeated Go out the Time Delay Model established needed for end.

Using above Time Delay Model, static timing analysis is carried out.Calculate the delay surplus of every kind of device（slack）, With the amount of delay needed for displacement parallel operation part（delta）It is compared.Work as delta<During slack, can effectively it be replaced, and Do not violate temporal constraint.

In order to improve efficiency, we would generally batch exchange a collection of unit component for, then carry out the renewal of time delay value.Group Combinational logic circuit can find out the incoherent unit of a collection of sequential by way of topological sorting.Relevance between sequential device It can not be discharged with topological sorting, inter-related situation usually occur, as shown in Figure 5.

A kind of it is proposed that method for establishing sequential device contingency table：First, the annexation based on circuit, by from institute There is sequential device output end Q to be traveled through to next sequential device input D, can obtain all D points there are the Q points of annexation；So Afterwards according to the contingency table of D points, we can analyze the contingency table for all D points for drawing the connection of Q points；Finally the two tables are closed And the contingency table put on all sequential devices can be drawn.

When replacing unit, sequential device can be ranked up by we by this contingency table according to the dimension of association.So Afterwards, the Delay Variation value calculated with reference to Time Delay Model（delta）With already present delay surplus（slack）, analyzing delta is It is no to be less than slack values, determine that can active cell be replaced.Meanwhile after current permutation consumes a part of surplus, those passes Whether the sequential device of connection also has enough delay surpluses to enter line replacement, and replaceable set must be excluded from if not enough.

Brief description of the drawings

Fig. 1 D flip flop

The signalling channel and waveform relationship of Fig. 2 NOT gates

The signalling channel and waveform relationship of Fig. 3 setup constraints

Signalling channel and waveform relationship of Fig. 4 clock ends to output end

It is interrelated between Fig. 5 sequential devices

Specific implementation step：

The method that HVT sequential devices are replaced into using LVT carries out electricity leakage power dissipation optimization, and operating process is as follows：

1）Prepare circuit meshwork list, the Lib storehouses of standard block and Sdc files, carry out static timing analysis；

2）The timing unit for being possible to be replaced is found out, and calculates the delay variation needed for displacement（delta）；

3）Filter out amount of delay and be more than delay surplus（slack）Unit；

4）The contingency table of sequential device is established, and ascending order arrangement is carried out according to associated apparatus number；

5）Disposable units are chosen in order, while exclude other timing units that selected cell influences whether；

, it is necessary to update delay data after the completion of displacement, follow-up circuit optimization step can proceed with.

Claims

1. a kind of method for reducing sequential element leakage power consumption in circuit, is related to EDA design tools, it is characterised in that described Method comprises the following steps：

(1) establish sequential device input to clock end Time Delay Model and clock end to output end Time Delay Model；

(2) calculate the delay surplus of sequential device and replace the amount of delay needed for device；

(3) by traveling through circuit diagram, contingency table between sequential device is established, sequential device is arranged according to the dimension of association Sequence；

(4) according to sequence, amount of delay and current delay surplus needed for more current sequential device, if amount of delay Less than current delay surplus, then replace current sequential device and consume required delay variation from current delay surplus Amount, otherwise excludes replaceable set by current sequential device；

(5) repeat step (2)-step (4), delay data is updated.

2. the method according to claim 1 for reducing sequential element leakage power consumption in circuit, it is characterised in that step (1) The sequential device input of establishing is that data-signal must carry before defining clock signal arrival to the Time Delay Model of clock end Preceding ready time-constrain；Sequential device clock end is established to the Time Delay Model of output end, is that signal arrives the moment from clock It is transferred to the time delay needed for output end.