CN101241523A - Full-chip interconnecting line power consumption optimum layout stage buffer planning method - Google Patents

Abstract

The present invention provides an approaches to planning of chip interconnection line power-optimized layout stage buffer, belonging to interconnection line design optimization field of technology, characterized in containing follow steps: reading module information and interconnection line information, establishing circuit logical topology, initializing side state being 1, calculating time relaxation measurement between the module interconnection lines, calculating each side weighing in the logical topology, obtaining maximal cut set of the logical topological diagram by pre-flowing boost method, distributing time relaxation measurement to each side of the cut set, for each interconnection line, calculating need buffer size and numbers and total interconnection lines power dissipation according to the distribution result of the time relaxation. The invention reduces total power dissipation of the interconnection line without sacrificing circuit time lag performance, having great executing efficiency and industrial application price.

Description

The layout stage buffer planning method of full-chip interconnecting line power consumption optimum

Technical field

The layout stage buffer planning method of full-chip interconnecting line power consumption optimum belongs to the integrated circuit CAD field, relates in particular to interconnection line design optimization field.

Background technology

Along with constantly dwindling of integrated circuit technology size and improving constantly of integrated level, the delay of interconnection line has influenced the performance of circuit to a great extent.In order to improve the delay of interconnection line, in general need in globally interconnected line, use impact damper.Yet these impact dampers have increased power consumption greatly, make interconnecting line power consumption become the important component part in the full chip power-consumption.Interconnecting line power consumption be optimized to important consideration in the circuit design.

The performance of circuit depends on the slowest path (critical path), for most of large scale integrated circuits, has a large amount of non-critical paths in the design.Under the prerequisite that is no more than the critical path time-delay, the time-delay that can increase non-critical path improves other performances of circuit, and the time-delay recruitment of being allowed on these non-critical paths is referred to as the time slack.In recent years, many technology point out if can suitably relax the requirement that interconnection line is postponed, and number that can be by reducing impact damper and the size that reduces impact damper reduce the power consumption of interconnection line.And, the power consumption reduction amount of interconnection line and the length of interconnection line, signal upset probability, and the time increment of allowing is all relevant, even different interconnection lines gives identical time increment, the power consumption reduction amount that obtains also may differ widely.Therefore, the time slack that how to make full use of in the non-critical path comes the interconnecting line power consumption of optimization integral body to become an important topic.This problem can simply be described as: the topological structure of a given circuit and layout result thereof (the lead end position of module is given), find out the non-critical path of circuit and calculate its time slack, again according to the topological relation of circuit, the time slack is distributed to the interconnection line that can obtain the maximum power dissipation reduction, thereby obtain optimized interconnection line total power consumption.

For a long time, time slack assignment problem is subjected to paying close attention to widely, and people have proposed a lot of time slack distribution methods.For example, the zero slack allocation algorithm of Ti Chuing (Zero Slack Algorithm) is given each section interconnection line of non-critical path with time slack uniform distribution the earliest, makes in the circuit no longer life period slack.Yet this algorithm only can guarantee that the time slack all is assigned with, and does not consider the relation between power consumption and the time slack, and allocation result can not reach overall interconnect line power consumption optimum.The multiple time slack allocation algorithm of optimizing at module dissipation has appearred afterwards.Module dissipation Optimization Model in these algorithms is mostly based on the multi-power source voltage technology, the use of this method has bigger limitation: multi-power source voltage can bring the expense of extra level shifting circuit on the one hand, and under the situation of given layout, these algorithms can cause the random distribution of low-voltage module, have greatly increased the design complexities of electric power network.On the other hand, have the IP module much designed in the modern designs, the voltage of these modules can not arbitrarily change.And supply voltage can only get several discrete values, and this uncontinuity can not guarantee that the time slack is fully utilized.Therefore, even the circuit of having optimized for module voltage is further optimized interconnecting line power consumption and also is very important.Because the relation of module dissipation and time slack is different with the relation of time slack with interconnecting line power consumption, these time slack allocation algorithms at module dissipation optimization can not be grafted directly on the interconnection line optimised power consumption.Therefore, up to now, also there is not a kind of effective method can effectively distribute the time slack to obtain optimization interconnection line total power consumption.

Summary of the invention

The objective of the invention is to propose a kind of stable, efficient, can in floor planning, realize under the prerequisite that does not influence circuit performance, making interconnecting line power consumption reach the industrial instrument of optimum the making rational planning for of impact damper.In the modern designs that interconnect delay sharply increases, the planning of impact damper becomes the important ring in the design, and interconnecting line power consumption occupies the also rising day by day of proportion of entire chip power consumption simultaneously.Therefore, the impact damper of considering power consumption is planned very necessary.

The invention is characterized in that described method realizes successively according to the following steps in computing machine:

Step (1). initialization

The technological parameter that power consumption calculation is used is set: supply voltage V _DD, clock frequency f _Clk, unit sizes impact damper leakage current I _Offn, unit sizes impact damper short circuit current I _Short,

The correlation parameter of impact damper: load capacitance C is set _L, drive output resistance R _d, unit sizes impact damper output resistance r _s, unit sizes impact damper input capacitance c _o, unit sizes impact damper output capacitance c _p,

The correlation parameter of interconnection line is set: unit length line capacitance c, unit length line resistance r,

The correlation parameter of power consumption-time slack branch linear model is set: the reference position a of each piecewise interval _i, final position b _i, the optimum time-delay of unit length interconnection line

The model parameter m of slope between the expression linear zone _i, n _i, and interconnection line critical length L _Crit, wherein power consumption-time slack branch linear model is:

$\mathrm{\&Delta;P}(\mathrm{\&alpha;},L,\mathrm{slack})=\left\{\begin{array}{c}0(L<=L_{\mathrm{crit}})\\ \mathrm{\&alpha;}(m_{i}L+n_i\mathrm{slack})(L>L_{\mathrm{crit}},f=\frac{\mathrm{slack}}{L\&CenterDot;{\left(\frac{\mathrm{\&tau;}}{l}\right)}_{\mathrm{opt}}}\&Element;[a_i,b_i))\end{array}\right.$

Wherein slack is the time slack, α representation signal upset probability, and L is an interconnect length;

Interconnection line critical length L _CritObtain by following formula:

$L_{\mathrm{crit}}=2\sqrt{\frac{{2r}_s(c_0+c_p)}{\mathrm{rc}}};$

Step (2). read in module and gauze information from module description file:

Step (2.1). read in the module four angular coordinate, and wide, high according to the four angular coordinate computing module of this module, and the coordinate of the corresponding lead end of module;

Step (2.2). read in the time delay information of selected module;

Step (2.3). read in gauze information, the interconnected information and the input/output relation of logging modle, and be calculated as follows the length L and the initial time delay of interconnection line:

If: the coordinate of interconnection line lead end is (x ₁, y ₁), (x ₂, y ₂),

Then: the length L of interconnection line is:

L＝|x ₁-x ₂|+|y ₁-y ₂|，

If: the initial time delay d of interconnection line _LinitFor

$d_{\mathrm{Linit}}=2\sqrt{r_s{c}_0\mathrm{rc}}(1+\sqrt{\frac{1}{2}(1+\frac{c_p}{c_0})})*L;$

Step (3). according to the module information and the interconnect information of step (2.2), structure is in order to the directed acyclic graph of the indication circuit annexation logical topology figure as circuit, node representation module among the figure, and the line between the representation module of limit, and increase a virtual input node as original all the input nodes input, simultaneously, increase the output of a virtual output node as original all output nodes, the intrinsic time-delay of dummy node all is designated as 0;

Step (4). iteration is distributed the time slack according to the following steps:

Step (4.1). the quantity of state that each limit in the directed acyclic graph is built in initial setting up is 1;

Step (4.2). calculate the time slack between each interconnection line as follows:

$\left\{\begin{array}{c}a\left(v\right)=\underset{u\&Element;\mathrm{FI}\left(v\right)}{\max }(a\left(u\right)+d\left(u\right)+d(u,v)),\\ r\left(v\right)=\underset{u\&Element;\mathrm{FO}\left(v\right)}{\min }(r\left(u\right)-d\left(v\right)-d(v,u)),\\ \mathrm{slack}(u,v)=r\left(v\right)-d\left(u\right)-a\left(u\right)-d(u,v),\end{array}\right.$

Wherein: a (v) be the time of the actual arrival of signal module v, the ns of unit,

A (u) is the time of the actual arrival of signal module u, the ns of unit,

D (v) be the intrinsic time-delay of signal by module v, the ns of unit,

D (u) is the intrinsic time-delay of signal by module u, the ns of unit,

D (u, v) for signal passes through module v, the time-delay of the interconnection line between the u, the ns of unit,

R (v) arrive the time of module v for semaphore request, the ns of unit,

R (u) is the time of semaphore request arrival module u, the ns of unit,

(u is module v v) to slack, the time slack of the interconnection line between the u, the ns of unit

FI (v) be the set of all load modules of module v,

FO (v) be the set of all output modules of module v,

Establish: the time of the virtual load module of the actual arrival of signal is 0 herein, and the time that semaphore request arrives virtual output module is the time of this module of the actual arrival of signal;

Step (4.3). for the time slack is 0 interconnection line, and the quantity of state of this interconnection line is changed to 0, in case the quantity of state of all interconnection lines is 0, iterative process finishes;

Step (4.4). be calculated as follows out the weight w on each limit among the logical topology figure of the circuit of building:

$w=\frac{\mathrm{d\&Delta;P}(\mathrm{\&alpha;},L,\mathrm{slack})}{d\left(\mathrm{slack}\right)}$

Be w be Δ P (α, L is slack) to the partial derivative of slack;

Step (4.5). utilize pre-stream propulsion method to obtain the maximum cut set of logical topology figure, the time slack is distributed on every limit in this cut set according to the following steps:

Step (4.5.1). when not inserting impact damper in the interconnection line, this interconnection line has maximum delay d _Lmax:

$d_{L\max }=\frac{1}{2}{\mathrm{<figure-callout\; id="2"\; label="rcL"\; filenames="S2008101015988E00011.png"\; state="\{\{state\}\}">rcL</figure-callout>}}^2+(R_{d}c+r{C}_L)L+R_d{C}_L,$

Wherein: R _dFor driving output resistance (Ω), C _LBe load capacitance (fF),

And the time-delay that is in the interconnection line of state i has a upper limit constraint d _Li:

d _Li＝d _Linit(1+f _i)，

f _iBe the right endpoint value between corresponding linear zone in power consumption-time slack branch linear model, d _LminIt is the initial time delay of the interconnection line that obtains in the step 2;

If: every current time-delay in limit is d under the current state _Lcurrent, slack is the time slack of interconnection line between the module that obtains in the step 4.2,

Then: the time-delay on this limit should be updated to d _Lupdated:

d _Lupdated＝min((d _Lcurrent+slack)，d _Lmax，d _Li)；

Step (4.5.2). if d _LupdatedBe assigned d _Lcurrent+ slack or d _Lmax, then this interconnection line quantity of state is rewritten as 0, this interconnection line time slack of can not reallocating;

Step (4.5.3). if d _LupdatedBe assigned d _Li, then this interconnection line quantity of state adds 1 on the original basis;

Step (4.6). for each section interconnection line, according to size s and number N and output that time slack allocation result is calculated needed impact damper, its formula is as follows:

$\frac{k_1(c_p+c_0)}{l}+\frac{k_2}{l}+k_3(1+f){\left(\frac{\mathrm{\&tau;}}{l}\right)}_{\mathrm{opt}}-[\frac{k_{1}s(c_p+c_0)}{{\mathrm{<figure-callout\; id="2"\; label="l"\; filenames="S2008101015988E00011.png"\; state="\{\{state\}\}">l</figure-callout>}}^2}+\frac{k_{2}s}{l^2}]\frac{\mathrm{dl}}{\mathrm{ds}}=0$

$\frac{1}{l}{r}_s(c_p+c_0)+\frac{r_s}{s}c+\mathrm{rs}{c}_0+\frac{1}{2}\mathrm{rcl}-(1+f){\left(\frac{\mathrm{\&tau;}}{l}\right)}_{\mathrm{opt}}=0$

$[\frac{1}{2}\mathrm{rc}-\frac{r_s(c_p+c_0)}{l^2}]\frac{\mathrm{dl}}{\mathrm{ds}}+{\mathrm{rc}}_0-\frac{r_{s}c}{s^2}=0$

Wherein, ${\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="S2008101015988E00011.png"\; state="\{\{state\}\}">k</figure-callout>}}_1=\mathrm{\&alpha;}{V}_{\mathrm{DD}}^2{f}_{\mathrm{clk}},$ ${\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="S2008101015988E00011.png"\; state="\{\{state\}\}">k</figure-callout>}}_2=\frac{3}{2}{V}_{\mathrm{DD}}{I}_{\mathrm{offn}},$

k ₃＝ln3·αV _DDI _shortf _clk，

Wherein, s is a buffer size, i.e. the multiple of unit buffer size,

L is an interconnect length, um,

α is a signal upset probability,

V _DDBe supply voltage, V,

f _ClkBe frequency of operation, GHz,

L is the impact damper spacing, um,

c _oBe the unit buffer input capacitance, fF,

C is the unit length line capacitance, fF/um,

c _pBe the unit buffer output capacitance, fF,

I _OffnBe the unit buffer leakage current, uA,

I _ShortBe the unit buffer short-circuit current, uA,

F is time punishment, exceeds optimum number percent (%) expression of delaying time with actual time delay,

Be the optimum time-delay of unit length interconnection line, ns, setting value;

The number N of impact damper tries to achieve according to following formula:

Expression rounds downwards

Step (4.7). by the power consumption of setting each section interconnection line, calculate this circuit overall interconnect line power consumption,

2. the buffer planning method of full-chip interconnecting line power consumption optimumization according to claim 1 is characterized in that, described power consumption-time slack piecewise linear model is obtained according to the following steps:

A) preseting length is the computing formula of power consumption P of the interconnection line of L:

$P=L*(k_1(\frac{s}{l}(c_p+c_o)+c)+k_2\frac{s}{l}+k_3(1+f)s{\left(\frac{\mathrm{\&tau;}}{l}\right)}_{\mathrm{opt}})$

Wherein, $k_{1}L(\frac{s}{l}(c_p+c_o)+c)$ Be dynamic power consumption,

Be short-circuit dissipation,

$k_{3}L(1+f)s{\left(\frac{\mathrm{\&tau;}}{l}\right)}_{\mathrm{opt}}$ Be electricity leakage power dissipation,

Wherein, ${\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="S2008101015988E00011.png"\; state="\{\{state\}\}">k</figure-callout>}}_1=\mathrm{\&alpha;}{V}_{\mathrm{DD}}^2{f}_{\mathrm{clk}},$ ${\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="S2008101015988E00011.png"\; state="\{\{state\}\}">k</figure-callout>}}_2=\frac{3}{2}{V}_{\mathrm{DD}}{I}_{\mathrm{offn}},$

k ₃＝ln3·αV _DDI _shortf _clk，

Wherein, L is an interconnect length, um,

α is a signal upset probability,

V _DDBe supply voltage, V,

f _ClkBe frequency of operation, GHz,

S is a buffer size, i.e. the multiple of unit buffer size,

L is the impact damper spacing, um,

c _oBe the unit buffer input capacitance, fF,

C is the unit length line capacitance, fF/um,

c _pBe the unit buffer output capacitance, fF,

I _OffnBe the unit buffer leakage current, uA,

I _ShortBe the unit buffer short-circuit current, uA,

F is time punishment, exceeds optimum number percent (%) expression of delaying time with actual time delay,

Be the optimum time-delay of unit length interconnection line, ns, setting value;

B) press $L_{\mathrm{crit}}=2\sqrt{\frac{{2r}_s(c_0+c_p)}{\mathrm{rc}}}$ Calculate the critical length L of interconnection line _Crit

C) when the interconnection line length L greater than L _CritThe time, at the time punishment f that sets, under the signal upset probability α, try to achieve funtcional relationship between power consumption reduction amount and linear fit itself and the interconnect length L with the formula in the step (a);

D) at L greater than L _CritUnder the situation, as time punishment f, when interconnect length L sets, the funtcional relationship between linear plan signal upset probability α and the power consumption reduction amount.

E) under the interconnect length L of the signal of step (c) upset probability α, step (d), the relation between piecewise linearity processing time punishment f and the power consumption reduction amount Δ P obtains power consumption-time slack piecewise linear model, represents with following formula:

$\mathrm{\&Delta;P}(\mathrm{\&alpha;},L,\mathrm{slack})=\left\{\begin{array}{c}0(L<=L_{\mathrm{crit}})\\ \mathrm{\&alpha;}(m_{i}L+n_i\mathrm{slack})(L>L_{\mathrm{crit}},f=\frac{\mathrm{slack}}{L\&CenterDot;{\left(\frac{\mathrm{\&tau;}}{l}\right)}_{\mathrm{opt}}}\&Element;[a_i,b_i))\end{array}\right.$

Wherein slack is the time slack, and the time slack that on behalf of this interconnection line, i distribute is residing different interval, a _i, b _iBe two end values between each linear zone, m _i, n _iBe the model parameter that match obtains, Be the optimum time-delay of unit length interconnection line, setting value.

Test findings shows: the present invention has improved the interconnection line total power consumption greatly under the prerequisite that does not influence the circuit delay performance, and this algorithm has good execution efficient.

Description of drawings

Fig. 1. interconnection line signal upset probability and power consumption reduce the linear fit result and the error of magnitude relation; Fig. 1 (a) is the linear fit curve, and Fig. 1 (b) is the graph of errors of match value and experiment value, and maximum error is 2.2%, and average error is 0.3%;

Fig. 2. punishment of interconnection line time and power consumption reduce the sectional linear fitting result and the error of magnitude relation; Fig. 2 (a) is the linear fit curve, and Fig. 2 (b) is the graph of errors of match value and experiment value, and maximum error is 4.9%, and average error is 1.7%;

Fig. 3. the static timing analysis synoptic diagram, the signal actual time of arrival a (C) of module C and semaphore request r time of arrival (C), and the time slack slack of interconnection line AC (A, C) satisfy following relation:

a(C)＝max((a(A)+d(A)+d(A，C))，(a(B)+d(B)+d(B，C)))；

r(C)＝min((r(D)-d(C)-d(C，D))，(r(E)-d(C)-d(C，E)))；

slack(A，C)＝r(C)-a(A)-d(A)-d(A，C)；

A (A) wherein, a (B) representation module A, the signal actual time of arrival of B, r (D), r (E) representation module D, the semaphore request time of arrival of E, d (A), d (B), d (C) representation module A, B, the intrinsic time-delay of C, d (A, C), and d (B, C), d (C, D), d (C, E) expression interconnection line AC, BC, CD, the intrinsic time-delay of CE.

Fig. 4. time slack allocation algorithm flow process.

Embodiment

Example is done with the n30 among the international benchmark test examples of circuits GSRC in this part, adopts the .18um technological parameter, according to above-described step the present invention is explained.

Following table is the definition and the numerical value of some technology correlation parameters:

Table one: technological parameter tabulation

r	Unit length line resistance (Ω/μ m)	0.008
			c	Unit length line capacitance (fF/ μ m)	0.269
V DD	Supply voltage (V)	1.8
			f clk	Frequency of operation (GHz)	1.2
c 0	Unit sizes impact damper input capacitance (fF)	1.9
			r s	Unit sizes impact damper output resistance (Ω)	36300
c p	Unit sizes impact damper output capacitance (fF)	4.8
			I offn	Unit sizes impact damper leakage current (uA)	0.2
I short	Unit sizes impact damper short-circuit current (uA)	65
			R d	Drive output resistance (Ω)	400
C L	Load capacitance (fF)	200

1. set up power consumption-time slack piecewise linear model, suppose that the error of piecewise linear model is no more than 5%:

A) computational length is the power consumption of the interconnection line of L in the following manner

$P=L*(k_1(\frac{s}{l}(c_p+c_o)+c)+k_2\frac{s}{l}+k_3(1+f)s{\left(\frac{\mathrm{\&tau;}}{l}\right)}_{\mathrm{opt}})$

Wherein, $k_{1}L(\frac{s}{l}(c_p+c_o)+c)$ Be dynamic power consumption,

Be short-circuit dissipation,

$k_{3}L(1+f)s{\left(\frac{\mathrm{\&tau;}}{l}\right)}_{\mathrm{opt}}$ Be electricity leakage power dissipation,

Wherein, ${\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="S2008101015988E00011.png"\; state="\{\{state\}\}">k</figure-callout>}}_1=\mathrm{\&alpha;}{V}_{\mathrm{DD}}^2{f}_{\mathrm{clk}},$ ${\mathrm{<figure-callout\; id="2"\; label="k"\; filenames="S2008101015988E00011.png"\; state="\{\{state\}\}">k</figure-callout>}}_2=\frac{3}{2}{V}_{\mathrm{DD}}{I}_{\mathrm{offn}},$

k ₃＝ln3·αV _DDI _shortf _clk，

Wherein, L is an interconnect length, um,

α is a signal upset probability,

V _DDBe supply voltage, V,

f _ClkBe frequency of operation, GHz,

S is a buffer size, i.e. the multiple of unit buffer size,

L is the impact damper spacing, um,

c _oBe the unit buffer input capacitance, fF,

C is the unit length line capacitance, fF/um,

c _pBe the unit buffer output capacitance, fF,

I _OffnBe the unit buffer leakage current, uA,

I _ShortBe the unit buffer short-circuit current, uA,

F is time punishment, exceeds optimum number percent (%) expression of delaying time with actual time delay,

Be the optimum time-delay of unit length interconnection line, ns, setting value;

B) press $L_{\mathrm{crit}}=2\sqrt{\frac{{2r}_s(c_0+c_p)}{\mathrm{rc}}}$ Calculate the critical length L of interconnection line _CritCan try to achieve critical length is 6.67mm;

C) supposition interconnection line upset probability α is 0.15, and time punishment f is 10%, tries to achieve the following relation of funtcional relationship between power consumption reduction amount and linear fit itself and the interconnect length L with the formula in the step (a):

$\mathrm{\&Delta;P}=\left\{\begin{array}{c}0(L<=L_{\mathrm{crit}})\\ 11.4L(L>L_{\mathrm{crit}})\end{array}\right.\left(\mathrm{mW}\right)$

D) suppose that interconnect length is 15mm, time punishment f is 10%, and it is as follows to try to achieve power consumption reduction amount and linear fit itself and the relation of overturning between the probability α with the formula in the step (a):

ΔP＝1.14α(mW)

Error maximum 2.2%, average 0.3%, fitting result and graph of errors are as shown in Figure 1;

E) suppose that interconnect length is 15mm, upset probability α is 0.15, and piecewise linearity is handled the relation between f and the Δ P, the f interval can be divided into 5 sections [0,1%), [1%, 4%), [4%, 10%), [10%, 60%), (60%, ∞).Comprehensive first two steps analysis, it is as follows to obtain power consumption-time slack piecewise linear model,

$\mathrm{\&Delta;P}(\mathrm{\&alpha;},L,\mathrm{slack})=\left\{\begin{array}{c}0(L<=L_{\mathrm{crit}})\\ \mathrm{\&alpha;}(m_{i}L+n_i\mathrm{slack})(L>L_{\mathrm{crit}},f=\frac{\mathrm{slack}}{L\&CenterDot;{\left(\frac{\mathrm{\&tau;}}{l}\right)}_{\mathrm{opt}}}\&Element;[a_i,b_i))\end{array}\right.$

The wherein value of each parameter such as following table:

Table two, each parameter of piecewise linear model is as follows

al	0	b1	1％	m1	0	n1	5.4
								a2	1％	b2	4％	m2	0.054	n2	1.9
a3	4％	b3		10％	m3	0.076	n3									0.853
								a4	10％	b4	60％	m4	0.085	n4	0.255
a5	60％	b5	∞	m5	0.153	n5	0.067

Analyze the error maximum 4.9% of whole piecewise linear model, average 1.7% through the Monte Carlo.Fitting result as shown in Figure 2;

2. computer program is carried out initialization, is provided with and imports following parameter according to table one and table two:

A) the relevant technological parameter of power consumption calculation is set, comprises supply voltage, clock frequency, unit sizes impact damper leakage current, unit sizes impact damper short-circuit current;

B) the relevant various performance parameters of impact damper is set, comprises load capacitance, drive output resistance, unit sizes impact damper output resistance, unit sizes impact damper input capacitance, unit sizes impact damper output capacitance;

C) the relevant various performance parameters of interconnection line is set, comprises the unit length line capacitance, the unit length line resistance;

D) correlation parameter of power consumption-time slack branch linear model is set, comprises the start-stop position a of each piecewise interval _i, b _i, the slope m of each interval line segment _i, n _i, the optimum time-delay of unit length interconnection line And interconnection line critical length L _Crit

3. computing machine reads in module and gauze information from module description file:

A) read in the module four angular coordinate, and wide, high according to module four angular coordinate computing module, and the coordinate of the corresponding lead end of module; Test module n30 contains 30 modules altogether;

B) read in module time delay information, produce n30 module time delay information at random according to the delayed data in .18um technology elementary cell storehouse in the test and read in;

C) read in gauze information.In this test the n30 gauze is handled, at first the multiterminal gauze is split as two end line nets, and specify wherein that an end is an input end, all the other are output terminal, obtain 181 interconnection lines; For every interconnection line, be calculated as follows interconnect length and initial time delay:

If: the coordinate of interconnection line lead end is (x ₁, y ₁), (x ₂, y ₂),

Then: the length L of interconnection line is:

L＝|x ₁-x ₂|+|y ₁-y ₂|，

The initial time delay d of interconnection line _LinitFor

$d_{\mathrm{Linit}}=2\sqrt{r_s{c}_0\mathrm{rc}}(1+\sqrt{\frac{1}{2}(1+\frac{c_p}{c_0})})*L;$

4. set up topological constraints figure

According to module information and interconnect information, put out the logical topology of circuit in order, construct the directed acyclic graph of indication circuit annexation, the module of the node indication circuit among the figure wherein, interconnection line between the limit representation module among the figure, and increase of the input of a virtual input node as original all input nodes, and increasing of the output of a virtual output node simultaneously as original all output nodes, the intrinsic time-delay of dummy node all is designated as 0; Contain 32 nodes among the resultant figure of example altogether, comprise that 30 internal nodes represent 30 modules, 1 virtual input node also has 1 virtual output node.

5. iteration is distributed time slack and output buffer program results according to the following steps:

A) quantity of state that each limit in the directed acyclic graph is built in initial setting up is 1;

B) calculate time slack between each interconnection line as follows:

$\left\{\begin{array}{c}a\left(v\right)=\underset{u\&Element;\mathrm{FI}\left(v\right)}{\max }(a\left(u\right)+d\left(u\right)+d(u,v)),\\ r\left(v\right)=\underset{u\&Element;\mathrm{FO}\left(v\right)}{\min }(r\left(u\right)-d\left(v\right)-d(v,u)),\\ \mathrm{slack}(u,v)=r\left(v\right)-d\left(u\right)-a\left(u\right)-d(u,v),\end{array}\right.$

Wherein: a (v) be the time of the actual arrival of signal module v, the ns of unit,

A (u) is the time of the actual arrival of signal module u, the ns of unit,

D (v) be the intrinsic time-delay of signal by module v, the ns of unit,

D (u) is the intrinsic time-delay of signal by module u, the ns of unit,

D (u, v) for signal passes through module v, the time-delay of the interconnection line between the u, the ns of unit,

R (v) arrive the time of module v for semaphore request, the ns of unit,

R (u) is the time of semaphore request arrival module u, the ns of unit,

(u is module v v) to slack, the time slack of the interconnection line between the u, the ns of unit

FI (v) be the set of all load modules of module v,

FO (v) be the set of all output modules of module v,

Establish: the time of the virtual load module of the actual arrival of signal is 0 herein, and the time that semaphore request arrives virtual output module is the time of this module of the actual arrival of signal; As shown in Figure 4;

C) for the time slack be 0 interconnection line, the quantity of state of this interconnection line is changed to 0, in case the quantity of state of all interconnection lines is 0, iterative process finishes;

D) be calculated as follows out the weight w on each limit among the logical topology figure of the circuit of building:

$w=\frac{\mathrm{d\&Delta;P}(\mathrm{\&alpha;},L,\mathrm{slack})}{d\left(\mathrm{slack}\right)}$

Be w be Δ P (α, L is slack) to the partial derivative of slack;

E) utilize pre-stream propulsion method to obtain the maximum cut set of logical topology figure.The time slack is distributed by following rule in every limit in this cut set:

1) when not inserting impact damper in the interconnection line, this interconnection line has maximum delay d _Lmax:

$d_{L\max }=\frac{1}{2}{\mathrm{<figure-callout\; id="2"\; label="rcL"\; filenames="S2008101015988E00011.png"\; state="\{\{state\}\}">rcL</figure-callout>}}^2+(R_{d}c+r{C}_L)L+R_d{C}_L,$

Wherein: R _dFor driving output resistance (Ω), C _LBe load capacitance (fF),

And the time-delay that is in the interconnection line of state i has a upper limit constraint d _Li:

d _Li＝d _Linit(1+f _i)，

f _iBe the right endpoint value between corresponding linear zone in power consumption-time slack branch linear model, d _LminIt is the initial time delay of the interconnection line that obtains in the step 2;

If: every current time-delay in limit is d under the current state _Lcurrent, slack is the time slack of interconnection line between the module that obtains in the step 4.2,

Then: the time-delay on this limit should be updated to d _Lupdated:

d _Lupdated＝min((d _Lcurrent+slack)，d _Lmax，d _Li)；

2) if d _LupdatedBe assigned d _Lcurrent+ slack or d _Lmax, then this interconnection line quantity of state is rewritten as 0, this interconnection line time slack of can not reallocating;

3) if d _LupdatedBe assigned d _Li, then this interconnection line quantity of state adds 1 on the original basis;

F). for each section interconnection line, according to size s and number N and output that time slack allocation result is calculated needed impact damper, its formula is as follows:

$\frac{k_1(c_p+c_0)}{l}+\frac{k_2}{l}+k_3(1+f){\left(\frac{\mathrm{\&tau;}}{l}\right)}_{\mathrm{opt}}-[\frac{k_{1}s(c_p+c_0)}{{\mathrm{<figure-callout\; id="2"\; label="l"\; filenames="S2008101015988E00011.png"\; state="\{\{state\}\}">l</figure-callout>}}^2}+\frac{k_{2}s}{l^2}]\frac{\mathrm{dl}}{\mathrm{ds}}=0$

$\frac{1}{l}{r}_s(c_p+c_0)+\frac{r_s}{s}c+\mathrm{rs}{c}_0+\frac{1}{2}\mathrm{rcl}-(1+f){\left(\frac{\mathrm{\&tau;}}{l}\right)}_{\mathrm{opt}}=0$

$[\frac{1}{2}\mathrm{rc}-\frac{r_s(c_p+c_0)}{l^2}]\frac{\mathrm{dl}}{\mathrm{ds}}+{\mathrm{rc}}_0-\frac{r_{s}c}{s^2}=0$

For rounding downwards

G). by the power consumption of each section interconnection line, calculate this circuit overall interconnect line power consumption, the total power consumption after n30 optimizes is 239.2mW, compares power consumption before with optimization and has reduced by 28.6%;

Except n30, (n50 ~ n300), and some other high-level comprehensive exemplary circuit test, the result is as shown in the table to other circuit in the GSRC example for we.Applied hardware was a 1.83GHz when the present invention tested, the PC of internal memory 1GB, and all exemplary circuit all can be obtained a result in several ms.

Table two exemplary circuit test result

Examples of circuits	The interconnection line number	Initial power consumption (mW)	Optimize back power consumption (mW)	Power consumption reduces (%)	Iterations
						n30	181	335.03	239.24	28.6	15
n50	208	1473.97	1100.81	25.3	16
						n100	293	2106.53	1251.53	40.6	21
n200	599	6413.5	3316.57	48.3	24
						n300	719	7126.47	3486.48	51.1	30
chemical	30	241.64	128.48	46.8	4
						dct_ijepg	64	1013.51	504.13	50.3	8
dct_lee	49	960.16	542.98	43.5	6
						Dct_wang	57	1123.31	592.02	47.3	6
elliptic	32	740.61	313.56	57.7	3
						iir77	32	683.94	378.79	44.6	7
jacobi_sm	60	1366.1	806.68	41	9
						wdf	47	457.57	306.06	33.1	5
Mean value				41.7

To sum up, buffer planning algorithm of the present invention has following advantage:

1. these time slacks take full advantage of the time slack in the circuit non-critical path, so that can be used in optimization interconnection line total power consumption.

2. only need disposable definite power consumption-time slack piecewise linear model, time slack allocation algorithm afterwards has very high execution efficient.

3. have industrial application value, can be used for the IC design process: the interconnect planning problem in module level floor planning/layout.

Claims (1)

1. the buffer planning method of full-chip interconnecting line power consumption optimumization is characterized in that, described method realizes in computing machine successively according to the following steps:

Step (1). initialization

The technological parameter that power consumption calculation is used is set: supply voltage V _DD, clock frequency f _Clk, unit sizes impact damper leakage current I _Offn, unit sizes impact damper short circuit current I _Short,

The correlation parameter of impact damper: load capacitance C is set _L, drive output resistance R _d, unit sizes impact damper output resistance r _s, unit sizes impact damper input capacitance c _o, unit sizes impact damper output capacitance c _p,

The correlation parameter of interconnection line is set: unit length line capacitance c, unit length line resistance r,

The correlation parameter of power consumption-time slack branch linear model is set: the reference position a of each piecewise interval _i, final position b _i, the optimum time-delay of unit length interconnection line

The model parameter m of slope between the expression linear zone _i, n _i, and interconnection line critical length L _Crit, wherein power consumption-time slack branch linear model is:

$\mathrm{\&Delta;P}(\mathrm{\&alpha;},L,\mathrm{slack})=\left\{\begin{array}{c}0(L<=L_{\mathrm{crit}})\\ \mathrm{\&alpha;}(m_{i}L+n_i\mathrm{slack})(L>L_{\mathrm{crit}},f=\frac{\mathrm{slack}}{L\&CenterDot;{\left(\frac{\mathrm{\&tau;}}{l}\right)}_{\mathrm{opt}}}\&Element;[a_i,b_i))\end{array}\right.$

Wherein slack is the time slack, α representation signal upset probability, and L is an interconnect length;

Interconnection line critical length L _CritObtain by following formula:

$L_{\mathrm{crit}}=2\sqrt{\frac{{2r}_s(c_0+c_p)}{\mathrm{rc}}};$

Step (2). read in module and gauze information from module description file:

Step (2.1). read in the module four angular coordinate, and wide, high according to the four angular coordinate computing module of this module, and the coordinate of the corresponding lead end of module;

Step (2.2). read in the time delay information of selected module;

Step (2.3). read in gauze information, the interconnected information and the input/output relation of logging modle, and be calculated as follows the length L and the initial time delay of interconnection line:

If: the coordinate of interconnection line lead end is (x ₁, y ₁), (x ₂, y ₂),

Then: the length L of interconnection line is:

L＝|x ₁-x ₂|+|y ₁-y ₂|，

If: the initial time delay d of interconnection line _LinitFor

$d_{\mathrm{Linit}}=2\sqrt{r_s{c}_0\mathrm{rc}}(1+\sqrt{\frac{1}{2}(1+\frac{c_p}{c_0})})*L;$

Step (3). according to the module information and the interconnect information of step (2.2), structure is in order to the directed acyclic graph of the indication circuit annexation logical topology figure as circuit, node representation module among the figure, and the line between the representation module of limit, and increase a virtual input node as original all the input nodes input, simultaneously, increase the output of a virtual output node as original all output nodes, the intrinsic time-delay of dummy node all is designated as 0;

Step (4). iteration is distributed the time slack according to the following steps:

Step (4.1). the quantity of state that each limit in the directed acyclic graph is built in initial setting up is 1;

Step (4.2). calculate the time slack between each interconnection line as follows:

$\left\{\begin{array}{c}a\left(v\right)=\underset{u\&Element;\mathrm{FI}\left(v\right)}{\max }(a\left(u\right)+d\left(u\right)+d(u,v)),\\ r\left(v\right)=\underset{u\&Element;\mathrm{FO}\left(v\right)}{\min }(r\left(u\right)-d\left(v\right)-d(v,u)),\\ \mathrm{slack}(u,v)=r\left(v\right)-d\left(u\right)-a\left(u\right)-d(u,v),\end{array}\right.$

Wherein: a (v) be the time of the actual arrival of signal module v, the ns of unit,

A (u) is the time of the actual arrival of signal module u, the ns of unit,

D (v) be the intrinsic time-delay of signal by module v, the ns of unit,

D (u) is the intrinsic time-delay of signal by module u, the ns of unit,

D (u, v) for signal passes through module v, the time-delay of the interconnection line between the u, the ns of unit,

R (v) arrive the time of module v for semaphore request, the ns of unit,

R (u) is the time of semaphore request arrival module u, the ns of unit,

(u is module v v) to slack, the time slack of the interconnection line between the u, the ns of unit

FI (v) be the set of all load modules of module v,

FO (v) be the set of all output modules of module v,

Establish: the time of the virtual load module of the actual arrival of signal is 0 herein, and the time that semaphore request arrives virtual output module is the time of this module of the actual arrival of signal;

Step (4.3). for the time slack is 0 interconnection line, and the quantity of state of this interconnection line is changed to 0, in case the quantity of state of all interconnection lines is 0, iterative process finishes;

Step (4.4). be calculated as follows out the weight w on each limit among the logical topology figure of the circuit of building:

$w=\frac{\mathrm{d\&Delta;P}(\mathrm{\&alpha;},L,\mathrm{slack})}{d\left(\mathrm{slack}\right)}$

Be w be Δ P (α, L is slack) to the partial derivative of slack;

Step (4.5). utilize pre-stream propulsion method to obtain the maximum cut set of logical topology figure, the time slack is distributed on every limit in this cut set according to the following steps:

Step (4.5.1). when not inserting impact damper in the interconnection line, this interconnection line has maximum delay d _Lmax:

$d_{L\max }=\frac{1}{2}{\mathrm{rcL}}^2+(R_{d}c+r{C}_L)L+R_d{C}_L,$

Wherein: R _dFor driving output resistance (Ω), C _LBe load capacitance (fF),

And the time-delay that is in the interconnection line of state i has a upper limit constraint d _Li:

d _Li＝d _Linit(1+f _i)，

f _iBe the right endpoint value between corresponding linear zone in power consumption-time slack branch linear model, d _LminIt is the initial time delay of the interconnection line that obtains in the step 2;

If: every current time-delay in limit is d under the current state _Lcurrent, slack is the time slack of interconnection line between the module that obtains in the step 4.2,

Then: the time-delay on this limit should be updated to d _Lupdated:

d _Lupdated＝min((d _Lcurrent+slack)，d _Lmax，d _Li)；

Step (4.5.2). if d _LupdatedBe assigned d _Lcurrent+ slack or d _Lmax, then this interconnection line quantity of state is rewritten as 0, this interconnection line time slack of can not reallocating;

Step (4.5.3). if d _LupdatedBe assigned d _Li, then this interconnection line quantity of state adds 1 on the original basis;

Step (4.6). for each section interconnection line, according to size s and number N and output that time slack allocation result is calculated needed impact damper, its formula is as follows:

$\frac{k_1(c_p+c_0)}{l}+\frac{k_2}{l}+k_3(1+f){\left(\frac{\mathrm{\&tau;}}{l}\right)}_{\mathrm{opt}}-[\frac{k_{1}s(c_p+c_0)}{l^2}+\frac{k_{2}s}{l^2}]\frac{\mathrm{dl}}{\mathrm{ds}}=0$

$\frac{1}{l}{r}_s(c_p+c_0)+\frac{r_s}{s}c+\mathrm{rs}{c}_0+\frac{1}{2}\mathrm{rcl}-(1+f){\left(\frac{\mathrm{\&tau;}}{l}\right)}_{\mathrm{opt}}=0$

$[\frac{1}{2}\mathrm{rc}-\frac{r_s(c_p+c_0)}{l^2}]\frac{\mathrm{dl}}{\mathrm{ds}}+{\mathrm{rc}}_0-\frac{r_{s}c}{s^2}=0$

Wherein, $k_1=\mathrm{\&alpha;}{V}_{\mathrm{DD}}^2{f}_{\mathrm{clk}},$ $k_2=\frac{3}{2}{V}_{\mathrm{DD}}{I}_{\mathrm{offn}},$ k ₃＝ln3·αV _DDI _shortf _clk，

Wherein, s is a buffer size, i.e. the multiple of unit buffer size,

L is an interconnect length, um,

α is a signal upset probability,

V _DDBe supply voltage, V,

f _ClkBe frequency of operation, GHz,

L is the impact damper spacing, um,

c _oBe the unit buffer input capacitance, fF,

C is the unit length line capacitance, fF/um,

c _pBe the unit buffer output capacitance, fF,

I _OffnBe the unit buffer leakage current, uA,

I _ShortBe the unit buffer short-circuit current, uA,

F is time punishment, exceeds optimum number percent (%) expression of delaying time with actual time delay,

Be the optimum time-delay of unit length interconnection line, ns, setting value;

The number N of impact damper tries to achieve according to following formula:

Expression rounds downwards

Step (4.7). by the power consumption of setting each section interconnection line, calculate this circuit overall interconnect line power consumption,

The buffer planning method of full-chip interconnecting line power consumption optimumization according to claim 1 is characterized in that, described power consumption-time slack piecewise linear model is obtained according to the following steps:

Preseting length is the computing formula of power consumption P of the interconnection line of L:

$P=L*(k_1(\frac{s}{l}(c_p+c_o)+c)+k_2\frac{s}{l}+k_3(1+f)s{\left(\frac{\mathrm{\&tau;}}{l}\right)}_{\mathrm{opt}})$

Wherein, $k_{1}L(\frac{s}{l}(c_p+c_o)+c)$ Be dynamic power consumption,

Be short-circuit dissipation,

$k_{3}L(1+f)s{\left(\frac{\mathrm{\&tau;}}{l}\right)}_{\mathrm{opt}}$ Be electricity leakage power dissipation,

Wherein, $k_1=\mathrm{\&alpha;}{V}_{\mathrm{DD}}^2{f}_{\mathrm{clk}},$ $k_2=\frac{3}{2}{V}_{\mathrm{DD}}{I}_{\mathrm{offn}},$ k ₃＝ln3·αV _DDI _shortf _clk，

Wherein, L is an interconnect length, um,

α is a signal upset probability,

V _DDBe supply voltage, V,

f _ClkBe frequency of operation, GHz,

S is a buffer size, i.e. the multiple of unit buffer size,

L is the impact damper spacing, um,

c _oBe the unit buffer input capacitance, fF,

C is the unit length line capacitance, fF/um,

c _pBe the unit buffer output capacitance, fF,

I _OffnBe the unit buffer leakage current, uA,

I _ShortBe the unit buffer short-circuit current, uA,

F is time punishment, exceeds optimum number percent (%) expression of delaying time with actual time delay,

Be the optimum time-delay of unit length interconnection line, ns, setting value;

Press $L_{\mathrm{crit}}=2\sqrt{\frac{{2r}_s(c_0+c_p)}{\mathrm{rc}}}$ Calculate the critical length L of interconnection line _Crit

C) when the interconnection line length L greater than L _CritThe time, at the time punishment f that sets, under the signal upset probability α, try to achieve funtcional relationship between power consumption reduction amount and linear fit itself and the interconnect length L with the formula in the step (a);

D) at L greater than L _CritUnder the situation, as time punishment f, when interconnect length L sets, the funtcional relationship between linear plan signal upset probability α and the power consumption reduction amount.

E) under the interconnect length L of the signal of step (c) upset probability α, step (d), the relation between piecewise linearity processing time punishment f and the power consumption reduction amount Δ P obtains power consumption-time slack piecewise linear model, represents with following formula:

$\mathrm{\&Delta;P}(\mathrm{\&alpha;},L,\mathrm{slack})=\left\{\begin{array}{c}0(L<=L_{\mathrm{crit}})\\ \mathrm{\&alpha;}(m_{i}L+n_i\mathrm{slack})(L>L_{\mathrm{crit}},f=\frac{\mathrm{slack}}{L\&CenterDot;{\left(\frac{\mathrm{\&tau;}}{l}\right)}_{\mathrm{opt}}}\&Element;[a_i,b_i))\end{array}\right.$

Wherein slack is the time slack, and the time slack that on behalf of this interconnection line, i distribute is residing different interval, a _i, b _iBe two end values between each linear zone, m _i, n _iBe the model parameter that match obtains,

Be the optimum time-delay of unit length interconnection line, setting value.

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