CN104820620B - A kind of heuristic multivoltage distribution method of on-chip system - Google Patents
A kind of heuristic multivoltage distribution method of on-chip system Download PDFInfo
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Abstract
The invention discloses a kind of heuristic multivoltage distribution method of on-chip system, the method that advantage is to propose is based on heuritic approach, has taken into account the quality and solving speed of solving result.The operating voltage of all circuit macroblocks is set to low-voltage by it first, then according to the fan-in of circuit macroblock/be fanned out to delay allowance information, drafting fan-in/be fanned out to delay allowance curve, by searching crest and trough in curve, if dry circuit macroblock is selected in algorithm iteration raises its operating voltage, after the temporal constraint of on-chip system is met, algorithm terminates and exports current multivoltage allocation result.Compared to traditional integral linear programming multivoltage distribution method, the inventive method can effectively be accelerated multivoltage dispensing rate, be enriched the Automated Design optimization method of on-chip system multivoltage distribution, reduce design cost again with less solution quality cost.By case verification, the CPU solution times that the inventive method obtains effectively are reduced.
Description
Technical Field
The invention relates to an automatic design method of a system on chip, in particular to a heuristic multi-voltage distribution method of the system on chip.
Background
A system-on-a-chip (SoC) is composed of a plurality of circuit macro blocks, and the circuit macro blocks are connected by using interconnecting lines. The single voltage technique requires that all circuit macros operate at this voltage, but some of them are non-critical, i.e., located in a non-critical path or operating at a lower frequency. Therefore, the multi-voltage technology reduces the working voltage of a part of non-key modules, effectively reduces the power consumption on the premise of ensuring that the SoC meets the performance constraint, and becomes the mainstream method of the current low-power SoC design.
The multi-voltage distribution is that each circuit macro-module is distributed with a working voltage, so that the power consumption is optimized as much as possible on the premise that the time sequence constraint is met. Meanwhile, multi-voltage distribution is used as a key step of multi-voltage layout planning collaborative optimization, and the solving quality and speed are important factors to be considered. The existing research generally adopts a deterministic solution method, such as integer linear programming, to complete multi-voltage distribution, and although the solution quality is guaranteed, more CPU time is consumed, so the solution speed is slow. In particular, as the SoC size increases, integer linear programming requires more constraints, resulting in a non-linear rise in solution time.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the defects of the prior art, the method for distributing the multiple voltages of the system on the chip is provided, and the method is based on the 'delay-power consumption' information of the given circuit macro blocks, firstly, the working voltages of all the circuit macro blocks are set to be low voltages, the time sequence constraint at the moment is definitely not satisfied, a plurality of circuit macro blocks are selected in the next algorithm iteration to increase the working voltages until the time sequence constraint is satisfied, and then the current solution is output. In order to determine which circuit macro blocks need to increase the working voltage, fan-in/fan-out delay margins of the circuit macro blocks are calculated, and a fan-in/fan-out delay margin curve is drawn for the circuit macro blocks according to topological sequencing. Searching peaks and valleys in the curve, wherein the circuit macro module corresponding to the peak position shows that the circuit macro module is a non-critical module with high possibility, so that the current voltage state of the circuit macro module is locked, and the working voltage is not allowed to be increased; and for the circuit macro module corresponding to the trough, the probability that the circuit macro module is a key module is high, and therefore the circuit macro module is stored in a queue for processing. When the circuit macro-modules are taken out from the queue for processing, firstly, a critical path passing through the circuit macro-modules is searched, all the circuit macro-modules on the critical path are stored, if the circuit macro-modules work at low voltage and are not in a locking state, the circuit macro-modules needing to be boosted are selected from the circuit macro-modules according to a cost function, and the working voltage of the circuit macro-modules is set to be high voltage. In order to avoid power consumption loss caused by the fact that the voltage of the macro module of the circuit is increased after the time sequence constraint is met, the flag bit is defined to judge the ratio of the number of the interconnection lines meeting the time sequence constraint and the total number of the interconnection lines. When the time sequence constraint is close to being met, only one circuit macro module is taken out for processing in each iteration, otherwise, all the circuit macro modules stored in the queue are taken out for processing in each iteration.
The technical scheme adopted by the invention for solving the technical problems is as follows: a heuristic multi-voltage distribution method of a system on chip comprises the following steps:
step (1): the system on chip comprises multiple circuit macro modules connected by interconnection lines with N number wires Define WR slack (u, v) is the connecting circuit macroblock sb u And sb v The line delay margin of the interconnection line of (2) is calculated as follows:
WR slack (u,v)＝tr v -d uv -ta u (1)
wherein tr v For circuit macroblock sb v Required arrival time of d uv For connecting circuit macroblocks sb u And sb v Delay of interconnection line of (1), ta u For circuit macroblock sb u The arrival time of (c); the computer reads and analyzes system-on-chip layout information, time delay constraint information, coordinate information of a circuit macro module and time delay-power consumption information when the system-on-chip layout information, the time delay constraint information and the circuit macro module work at high voltage and low voltage which are provided by a user; defining Flag to be a TRUE-FALSE Flag, when Flag = FALSE indicates FALSE, and when Flag = TRUE indicates TRUE, let Flag = FALSE;
step (2): defining the set of circuit macroblocks included in the system on chip as B, for each circuit macroblock sb i E is B, and the working voltage of the B is low;
and (3): performing static time sequence analysis on the system on chip, calculating the line delay margin of all the interconnection lines, and calculating the interconnection line number N with the line delay margin larger than or equal to 0 legal ；
And (4): defining a circuit macroblock sb m There are l fan-in circuit macroblocks, { sb m1 ，sb m2 ，…，sb ml }, then circuit macroblock sb m The calculation formula of the fan-in delay margin is as follows:
defining a circuit macroblock sb n There are k fanout circuit macroblocks,namely { sb n1 ，sb n2 ，…，sb nk }, then the circuit macro-module sb n The fan-out delay margin calculation formula of (2) is as follows:
respectively calculating fan-in/fan-out delay margin values of the circuit macro modules, sequencing the circuit macro modules according to topology, and respectively drawing fan-in/fan-out delay margin curves;
and (5): searching a wave crest and a wave trough of a curve in a fan-in/fan-out delay allowance curve, and respectively storing circuit macro modules corresponding to the wave crest and the wave trough into a set P and a set Q;
and (6): traversing all circuit macroblocks, for each circuit macroblock sb i If sb i Belongs to P, let sb i Is in a locked state; if sb i Storing the circuit macro module into a queue U when the macro module belongs to Q and is not in a locking state;
and (7): calculating the ratio (ratio = N) of the interconnection lines with the line delay margin larger than or equal to 0 to the total interconnection lines legal /N wires (ii) a Define PER e (0,1) as a predefined floating point decimal if ratio&PER, let Flag = TRUE; if Flag = TRUE, selecting only one circuit macro module from the queue U for processing; if Flag = FALSE, all circuit macro-modules in the queue U are processed; for the circuit macro block sb needing processing i First, search through the macro block sb of the circuit to be processed i For all circuit macro-modules on the critical path, if the circuit macro-modules currently work at low voltage and are not in a locking state, the cost is calculated according to the following formula:
where Δ sleep and Δ power respectively denote the circuit macroblock sb that needs to be processed i Caused by the operating voltage from low to highWeight e (0,1) represents a user-defined floating point fraction that reflects the circuit macroblock sb that needs processing i The weight of (c); the circuit macro block with the lowest cost is selected to work at high voltage;
and (8): if the current time sequence constraint is met, the algorithm is terminated, and a current voltage distribution result is output; otherwise, repeating the steps (3) to (8).
Compared with the prior art, the invention has the advantages that: the multi-voltage distribution method provided by the invention based on the heuristic method can select a proper circuit macro module to increase the working voltage of the circuit macro module in each algorithm iteration process according to the fan-out/fan-out delay margin information of the circuit macro module, and can slow down the number of the circuit macro modules which need to increase the working voltage each time when the time sequence constraint is approximately met, thereby optimizing the power consumption to the maximum extent on the premise of meeting the time sequence constraint. The multi-voltage distribution method can give consideration to the solving quality and speed, and is not only suitable for the post-layout optimization stage, but also suitable for the multi-voltage layout collaborative optimization stage. Compared with the traditional multi-voltage distribution method of the system on chip, the method disclosed by the invention can greatly improve the solving speed, can obtain a better voltage distribution result in a faster time, and can obtain a better solving result by integrating the method into multi-voltage layout planning collaborative optimization. The invention provides a new idea for multi-voltage distribution of the system on chip, which not only enriches the automatic design optimization method of the multi-voltage distribution of the system on chip, but also reduces the design cost, and has stronger practical significance and practical significance for multi-voltage SoC design.
Drawings
FIG. 1 is a physical layout representation of a GSRC benchmark circuit n 10;
FIG. 2 is a schematic diagram of interconnection line connections for GSRC benchmark circuit n 10;
fig. 3 is a graph of fan-in/fan-out delay margin.
Detailed Description
The invention is described in further detail below with reference to the examples of the drawings.
FIG. 1 shows a layout representation of a GSRC benchmark circuit n10, which includes 10 circuit macroblocks { sb } 0 ，sb 1 ，…，sb 9 }. Fig. 2 is a schematic diagram illustrating interconnection connections of GSRC benchmark circuit n 10.
The heuristic multi-voltage distribution method for the n10 system on chip comprises the following steps of:
step (1): the system on chip consists of 10 circuit macroblocks sb 0 ，sb 1 ，…，sb 9 The macro modules of the circuit are connected by adopting interconnecting lines, and the number of the interconnecting lines is N wires From FIG. 2, N is shown wires =23, define WR slack (u, v) is the connecting circuit macroblock sb u And sb v The line delay margin of the interconnection line of (2) is calculated as follows:
WR slack (u,v)＝tr v -d uv -ta u (1)
wherein tr v For circuit macroblock sb v Required arrival time of d uv For connecting circuit macroblocks sb u And sb v Delay of the interconnection line of (1), ta u For circuit macroblock sb u The arrival time of (c); reading and analyzing system-on-chip layout information, time delay constraint information, coordinate information of the circuit macro module and time delay-power consumption information when the circuit macro module works at high voltage and low voltage, wherein the time delay-power consumption information of the circuit macro module contained in n10 is shown in a table I; defining Flag to be a TRUE-FALSE Flag, when Flag = FALSE indicates FALSE, and when Flag = TRUE indicates TRUE, let Flag = FALSE;
step (2): defining the set of circuit macroblocks included in the system on chip as B, for each circuit macroblock sb i E.g. B, the working voltage is low, i.e. n10 comprises 10 circuit macro blocks { sb 0 ，sb 1 ，…，sb 9 All work at low voltage;
and (3): performing static timing analysis on the system on chip, and calculating the line delay margins of all the interconnection lines, wherein the calculation result is as follows:
WR slack (0,2)＝-139165.5；WR slack (0,9)＝-184132.5；WR slack (1,0)＝-184132.5；
WR slack (1,4)＝-186378.5；WR slack (3,0)＝-47398.5；WR slack (3,1)＝-107672.5；
WR slack (3,5)＝-186378.5；WR slack (4,9)＝-186378.5；WR slack (5,0)＝-126114.5；
WR slack (5,1)＝-186378.5；WR slack (5,2)＝-37599.5；WR slack (5,9)＝-82600.5；
WR slack (6,2)＝177298.5；WR slack (6,3)＝-101456.5；WR slack (6,5)＝-50632.5；
WR slack (6,8)＝-172329.5；WR slack (7,1)＝-56104.5；WR slack (7,3)＝-186378.5；
WR slack (7,9)＝47883.5；WR slack (8,1)＝-42709.5；WR slack (8,2)＝106451.5；
WR slack (8,3)＝-172329.5；WR slack (8,9)＝61606.5；
and calculating the number N of interconnection lines with the line delay margin larger than or equal to 0 legal ＝4；
And (4): defining a circuit macroblock sb m There are l fan-in circuit macroblocks, { sb m1 ，sb m2 ，…，sb ml }, then the circuit macro-module sb m The calculation formula of the fan-in delay margin is as follows:
the result of calculating the fan-in delay margin of the circuit macro block is as follows:
FIN slack (sb 8 )＝-172329.5；FIN slack (sb 3 )＝-460164.5；FIN slack (sb 5 )＝-237011；
FIN slack (sb 1 )＝-392865；FIN slack (sb 0 )＝-357645.5；FIN slack (sb 4 )＝-186378.5；
FIN slack (sb 2 )＝106985；FIN slack (sb 9 )＝-343621.5；
defining a circuit macroblock sb n With k fanout circuit macroblocks, i.e. { sb n1 ，sb n2 ，…，sb nk }, then the circuit macro-module sb n The fan-out delay margin calculation formula is as follows:
the result of calculating the fan-out delay margin of the macro block of the circuit is as follows:
FOUT slack (sb 6 )＝-147120；FOUT slack (sb 7 )＝-194599.5；FOUT slack (sb 8 )＝-46981；
FOUT slack (sb 3 )＝-341449.5；FOUT slack (sb 5 )＝-432693；FOUT slack (sb 1 )＝-370511；
FOUT slack (sb 0 )＝-323298；FOUT slack (sb 4 )＝-186378.5；
respectively calculating fan-in/fan-out delay margin values of the circuit macro modules, sequencing the circuit macro modules according to topology, and respectively drawing fan-in/fan-out delay margin curves, as shown in fig. 3;
and (5): searching a wave crest and a wave trough of a curve in a fan-in/fan-out delay allowance curve, and respectively storing circuit macro modules corresponding to the wave crest and the wave trough into a set P and a set Q; fig. 3 shows that the macro block of the circuit corresponding to the peak is sb 2 、sb 5 And sb 8 Then P = { sb = 2 ,sb 5 ,sb 8 }; the circuit macro block corresponding to the wave trough is sb 1 、sb 3 And sb 5 Then Q = { sb = 1 ,sb 3 ,sb 5 }; it can be seen that sb 5 Namely the wave crest of the fan-in delay curve and the wave trough of the fan-out delay curve, the circuit macro-module can be locked in the subsequent process and does not participate in the processing;
and (6): traversing all circuit macroblocks, for each circuit macroblock sb i If sb i Belongs to P, let sb i In the locked state, sb 2 、sb 5 And sb 8 The working voltages of the two-phase converter are all in a locking state; if sb i E is Q, and is not in a locking state, and the circuit macro module is stored into a queue U, then U = { sb 1 ,sb 3 }；
And (7): calculating the ratio (ratio = N) of the interconnection lines with the line delay margin larger than or equal to 0 to the total interconnection lines legal /N wires =4/23=0.17; defining PER e (0,1) as a predefined floating point decimal if predefined PER =0.8 if ratio&PER, let Flag = TRUE, here ratio&PER, flag is still FALSE; if Flag = TRUE, selecting only one circuit macro module from the queue U for processing; if Flag = FALSE, processing all circuit macros in the queue U; if Flag = FALSE is satisfied, sb is taken out of U 1 And sb 3 Carrying out treatment; for the circuit macro block sb needing to be processed i With sb 1 For example, first search through sb 1 For all circuit macroblocks on the critical path, i.e. path { sb 7 -sb 3 -sb 5 -sb 1 -sb 4 -sb 9 If the current work is in low voltage and not in locking state, the cost is calculated according to the following formula, and the qualified circuit macro module comprises sb 7 ，sb 3 ，sb 1 ，sb 4 ，sb 9 ，
Where Δ sleep and Δ power respectively denote the circuit macroblock sb that needs to be processed i From low voltageThe increment of delay margin and the increment of power consumption caused by pressing to high voltage, weight epsilon (0,1) represents a floating point decimal defined by a user and is used for reflecting the circuit macro block sb needing to be processed i The weight of (1), the weight and the 'delay-power consumption' information of the circuit macro block are shown in table one; the calculation results are as follows:
the circuit macroblock with the lowest cost is selected to operate at a high voltage, sb 3 The operating voltage of (2) rises;
and (8): if the current time sequence constraint is met, the algorithm is terminated, and the current voltage distribution result is output; otherwise, repeating the steps (3) to (8), wherein the time sequence still does not meet the requirement, and the steps (3) to (8) need to be continuously repeated.
Watch 1
| Circuit macroblock name | Weight of | High voltage time delay | Power consumption at high voltage | Delay at low voltage | Low power consumption at voltage |
| sb 0 | 0.90 | 16318 | 16318 | 43514 | 7252 |
| sb 1 | 1.00 | 21640 | 24045 | 57706 | 10686 |
| sb 2 | 0.75 | 7850 | 7137 | 20933 | 3172 |
| sb 3 | 1.00 | 19038 | 17134 | 50768 | 7615 |
| sb 4 | 0.80 | 17035 | 18928 | 45426 | 8412 |
| sb 5 | 0.95 | 29515 | 26832 | 78706 | 11925 |
| sb 6 | 0.90 | 14612 | 13284 | 38965 | 5904 |
| sb 7 | 0.85 | 46271 | 42065 | 123389 | 18695 |
| sb 8 | 0.75 | 26402 | 26402 | 70405 | 11734 |
| sb 9 | 0.85 | 24696 | 24696 | 65856 | 10976 |
By testing the GSRC reference test circuit, the multi-voltage distribution method provided by the invention is applied to multi-voltage SoC layout planning collaborative optimization, and the obtained power consumption and CPU operation time details are shown in a table II:
watch 2
It can be seen that although the power consumption optimization result of the multi-voltage distribution method provided by the invention is sacrificed by 3% on average compared with the traditional integer linear programming method, the running time of the CPU is increased by 18.42 times on average, so that the solving time of the CPU is effectively reduced. Therefore, the method can effectively accelerate the multi-voltage distribution speed with lower solving quality cost, enrich the automatic design optimization method of the multi-voltage distribution of the system on chip and reduce the design cost.
Claims (1)
1. A heuristic multi-voltage distribution method of a system on a chip is characterized by comprising the following steps:
step (1): the system on chip comprises multiple circuit macro modules connected by interconnection lines with N number wires Define WR slack (u, v) is the connecting circuit macroblock sb u And sb v The line delay margin of the interconnection line of (2) is calculated as follows:
WR slack (u,v)＝tr v -d uv -ta u (1)
wherein tr v For circuit macroblock sb v Required arrival time of d uv For connecting circuit macroblocks sb u And sb v Delay of the interconnection line of (1), ta u For circuit macroblock sb u The arrival time of (c); the computer reads and analyzes the layout information, time delay constraint information and coordinate information of the circuit macro module of the system-on-chip provided by the userInformation of time delay-power consumption when working at high voltage and low voltage; defining Flag to be a TRUE-FALSE Flag, when Flag = FALSE indicates FALSE, and when Flag = TRUE indicates TRUE, let Flag = FALSE;
step (2): defining the set of circuit macroblocks included in the system on chip as B, for each circuit macroblock sb i E is B, and the working voltage of the B is low;
and (3): performing static time sequence analysis on the system on chip, calculating the line delay margin of all the interconnection lines, and calculating the number N of the interconnection lines with the line delay margin more than or equal to 0 legal ；
And (4): defining a circuit macroblock sb m There are l fan-in circuit macroblocks, { sb m1 ，sb m2 ，…，sb ml }, then the circuit macro-module sb m The calculation formula of the fan-in delay margin is as follows:
defining a circuit macroblock sb n With k fan-out macro blocks, i.e. { sb n1 ，sb n2 ，…，sb nk }, then the circuit macro-module sb n The fan-out delay margin calculation formula is as follows:
respectively calculating fan-in/fan-out delay margin values of the circuit macro modules, sequencing the circuit macro modules according to topology, and respectively drawing fan-in/fan-out delay margin curves;
and (5): searching a wave crest and a wave trough of a curve in a fan-in/fan-out delay allowance curve, and respectively storing circuit macro modules corresponding to the wave crest and the wave trough into a set P and a set Q;
and (6): traversing all circuit macroblocks, for each circuit macroblock sb i If sb i Belongs to P, let sb i Is in a locked state; if sb i Is epsilon of Q and is not in lockStatus, storing the circuit macro into a queue U;
and (7): calculating the ratio (ratio = N) of the interconnection lines with the line delay margin larger than or equal to 0 to the total interconnection lines legal /N wires (ii) a Define PER e (0,1) as a predefined floating point decimal if ratio&PER, let Flag = TRUE; if Flag = TRUE, selecting only one circuit macro module from the queue U for processing; if Flag = FALSE, all circuit macro-modules in the queue U are processed; for the circuit macro block sb needing to be processed i First, search through the macro block sb of the circuit to be processed i For all circuit macro-modules on the critical path, if the circuit macro-modules currently work at low voltage and are not in a locking state, the cost is calculated according to the following formula:
where Δ sleep and Δ power respectively denote the circuit macroblock sb that needs to be processed i The weight e (0,1) represents a floating point decimal defined by a user and is used for reflecting the circuit macro block sb needing to be processed i The weight of (c); the circuit macro block with the lowest cost is selected to work at high voltage;
and (8): if the current time sequence constraint is met, the algorithm is terminated, and a current voltage distribution result is output; otherwise, repeating the steps (3) to (8).
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| US8370779B1 (en) * | 2005-02-14 | 2013-02-05 | Cadence Design Systems, Inc. | Method and system for power distribution analysis |
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