CN104021240A - System-on-chip layout planning method oriented towards multi-supply-voltage technique - Google Patents

Abstract

The invention discloses a system-on-chip layout planning method oriented towards the multi-supply-voltage technique. The system-on-chip layout planning method has the advantages that a virtual level shifter can be inserted to provide enough blank areas for distribution of a level shifter in a layout according to static timing analysis of a netlist; in addition, in the layout step, physic information of the distribution of the level shifter is fed back to a voltage for allocation by building internal circulation, so that a generated layout solution synchronously meets the timing sequence and physic constraint. Compared with an existing system-on-chip layout planning method oriented towards the multi-supply-voltage technique, the method can further reduce power consumption. Automatic design optimization methods of a system on chip are enriched, and design cost is reduced. Examples verify that the layout of the level shifter can be effectively completed through the blank areas obtained through the method, and the power consumption is reduced.

Description

A kind of SOC (system on a chip) layout planning method towards many supply voltages technology

Technical field

The present invention relates to a kind of the Automation Design method of SOC (system on a chip), especially relate to a kind of SOC (system on a chip) layout planning method towards many supply voltages technology.

Background technology

Because dynamic power consumption and the supply voltage of chip are quadratic relationship, carrying out low power dissipation design by reduction supply voltage is effectively the most direct optimal way.SOC (system on a chip) is made up of circuit macroblock (hereinafter to be referred as module), multivoltage system-on-chip designs is just based on this principle, ensureing under the prerequisite of SOC (system on a chip) performance, by distributing high voltage to key modules, and reach the object of optimised power consumption to non-key module assignment low voltage, be the main flow method for designing of current SOC (system on a chip) low power dissipation design.

But, in the design process of multivoltage SOC (system on a chip), in the time that low-voltage module directly drives high-voltage module, because extra quiescent current will produce leakage power, even logic error, therefore must between low-voltage module and high-voltage module, insert level shifter (level shifter, LS) and complete the coupling of voltage domain.This brings the problem of two aspects to the floor planning of multivoltage SOC (system on a chip).First be the location problem of level shifter, because it has certain area overhead, in Butut, must have enough blank areas; Next is the module voltage assignment problem under temporal constraint, and level shifter has the delay overhead of certain time delay and interconnection generation equally, must just can complete voltage distribution in conjunction with the physical message of level shifter.

B.Yu, S.Dong, the article " Voltage-island driven floorplanning considering level-shifter positions " that S.Goto etc. deliver at ACM Great Lakes Symposium on VLSI in 2009 is studied for the SOC (system on a chip) layout planning method towards many supply voltages technology, in the time carrying out level shifter layout, because there is no enough blank areas, the method is as much as possible completes layout to level shifter, for the level shifter of the remaining layout that fails after floor planning completes, after, the Butut stage is further optimized.The method is deposited defect both ways: on the one hand, the layout solution space in rear Butut stage is limited, and not only power consumption improvement is limited, and can cause sequential to be difficult to convergence; On the other hand, if rear Butut is unsuccessful, need re-start Butut, cause design to be difficult to convergence.

For above-mentioned existing methods defect, need to carry out on the one hand the management work of Butut empty area, make existing enough blank areas for level shifter layout, be unlikely to make again layout area sharply to increase; On the other hand, voltage distribution needs and the layout of level shifter produces loop iteration, has fed back voltage distribution by the physical message of level shifter, and temporal constraint and physical constraint are met simultaneously, and optimizing power consumption.Therefore the inventive method is for having stronger realistic meaning and practice significance towards the system-on-chip designs of many supply voltages technology.

Summary of the invention

Technical matters to be solved by this invention is to provide a kind of SOC (system on a chip) layout planning method towards many supply voltages technology, the implementation phase of being divided into two: net table modification stage and Butut stage.First carry out static timing analysis for net heading, obtain the time delay allowance of each module, the simulation based on probability of carrying out based on this module voltage distributes, after assigning process completes, traversal net table, in the time of low-voltage module drive high-voltage module, insert virtual level shifter, and upgrade net table, to occupying blank area in the Butut stage.In the Butut stage, first the net table based on after upgrading produces Butut feasible solution; Then it is carried out to the voltage distribution under temporal constraint; Obtain inserting number and the link information of level shifter according to allocation result, then in the blank area of Butut, carry out the layout of level shifter, if do not meet temporal constraint after layout, the physical message of layout is fed back to voltage distribution step, by the lax temporal constraint of operating voltage of rising module, proceed again the layout of level shifter, form a circulation until sequential and physical constraint are jumped out circulation after being all met with this; To current Butut feasible solution, by cost function comprehensive assessment line length, area and power consumption, then disturbance Butut produces new feasible solution, until reach floor planning end condition, the Butut result of output level shift unit and module.

The present invention solves the problems of the technologies described above adopted technical scheme:

1, towards a SOC (system on a chip) layout planning method for many supply voltages technology, it is characterized in that comprising the following steps:

Step is 1.: definition net table is the description document of the length and width information, time delay-power consumption information and the link information that comprise circuit macroblock; Defining virtual level shifter is to be present in the circuit macroblock with level shifter in net table with identical size, time delay and power consumption; The net table providing with analysis user is provided computing machine, by static timing analysis, calculates the time delay allowance of each circuit macroblock, inserts virtual level shifter in net table, and upgrades net table;

Step is 2.: based on the net table after upgrading, produce Butut feasible solution;

Step is 3.: when Butut feasible solution is first when voltage distribution, under the prerequisite that meets temporal constraint, coordinate information and wire length information based on circuit macroblock in Butut feasible solution are carried out voltage distribution; In the time of the non-voltage distribution first of Butut feasible solution, based on current voltage allocation result, by the operating voltage of some circuit macroblocks that are operated in low-voltage is raise, re-start voltage distribution;

Step is 4.: based on the result of voltage distribution, utilize blank area in Butut feasible solution to carry out the layout of level shifter;

Step is 5.: in conjunction with the physical message after level shifter layout, in the time that circuit macroblocks all in net table all meets temporal constraint, continue next step; In the time existing circuit macroblock not meet temporal constraint in net table, turn back to step 3.;

Step is 6.: adopt cost function to assess to current cloth diagram, obtain value at cost C _curr, work as C _currbe less than current minimum cost value C _besttime, upgrading current minimum cost value is C _curr; Work as C _currbe more than or equal to current minimum cost value C _besttime, continue next step;

Step is 7.: when Butut disturbance number of times p is less than the upper limit number of times p of setting _maxtime, disturbance Butut produces new Butut feasible solution, and Butut disturbance time counting number adds 1, and turns back to step 2.; When Butut disturbance number of times equals the upper limit number of times p setting _maxtime, Output rusults.

2, step 1. in the method that is inserted in net table of virtual level shifter comprise the following steps:

Step 1.-a: the time delay allowance of definition circuit macroblock i is sck _i, the average delay allowance of all circuit macroblocks is sck _avg, minimal time delay allowance is sck _min, definition probability mass function is

$\mathrm{pmf}\left(i\right)=1-\exp (-\frac{{\mathrm{sck}}_i-{\mathrm{sck}}_{\min }}{\mathrm{\α}\×{\mathrm{sck}}_{\mathrm{avg}}})---\left(1\right)$

Wherein α is greater than 0 real number; For the random floating number rand () between 0 and 1 producing of circuit macroblock i, in the time that rand () is less than or equal to pmf (i), think that circuit macroblock i is operated in low-voltage; In the time that rand () is greater than pmf (i), think that circuit macroblock i is operated in high voltage;

Step 1.-b: travel through all circuit macroblocks, obtain the operating voltage state of each circuit macroblock;

Step 1.-c: traversal net table, in the time having low voltage circuit macroblock to drive high voltage circuit macroblock in net table, insert virtual level shifter in the middle of this low voltage circuit macroblock and high voltage circuit macroblock, and upgrade net table.

3, step 4. in the layout method of level shifter comprise the following steps:

Step 4.-a: in Butut feasible solution, the blank area that the intrinsic blank area of search circuit macroblock Butut combination results and virtual level shifter occupy;

Step 4.-b: according to the size of level shifter, the blank area hunting out is divided into the feasible layout website of level shifter;

Step 4.-c: according to the result of voltage distribution, required level shifter is assigned in a unique feasible website one by one.

Compared with prior art, the method that the invention has the advantages that proposition can be carried out anticipation according to net table, by the mode of inserting virtual level shifter, the blank area of Butut stage generation is managed, so that the layout of level shifter, suitable layout contributes to reduce the length of line, thereby reduce connecting line time delay, reach the object of optimizing power consumption; In addition, the voltage distribution in Butut stage and the layout of level shifter solve by circulation, the physical message of level shifter feeds back to voltage distribution, circulation is until sequential and physical constraint are met rear termination simultaneously, can go bail for and obtain the feasible solution of level shifter layout by an inner loop, improve towards the speed of convergence of the system-on-chip designs of many supply voltages technology.Than the SOC (system on a chip) layout planning method towards many supply voltages technology of having delivered, the method for proposition is optimizing power consumption further.

Brief description of the drawings

Fig. 1 is the annexation schematic diagram of exemplary circuit;

Fig. 2 is the annexation schematic diagram upgrading after virtual level shifter inserts;

Fig. 3 is the Butut feasible solution schematic diagram producing based on the net table upgrading;

Fig. 4 is the feasible position view of level shifter layout;

Fig. 5 is the Butut after level shifter layout completes;

Fig. 6 is process flow diagram of the present invention.

Embodiment

Table 1 exemplary circuit net table information

Below in conjunction with accompanying drawing example, the present invention is described in further detail.

Towards a SOC (system on a chip) layout planning method for many supply voltages technology, it is characterized in that comprising the following steps:

Step is 1.: definition net table is the description document of the length and width information, time delay-power consumption information and the link information that comprise circuit macroblock, table 1 is depicted as the net table information of example, comprise 6 circuit macroblock b0～b5, in table, provide the length and width information of module, the visible VDDH of time delay-power consumption information and VDDL row, the size that represents respectively each module time delay and power consumption under high voltage and low-voltage, the annexation of module is shown in Fig. 1; Defining virtual level shifter is for being present in net table, has the circuit macroblock of identical size, time delay and power consumption with level shifter; The net table providing with analysis user is provided computing machine, by static timing analysis, calculates the time delay allowance of each circuit macroblock, inserts virtual level shifter in net table, and upgrades net table;

Step is 2.: based on the net table after upgrading, produce Butut feasible solution; As shown in Fig. 3 (a), in the time not adding virtual level shifter, the blank area in Butut feasible solution is less, can not complete the layout of level shifter; As shown in Fig. 3 (b), increase after virtual level shifter, it has occupied certain area in Butut feasible solution, and highly just in time equal actual level shifter, therefore, facilitated layout, empty wire frame representation link block b2 in figure and the bounding box of b3, level shifter layout can not cause extra line expense in frame, can not cause extra time delay, is the ideal situation of level shifter layout.

Step is 3.: when Butut feasible solution is first when voltage distribution, under the prerequisite that meets temporal constraint, coordinate information and wire length information based on circuit macroblock in Butut feasible solution are carried out voltage distribution; In the time of the non-voltage distribution first of Butut feasible solution, based on current voltage allocation result, by the operating voltage of some circuit macroblocks that are operated in low-voltage is raise, re-start voltage distribution; Current is the distribution first of voltage, and the maximum delay that temporal constraint refers to all circuit macroblocks in net table must be less than clock period T _cycleif set T _cyclevalue be module 1.5 times of maximum delay while being all operated in VDDH, T _cycle=86511 × 1.5=129766.5, now can be according to document W.-P.Lee, H.-Y.Liu, the integral linear programming method that Y.-W.Chang proposes at the paper " An ILP algorithm for post-foorplanning voltage-island generation considering power-network planning " delivered of International Conference on Computer Aided Design (ICCAD) in 2007 solves, and obtains voltage distribution result.Represent VDDL with low, high represents VDDH, and result is b0=high, b1=high, and b2=high, b3=high, b4=low, b5=low, obtaining power consumption is 84971; If be not the distribution first of voltage current, for instance, if the temporal constraint between b4 and b2 is violated, the operating voltage of the b4 that raises is high, can obtain so larger time delay allowance, needn't be now that b4 and b2 insert level shifter, the corresponding rising of power consumption.

Step is 4.: based on the result of voltage distribution, utilize blank area in Butut feasible solution to carry out the layout of level shifter;

Step is 5.: in conjunction with the physical message after level shifter layout, in the time that circuit macroblocks all in net table all meets temporal constraint, continue next step; In the time existing circuit macroblock not meet temporal constraint in net table, turn back to step 3.; In this example, temporal constraint is met.

Step is 6.: adopt cost function to assess to current cloth diagram, obtain value at cost C _curr, work as C _currbe less than current minimum cost value C _besttime, upgrading current minimum cost value is C _curr; Work as C _currbe more than or equal to current minimum cost value C _besttime, continue next step; Arranging of cost function can be the convex combination of power consumption, area and line length, and for convenience of description, in this example, hypothesis is only taking power consumption as calculating target, C _best=90000, because of most current cost value C _curr=84971, be less than C _best, upgrade current minimum cost value C _bestbe 84971, i.e. C _best=84971;

Step is 7.: when Butut disturbance number of times _pbe less than the upper limit number of times p of setting _maxtime, disturbance Butut produces new Butut feasible solution, and Butut disturbance time counting number adds 1, and turns back to step 2.; When Butut disturbance number of times equals the upper limit number of times p setting _maxtime, Output rusults.Suppose the upper limit number of times p that Butut disturbance is set _maxbe 100, current disturbance number of times p is 1, is less than p _max, Butut disturbance number of times _pcounting adds 1, _pbe 1, turn back to step and 2. continue.

2, step 1. in the method that is inserted in net table of virtual level shifter comprise the following steps:

Step 1.-a: the time delay allowance of definition circuit macroblock i is sck _i, the average delay allowance of all circuit macroblocks is sck _avgminimal time delay allowance is sckmin, in the time that supposition module is all operated in VDDH, carry out static timing analysis, obtain the time delay allowance sck (b0)=0 of module, sck (b1)=0, sck (b2)=21665, sck (b3)=0, sck (b4)=26270, sck (b5)=0, in addition sck, _avg=7989.1, sck _min=0, definition probability mass function is

$\mathrm{pmf}\left(i\right)=1-\exp (-\frac{{\mathrm{sck}}_i-{\mathrm{sck}}_{\min }}{\mathrm{\α}\×{\mathrm{sck}}_{\mathrm{avg}}})---\left(1\right)$

Wherein α is greater than 0 real number, supposes α=1; For the random floating number rand () between 0 and 1 producing of circuit macroblock i, in the time that rand () is less than or equal to pmf (i), think that circuit macroblock i is operated in low-voltage; In the time that rand () is greater than pmf (i), think that circuit macroblock i is operated in high voltage; The module i that is 0 for time delay allowance, pmf (i)=1-1=0, therefore needs to be operated in high voltage, and this coincide with the character that is operated in the key modules in critical path.

Step 1.-b: travel through all circuit macroblocks, obtain the operating voltage state of each circuit macroblock; For b2,

$\mathrm{pmf}\left(i\right)=1-\exp (-\frac{{\mathrm{sck}}_i-{\mathrm{sck}}_{\min }}{\mathrm{\α}\×{\mathrm{sck}}_{\mathrm{avg}}})=1-\exp (-\frac{21665-0}{1\×7989.1})=0.933$

The random floating number rand () between 0 and 1 producing, it has greater probability to be less than 0.933, if rand ()=0.789 arranges b2 and is operated in low-voltage.For b4,

$\mathrm{pmf}\left(i\right)=1-\exp (-\frac{{\mathrm{sck}}_i-{\mathrm{sck}}_{\min }}{\mathrm{\α}\×{\mathrm{sck}}_{\mathrm{avg}}})=1-\exp (-\frac{26270-0}{1\×7989.1})=0.963$

The random floating number rand () between 0 and 1 producing, it has greater probability to be less than 0.963, if rand ()=0.327 arranges b4 and is operated in low-voltage.

Step 1.-c: traversal net table, in the time having low voltage circuit macroblock to drive high voltage circuit macroblock in net table, insert virtual level shifter in the middle of this low voltage circuit macroblock and high voltage circuit macroblock, and upgrade net table.According to allocation result, Fig. 2 is shown in by the net table of renewal, and wherein LS represents level shifter.

3, step 4. in the layout method of level shifter comprise the following steps:

Step 4.-a: in Butut feasible solution, the blank area that the intrinsic blank area of search circuit macroblock Butut combination results and virtual level shifter occupy;

Step 4.-b: according to the size of level shifter, the blank area hunting out is divided into the feasible layout website of level shifter, as shown in Figure 4, in the blank area in Butut feasible solution, finds out the layout site location that LS is feasible;

Step 4.-c: according to the result of voltage distribution, required level shifter is assigned in a unique feasible website one by one, according to the module annexation shown in step voltage distribution result and Fig. 1 3., b4 and b2, between b5 and b3, need to insert level shifter, layout result as shown in Figure 5, wherein LS1 is between b5 and b3, and LS2 is the level shifter between b4 and b2.

Figure 6 shows that process flow diagram of the present invention.

To the test result of the concentrated circuit of GSRC test circuit in table 2, previously method referred to B.Yu, S.Dong, the article " Voltage-island driven floorplanning considering level-shifter positions " that S.Goto etc. deliver at ACM Great Lakes Symposium on VLSI in 2009.The present invention on average optimizes 15% power consumption.

Table 2 circuit test results

Claims (3)

1. towards a SOC (system on a chip) layout planning method for many supply voltages technology, it is characterized in that comprising the following steps:

Step is 1.: definition net table is the description document of the length and width information, time delay-power consumption information and the link information that comprise circuit macroblock; Defining virtual level shifter is to be present in the circuit macroblock with level shifter in net table with identical size, time delay and power consumption; The net table providing with analysis user is provided computing machine, by static timing analysis, calculates the time delay allowance of each circuit macroblock, inserts virtual level shifter in net table, and upgrades net table;

Step is 2.: based on the net table after upgrading, produce Butut feasible solution;

Step is 3.: when Butut feasible solution is first when voltage distribution, under the prerequisite that meets temporal constraint, coordinate information and wire length information based on circuit macroblock in Butut feasible solution are carried out voltage distribution; In the time of the non-voltage distribution first of Butut feasible solution, based on current voltage allocation result, by the operating voltage of some circuit macroblocks that are operated in low-voltage is raise, re-start voltage distribution;

Step is 4.: based on the result of voltage distribution, utilize blank area in Butut feasible solution to carry out the layout of level shifter;

Step is 5.: in conjunction with the physical message after level shifter layout, in the time that circuit macroblocks all in net table all meets temporal constraint, continue next step; In the time existing circuit macroblock not meet temporal constraint in net table, turn back to step 3.;

Step is 6.: adopt cost function to assess to current cloth diagram, obtain value at cost C _curr, work as C _currbe less than current minimum cost value C _besttime, upgrading current minimum cost value is C _curr; Work as C _currbe more than or equal to current minimum cost value C _besttime, continue next step;

Step is 7.: when Butut disturbance number of times p is less than the upper limit number of times p of setting _maxtime, disturbance Butut produces new Butut feasible solution, and Butut disturbance time counting number adds 1, and turns back to step 2.; When Butut disturbance number of times equals the upper limit number of times p setting _maxtime, Output rusults.

2. the SOC (system on a chip) layout planning method towards many supply voltages technology as claimed in claim 1, is characterized in that, step 1. in the method that is inserted in net table of virtual level shifter comprise the following steps:

Step 1.-a: the time delay allowance of definition circuit macroblock i is sck _i, the average delay allowance of all circuit macroblocks is sck _avg, minimal time delay allowance is sck _min, definition probability mass function is

$\mathrm{pmf}\left(i\right)=1-\exp (-\frac{{\mathrm{sck}}_i-{\mathrm{sck}}_{\min }}{\mathrm{\α}\×{\mathrm{sck}}_{\mathrm{avg}}})---\left(1\right)$

Wherein α is greater than 0 real number; For the random floating number rand () between 0 and 1 producing of circuit macroblock i, in the time that rand () is less than or equal to pmf (i), think that circuit macroblock i is operated in low-voltage; In the time that rand () is greater than pmf (i), think that circuit macroblock i is operated in high voltage;

Step 1.-b: travel through all circuit macroblocks, obtain the operating voltage state of each circuit macroblock;

Step 1.-c: traversal net table, in the time having low voltage circuit macroblock to drive high voltage circuit macroblock in net table, insert virtual level shifter in the middle of this low voltage circuit macroblock and high voltage circuit macroblock, and upgrade net table.

3. the SOC (system on a chip) layout planning method towards many supply voltages technology as claimed in claim 1, is characterized in that, the step 4. layout method of middle level shifter comprises the following steps:

Step 4.-a: in Butut feasible solution, the blank area that the intrinsic blank area of search circuit macroblock Butut combination results and virtual level shifter occupy;

Step 4.-b: according to the size of level shifter, the blank area hunting out is divided into the feasible layout website of level shifter;

Step 4.-c: according to the result of voltage distribution, required level shifter is assigned in a unique feasible website one by one.