CN104021240B - System-on-chip layout planning method oriented towards multi-supply-voltage technique - Google Patents
System-on-chip layout planning method oriented towards multi-supply-voltage technique Download PDFInfo
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Abstract
The invention discloses a system-on-chip layout planning method oriented towards the multi-supply-voltage technique. The system-on-chip layout planning method has the advantages that a virtual level shifter can be inserted to provide enough blank areas for distribution of a level shifter in a layout according to static timing analysis of a netlist; in addition, in the layout step, physic information of the distribution of the level shifter is fed back to a voltage for allocation by building internal circulation, so that a generated layout solution synchronously meets the timing sequence and physic constraint. Compared with an existing system-on-chip layout planning method oriented towards the multi-supply-voltage technique, the method can further reduce power consumption. Automatic design optimization methods of a system on chip are enriched, and design cost is reduced. Examples verify that the layout of the level shifter can be effectively completed through the blank areas obtained through the method, and the power consumption is reduced.
Description
Technical field
The present invention relates to a kind of the Automation Design method of SOC(system on a chip), more particularly, to one kind towards many supply voltage skills
The SOC(system on a chip) layout planning method of art.
Background technology
Because the dynamic power consumption of chip is in square with supply voltage, carrying out low power dissipation design by reduction supply voltage is
Most effective direct optimal way.SOC(system on a chip) is made up of circuit macroblock (hereinafter referred to as module), and multivoltage SOC(system on a chip) sets
Meter is based on this principle, on the premise of SOC(system on a chip) performance is ensured, by distributing high voltage to key modules, and gives non-
Key modules distribution low voltage reaches the purpose of optimised power consumption, is the mainstay side of system low-power consumption design in current slice
Method.
However, in the design process of multivoltage SOC(system on a chip), when low-voltage module directly drives high-voltage module, because
Extra quiescent current will produce leakage power, or even logical error, it is therefore necessary between low-voltage module and high-voltage module
Insert level shifter (level shifter, LS) to complete the matching of voltage domain.This is advised to the Butut of multivoltage SOC(system on a chip)
Draw problem of both bringing.It is the location problem of level shifter first, because which has certain area overhead, in Butut
There must be enough blank areas；Next to that the module voltage assignment problem under temporal constraint, level shifter is equally with one
The delay overhead that fixed time delay and interconnection are produced, it is necessary to can just complete voltage distribution with reference to the physical message of level shifter.
The text that B.Yu, S.Dong, S.Goto etc. are delivered in ACM Great Lakes Symposium on VLSI in 2009
Chapter《Voltage-island driven floorplanning considering level-shifter positions》Pin
SOC(system on a chip) layout planning method towards many supply voltage technologies is studied, when level shifter layout is carried out,
Because not having enough blank areas, the method is as much as possible to complete layout to level shifter, fails for remaining
Then after the completion of floor planning, i.e., rear layout stage further optimizes the level shifter of layout.Of both the method is present
Defect：On the one hand, the layout solution space of rear layout stage is limited, and not only power consumption improves limited, and sequential can be caused to be difficult to receive
Hold back；On the other hand, if rear Butut is unsuccessful, Butut need to be re-started, causes design to be difficult to restrain.
For above-mentioned existing methods defect, on the one hand need to carry out the management work of blank area in Butut so that both
There are enough blank areas for level shifter layout, be unlikely to again to be increased dramatically layout area；On the other hand, voltage
Distribution needs and the layout of level shifter produces loop iteration, completes voltage point by the physical message feedback of level shifter
Match somebody with somebody so that temporal constraint and physical constraint are met simultaneously, and optimize power consumption.Therefore the inventive method is for towards many power supplies
The system-on-chip designs of Voltage Technique have stronger realistic meaning and practice significance.
The content of the invention
The technical problem to be solved is to provide a kind of SOC(system on a chip) Butut towards many supply voltage technologies and advises
The method of drawing, is divided into two implementation phases：Netlist modification stage and layout stage.Static timing analysis are carried out first for netlist,
The time delay allowance of each module is obtained, the simulation based on probability for carrying out module voltage based on this distributes, and assigning process is complete
Cheng Hou, travels through netlist, inserts virtual level shifter when low-voltage module drive high-voltage module, and update netlist, to
Blank area is occupied in layout stage.In layout stage, it is primarily based on the netlist after updating and produces Butut feasible solution；Then to which
Carry out the voltage distribution under temporal constraint；Obtain needing the number and link information that insert level shifter according to allocation result,
Then the layout of level shifter is carried out in the blank area of Butut, if temporal constraint is unsatisfactory for after layout, by layout
Physical message feeds back to voltage allocation step, by the lax temporal constraint of the running voltage for raising module, is further continued for into line level
The layout of shift unit, forms a circulation with this and jumps out circulation after sequential and physical constraint are met；To current cloth
Then figure feasible solution disturbs Butut and produces new feasible solution, Zhi Daoda by cost function comprehensive assessment line length, area and power consumption
To the Butut result of floor planning end condition, output level shift unit and module.
The present invention solve the technical scheme that adopted of above-mentioned technical problem for：
1st, a kind of SOC(system on a chip) layout planning method towards many supply voltage technologies, it is characterised in that including following step
Suddenly：
Step is 1.：It is retouching for the length and width information comprising circuit macroblock, time delay-power consumption information and link information to define netlist
State file；Define virtual level shifter for be present in netlist with level shifter be of the same size, time delay and power consumption
Circuit macroblock；Computer reads in and analyzes the netlist that user provides, and by static timing analysis, calculates each circuit grand
The time delay allowance of module, inserts virtual level shifter in netlist, and updates netlist；
Step is 2.：Based on the netlist after renewal, Butut feasible solution is produced；
Step is 3.：It is when voltage distributes Butut feasible solution first, on the premise of temporal constraint is met, feasible based on Butut
In solution, the coordinate information of circuit macroblock and wire length information carry out voltage distribution；When the non-distribution of voltage first of Butut feasible solution
When, based on current voltage allocation result, raised by the running voltage by some circuit macroblocks for being operated in low-voltage, again
Carry out voltage distribution；
Step is 4.：Based on the result that voltage distributes, level shifter is carried out using the blank area in Butut feasible solution
Layout；
Step is 5.：With reference to the physical message after level shifter layout, when in netlist, all of circuit macroblock is satisfied by
During temporal constraint, continue next step；When there is circuit macroblock in netlist and being unsatisfactory for temporal constraint, step is returned to 3.；
Step is 6.：Current layout solution is estimated using cost function, value at cost C is obtainedcurr, work as CcurrLess than current
Minimum cost value CbestWhen, it is C to update current minimum cost valuecurr；Work as CcurrMore than or equal to current minimum cost value CbestWhen,
Continue next step；
Step is 7.：When layout perturbation number of times p is less than the upper limit number of times p of settingmaxWhen, disturbing the new Butut of Butut generation can
Row solution, layout perturbation counting how many times add 1, and return to step 2.；When layout perturbation number of times is equal to the upper limit number of times p of settingmax
When, output result.
2nd, step 1. in the method that is inserted in netlist of virtual level shifter comprise the following steps：
Step 1.-a：The time delay allowance of definition circuit macroblock i is scki, the average delay allowance of all circuit macroblocks
For sckavg, minimal time delay allowance is sckmin, defining probability mass function is
Wherein α is the real number more than 0；For floating number rand between 0 and 1 that circuit macroblock i is randomly generated
(), when rand () is less than or equal to pmf (i), it is believed that circuit macroblock i is operated in low-voltage；When rand () is more than pmf (i)
When, it is believed that circuit macroblock i is operated in high voltage；
Step 1.-b：All circuit macroblocks are traveled through, the operating voltage state of each circuit macroblock is obtained；
Step 1.-c：Traversal netlist, when there is low voltage circuit macroblock to drive high voltage circuit macroblock in netlist, inserts
Enter virtual level shifter in the middle of the low voltage circuit macroblock and high voltage circuit macroblock, and update netlist.
3rd, the layout method of step 4. middle level shifter is comprised the following steps：
Step 4.-a：In Butut feasible solution, intrinsic blank area and void that the combination of search circuit macroblock Butut is produced
Intend the blank area that level shifter is occupied；
Step 4.-b：According to the size of level shifter, the blank area for hunting out is divided into into level shifter feasible
Layout website；
Step 4.-c：Required level shifter is assigned to one by one by the feasible station of only one according to the result of voltage distribution
Point in.
Compared with prior art, it is an advantage of the current invention that the method for proposing can carry out anticipation according to netlist, by inserting
The mode for entering virtual level shifter is managed to the blank area that layout stage is produced, in order to the cloth of level shifter
Office, suitable layout contribute to the length for reducing line, so as to reduce connecting line time delay, reach the purpose of optimization power consumption；Additionally,
The voltage distribution of layout stage and the layout of level shifter are solved by circulating, and the physical message of level shifter feeds back to electricity
Pressure distribution, is circulated and is terminated after sequential and physical constraint are met simultaneously, can be gone bail for by an inner loop and be obtained
The feasible solution of level shifter layout, improves the convergence rate of the system-on-chip designs towards many supply voltage technologies.Compare
In the SOC(system on a chip) layout planning method towards many supply voltage technologies delivered, the method for proposition can further optimize work(
Consumption.
Description of the drawings
Annexation schematic diagrams of the Fig. 1 for exemplary circuit；
Fig. 2 is the annexation schematic diagram updated after virtual level shifter is inserted；
Fig. 3 is the Butut feasible solution schematic diagram produced based on the netlist for updating；
Fig. 4 is the feasible position view of level shifter layout；
Fig. 5 is the Butut after the completion of level shifter layout；
Fig. 6 is the flow chart of the present invention.
Specific embodiment
1 exemplary circuit netlist information of table
The present invention is described in further detail below in conjunction with attached Example.
A kind of SOC(system on a chip) layout planning method towards many supply voltage technologies, it is characterised in that comprise the following steps：
Step is 1.：It is retouching for the length and width information comprising circuit macroblock, time delay-power consumption information and link information to define netlist
File is stated, table 1 show the netlist information of example, including 6 circuit macroblock b0～b5, in table, give the length and width letter of module
Breath, time delay-power consumption information visible VDDH and VDDL row represent each module time delay and power consumption under high voltage and low-voltage respectively
Size, the annexation of module are shown in Fig. 1；Virtual level shifter is defined to be present in netlist, there is phase with level shifter
The circuit macroblock of same size, time delay and power consumption；Computer reads in and analyzes the netlist that user provides, by static timing point
Analysis, calculates the time delay allowance of each circuit macroblock, inserts virtual level shifter in netlist, and updates netlist；
Step is 2.：Based on the netlist after renewal, Butut feasible solution is produced；As shown in Fig. 3 (a), move virtual level is not added
During the device of position, the blank area in Butut feasible solution is less, it is impossible to complete the layout of level shifter；As shown in Fig. 3 (b), increase
After virtual level shifter, which occupies certain area in Butut feasible solution, and height is exactly equal to actual level
Shift unit, therefore, layout is facilitated, the dotted line frame in figure represents the bounding box of link block b2 and b3, level shifter layout
Extra line expense will not be caused in frame, i.e., will not cause extra time delay, be the ideal situation of level shifter layout.
Step is 3.：It is when voltage distributes Butut feasible solution first, on the premise of temporal constraint is met, feasible based on Butut
In solution, the coordinate information of circuit macroblock and wire length information carry out voltage distribution；When the non-distribution of voltage first of Butut feasible solution
When, based on current voltage allocation result, raised by the running voltage by some circuit macroblocks for being operated in low-voltage, again
Carry out voltage distribution；The current distribution first for voltage, temporal constraint refer to the maximum of all circuit macroblocks in netlist and prolong
When be necessarily less than clock cycle TcycleIf setting TcycleValue be module 1.5 times of maximum delay when being all operated in VDDH,
Then Tcycle=86511 × 1.5=129766.5, now can be according to document W.-P.Lee, and H.-Y.Liu, Y.-W.Chang are 2007
The paper that year International Conference on Computer Aided Design (ICCAD) delivers《An ILP
algorithm for post-floorplanning voltage-island generation considering power-
network planning》The integral linear programming method of proposition is solved, and obtains voltage allocation result.VDDL is represented with low,
High represents VDDH, is as a result b0=high, b1=high, b2=high, b3=high, b4=low, b5=low, obtains work(
Consume for 84971；If being currently not the distribution first of voltage, for example, if the temporal constraint between b4 and b2 is violated, raise b4
Running voltage be high, then available bigger time delay allowance, be now not necessarily b4 and b2 insertion level shifters, power consumption
It is corresponding to raise.
Step is 4.：Based on the result that voltage distributes, level shifter is carried out using the blank area in Butut feasible solution
Layout；
Step is 5.：With reference to the physical message after level shifter layout, when in netlist, all of circuit macroblock is satisfied by
During temporal constraint, continue next step；When there is circuit macroblock in netlist and being unsatisfactory for temporal constraint, step is returned to 3.；Should
In example, temporal constraint is met.
Step is 6.：Current layout solution is estimated using cost function, value at cost C is obtainedcurr, work as CcurrLess than current
Minimum cost value CbestWhen, it is C to update current minimum cost valuecurr；Work as CcurrMore than or equal to current minimum cost value CbestWhen,
Continue next step；The setting of cost function can be the convex combination of power consumption, area and line length, for convenience of description, assume in this example that
Only with power consumption to calculate target, Cbest=90000, because of most current cost value Ccurr=84971, less than Cbest, then update current minimum
Value at cost CbestFor 84971, i.e. Cbest=84971；
Step is 7.：When layout perturbation number of times p is less than the upper limit number of times p of settingmaxWhen, disturbing the new Butut of Butut generation can
Row solution, layout perturbation counting how many times add 1, and return to step 2.；When layout perturbation number of times is equal to the upper limit number of times p of settingmax
When, output result.Assume the upper limit number of times p of layout perturbation settingmaxFor 100, current disturbance number of times p is 1, less than pmax, then cloth
Count is incremented for figure disturbance number of times p, i.e. p is 1, returns to step and 2. continues.
2nd, step 1. in the method that is inserted in netlist of virtual level shifter comprise the following steps：
Step 1.-a：The time delay allowance of definition circuit macroblock i is scki, the average delay allowance of all circuit macroblocks
For sckavg, minimal time delay allowance is sckmin, static timing analysis are carried out when it is assumed that module is all operated in VDDH, mould is obtained
Time delay allowance sck (b0) of block=0, sck (b1)=0, sck (b2)=21665, sck (b3)=0, sck (b4)=26270,
Sck (b5)=0, additionally, sckavg=7989.1, sckmin=0, defining probability mass function is
Wherein α is the real number more than 0, it is assumed that α=1；It is floating between 0 and 1 for what circuit macroblock i was randomly generated
Points rand (), when rand () is less than or equal to pmf (i), it is believed that circuit macroblock i is operated in low-voltage；When rand () it is big
When pmf (i), it is believed that circuit macroblock i is operated in high voltage；For module i that time delay allowance is 0, pmf (i)=1-1=0,
Therefore high voltage need to be operated in, this is coincide with the property of the key modules being operated in critical path.
Step 1.-b：All circuit macroblocks are traveled through, the operating voltage state of each circuit macroblock is obtained；For b2,
Floating number rand () between 0 and 1 for randomly generating, which has greater probability less than 0.933, if rand ()
=0.789, then b2 is set and is operated in low-voltage.For b4,
Floating number rand () between 0 and 1 for randomly generating, which has greater probability less than 0.963, if rand ()
=0.327, then b4 is set and is operated in low-voltage.
Step 1.-c：Traversal netlist, when there is low voltage circuit macroblock to drive high voltage circuit macroblock in netlist, inserts
Enter virtual level shifter in the middle of the low voltage circuit macroblock and high voltage circuit macroblock, and update netlist.Foundation point
With result, the netlist of renewal is shown in that Fig. 2, wherein LS represent level shifter.
3rd, the layout method of step 4. middle level shifter is comprised the following steps：
Step 4.-a：In Butut feasible solution, intrinsic blank area and void that the combination of search circuit macroblock Butut is produced
Intend the blank area that level shifter is occupied；
Step 4.-b：According to the size of level shifter, the blank area for hunting out is divided into into level shifter feasible
Layout website, as shown in figure 4, the feasible layout site locations of LS are found out in the blank area in Butut feasible solution；
Step 4.-c：Required level shifter is assigned to one by one by the feasible station of only one according to the result of voltage distribution
In point, the module annexation according to step voltage allocation result 3. and Fig. 1 needs to insert between b4 and b2, b5 and b3
Enter level shifter, as shown in Figure 5, wherein LS1 is that, between b5 and b3, LS2 is the level shift between b4 and b2 to layout result
Device.
The flow chart that Fig. 6 show the present invention.
The test result of the circuit concentrated to GSRC test circuits is shown in Table 2, and prior method refers to B.Yu, S.Dong,
The article that S.Goto etc. is delivered in ACM Great Lakes Symposium on VLSI in 2009《Voltage-island
driven floorplanning considering level-shifter positions》.Average optimization of the invention 15%
Power consumption.2 circuit test results of table
Claims (3)
1. a kind of SOC(system on a chip) layout planning method towards many supply voltage technologies, it is characterised in that comprise the following steps：
Step is 1.：Define the description text that netlist is length and width information, time delay-power consumption information and link information comprising circuit macroblock
Part；Define virtual level shifter be present in netlist with level shifter be of the same size, the electricity of time delay and power consumption
Road macroblock；Computer reads in and analyzes the netlist that user provides, and by static timing analysis, calculates each circuit macroblock
Time delay allowance, insert virtual level shifter in netlist, and update netlist；
Step is 2.：Based on the netlist after renewal, Butut feasible solution is produced；
Step is 3.：When voltage distributes Butut feasible solution first, on the premise of temporal constraint is met, based in Butut feasible solution
The coordinate information and wire length information of circuit macroblock carries out voltage distribution；When the non-voltage first of Butut feasible solution distributes,
Based on current voltage allocation result, raised by the running voltage by some circuit macroblocks for being operated in low-voltage, entered again
Row voltage distributes；
Step is 4.：Based on the result that voltage distributes, the layout of level shifter is carried out using the blank area in Butut feasible solution；
Step is 5.：With reference to the physical message after level shifter layout, when in netlist, all of circuit macroblock is satisfied by sequential
During constraint, continue next step；When there is circuit macroblock in netlist and being unsatisfactory for temporal constraint, step is returned to 3.；
Step is 6.：Current layout solution is estimated using cost function, value at cost C is obtainedcurr, work as CcurrLess than current minimum
Value at cost CbestWhen, it is C to update current minimum cost valuecurr, work as CcurrMore than or equal to current minimum cost value CbestWhen, continue
Next step；
Step is 7.：When layout perturbation number of times p is less than the upper limit number of times p of settingmaxWhen, disturb Butut and produce new Butut feasible solution,
Layout perturbation counting how many times add 1, and return to step 2.；When layout perturbation number of times is equal to the upper limit number of times p of settingmaxWhen, output
As a result.
2. as claimed in claim 1 towards the SOC(system on a chip) layout planning method of many supply voltage technologies, it is characterised in that step
It is rapid 1. in the method that is inserted in netlist of virtual level shifter comprise the following steps：
Step 1.-a：The time delay allowance of definition circuit macroblock i is scki, the average delay allowance of all circuit macroblocks is
sckavg, minimal time delay allowance is sckmin, defining probability mass function is
Wherein α is the real number more than 0；For floating number rand () between 0 and 1 that circuit macroblock i is randomly generated, when
When rand () is less than or equal to pmf (i), it is believed that circuit macroblock i is operated in low-voltage；When rand () is more than pmf (i), it is believed that
Circuit macroblock i is operated in high voltage；
Step 1.-b：All circuit macroblocks are traveled through, the operating voltage state of each circuit macroblock is obtained；
Step 1.-c：Traversal netlist, when there is low voltage circuit macroblock to drive high voltage circuit macroblock in netlist, insertion is empty
Intend level shifter in the middle of the low voltage circuit macroblock and high voltage circuit macroblock, and update netlist.
3. as claimed in claim 1 towards the SOC(system on a chip) layout planning method of many supply voltage technologies, it is characterised in that step
The layout method of rapid 4. middle level shifter is comprised the following steps：
Step 4.-a：In Butut feasible solution, intrinsic blank area and virtual electricity that the combination of search circuit macroblock Butut is produced
The blank area that translational shifting device is occupied；
Step 4.-b：According to the size of level shifter, the blank area for hunting out is divided into into the feasible layout of level shifter
Website；
Step 4.-c：Required level shifter is assigned to one by one by the feasible website of only one according to the result of voltage distribution
In.
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| Efficient nonrectangularshapedvoltageislandaware floorplanning;zhufei chu etal.;《Microelectronics Journal》;20140124;第382-393页 * |
| 一种基于电压岛的片上网络低功耗设计;何奇等;《中国集成电路》;20110405(第143期);第34-39页 * |
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