CN107944183B - Method and device for creating FPGA (field programmable Gate array) top netlist, computer equipment and medium - Google Patents
Method and device for creating FPGA (field programmable Gate array) top netlist, computer equipment and medium Download PDFInfo
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Abstract
The embodiment of the invention provides a method and a device for creating a top netlist of an FPGA (field programmable gate array), computer equipment and a medium, and belongs to the technical field of FPGA (field programmable gate array). The method for creating the top netlist of the FPGA comprises the following steps: dividing a plurality of unit electronic devices into the same module according to a predefined division standard; mapping the divided module to a grid cell; verifying the equivalence of the modules in the lattice unit and the plurality of unit electronic devices according to the actual connection and functions of the unit electronic devices; when the parity verified is fully-aligned, all the lattice cells are defined as the top-level netlist. The method and the device can ensure the consistency of the top netlist of the software layer and the electronic device on the hardware, reduce the adjustment time consumed by the inconsistency of the design of the software netlist and the hardware equipment in the later use, and improve the overall research and development efficiency.
Description
Technical Field
The invention relates to the technical field of Field Programmable Gate Arrays (FPGA), in particular to a method and a device for creating a top net list of the FPGA, computer equipment and a medium.
Background
A Field Programmable Gate Array (FPGA) is a product of further development based on Programmable devices such as PAL (Programmable Array Logic) and CPLD (Complex Programmable Logic Device). The circuit is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASICs), not only overcomes the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited.
The research and development of the FPGA are divided into chip hardware research and development and software development tools, in the chip hardware research and development process, the generation, verification and other works of a hardware full-chip function netlist are involved, the research and development of the software development tools comprise the processes of layout and wiring, bit stream file generation and the like, and the research and development of the software development tools are based on the premise that a correct software netlist is required.
In the conventional technology, the creation of the software netlist is defined after the hardware design is completed, the functional consistency of the hardware equipment and the software netlist is difficult to guarantee, when the design of the software netlist is inconsistent with the hardware equipment, the problem discovery and adjustment are time-consuming and labor-consuming, and the research and development efficiency is reduced.
Disclosure of Invention
The embodiment of the invention provides a method and a device for creating a top netlist of an FPGA (field programmable gate array), computer equipment and a medium, which can ensure the consistency of functions of hardware equipment and a software netlist so as to improve the research and development efficiency.
The technical scheme adopted by the invention for solving the technical problems is as follows:
according to one aspect of the present invention, a method for creating a top netlist of an FPGA is provided, which includes:
dividing a plurality of unit electronic devices into the same module according to a predefined division standard;
mapping the divided module to a grid cell;
verifying the equivalence of the modules in the lattice unit and the plurality of unit electronic devices according to the actual connection and functions of the unit electronic devices;
when the parity verified is fully-aligned, all the lattice cells are defined as the top-level netlist.
In one embodiment, the step of defining all of the lattice cells as the top level netlist comprises:
the table name of the top netlist and the coordinates of each lattice cell are defined.
In one embodiment, after the step of dividing the unit electronic devices into the same module, the method further comprises:
respectively defining the same divided module through expressions of different levels;
the step of mapping the divided module to a lattice cell includes:
mapping the divided modules to grid point units under corresponding levels;
verifying the equality of the same module in the lattice point unit in different levels;
when the equality of the same module in the lattice cell in different levels is completely equal, all lattice cells under each level are defined as the top netlist respectively.
In one embodiment, the step of verifying the peer of the module in the grid cell with the number of cell electronics comprises:
and respectively verifying the equality of the same module in adjacent levels according to the sequence of the levels from low to high, wherein the lowest level in different levels is the level corresponding to the unit electronic device.
In one embodiment, after the step of defining all lattice cells under each level as a top-level netlist, respectively, the method further comprises:
the identity of the same module in the top level netlist in different levels is verified.
In one embodiment, the unit electronics in the same module include a register and at least one of a nand gate or a nor gate.
According to another aspect of the present invention, an apparatus for creating a top netlist of an FPGA is provided, which includes:
the dividing module is used for dividing the unit electronic devices into the same module according to a predefined dividing standard;
a mapping module for mapping the divided modules to lattice point units;
the verification module is used for verifying the equivalence of the module in the lattice point unit and the plurality of unit electronic devices according to the actual connection and functions of the unit electronic devices;
and a netlist definition module for defining all the lattice point cells as a top netlist when the verified equivalence is full equivalence.
In one embodiment, the netlist definition module is specifically configured to:
the table name of the top netlist and the coordinates of each lattice cell are defined.
According to another aspect of the present invention, a computer device is provided, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method for creating the FPGA top netlist when executing the computer program.
According to yet another aspect of the present invention, a computer readable storage medium is provided, on which a computer program is stored, which when executed by a processor implements the steps in the method for creating a top netlist of an FPGA.
The invention divides a plurality of unit electronic devices into the same module, maps the divided module to the lattice point unit, verifies the equivalence of the module in the lattice point unit and the plurality of unit electronic devices according to the actual connection and functions of the unit electronic devices, and finally defines all the lattice point units as the top-layer netlist when the verified equivalence is completely equivalent, thereby ensuring the consistency of the top-layer netlist of a software layer and the electronic devices on hardware, reducing the adjustment time consumed by the inconsistency of the design of the software netlist and the hardware equipment in the later use, and improving the overall research and development efficiency.
Drawings
FIG. 1 is a flow diagram of a method for creating a top level netlist of an FPGA according to one embodiment of the invention;
FIG. 2 is a flow diagram of a usage scenario according to one embodiment of the present invention;
FIG. 3 is a schematic diagram of a verification relationship according to one embodiment of the invention;
FIG. 4 is a wiring schematic of the cell electronics according to one embodiment of the present invention;
FIG. 5 is a schematic diagram of a grid cell in accordance with one embodiment of the present invention;
FIG. 6 is a schematic diagram of a top level netlist according to one embodiment of the invention;
FIG. 7 is an exemplary block diagram of an apparatus for creating a top netlist of an FPGA according to an embodiment of the present invention;
fig. 8 is a schematic diagram of the internal structure of a computer device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Fig. 1 is a flowchart of a method for creating an FPGA top netlist according to an embodiment of the present invention, and the method for creating an FPGA top netlist according to an embodiment of the present invention is described in detail below with reference to fig. 1, and as shown in fig. 1, the method includes the following steps S101 to S104.
S101, dividing a plurality of unit electronic devices into the same module according to a predefined division standard.
According to one example of this embodiment, the number of cell electronics in the same module includes a register and at least one of a nand gate or a nor gate. For example. One module may include ten nand gates and one register, or may include ten nor gates and one register.
According to an example of the embodiment, the predefined division standard is designed to improve the utilization rate of each electronic device, and what unit electronic devices need to be divided into the same module may be designed according to the actual needs of the user, which is not limited herein.
And S102, mapping the divided modules to grid point units.
S103, verifying the equivalence of the modules in the lattice unit and the unit electronic devices according to the actual connection and functions of the unit electronic devices.
And S104, when the verified equivalence is completely equivalent, defining all the lattice point units as top-level netlists.
In one embodiment, the step of defining all the lattice cells as the top netlist in step S104 includes:
the table name of the top netlist and the coordinates of each lattice cell are defined.
In one embodiment, after the step of dividing the unit electronic devices into the same module, the method further comprises:
respectively defining the same divided module through expressions of different levels;
the step of mapping the divided module to a lattice cell includes:
mapping the divided modules to grid point units under corresponding levels;
verifying the equality of the same module in the lattice point unit in different levels;
when the equality of the same module in the lattice cell in different levels is completely equal, all lattice cells under each level are defined as the top netlist respectively.
In one embodiment, the step of verifying the identity between the module in the grid cell and the unit electronic devices in step S103 includes:
and respectively verifying the equality of the same module in adjacent levels according to the sequence of the levels from low to high, wherein the lowest level in different levels is the level corresponding to the unit electronic device.
In one embodiment, after the step of S104, the method further includes:
the identity of the same module in the top level netlist in different levels is verified.
According to an example of this embodiment, the reference numerals of the above steps S101 to S104 are not used to limit the sequence of each step in this embodiment, and the number of each step is only used to make the reference numerals that refer to the steps in the description of each step be used for convenient reference, so long as the execution sequence of each step does not affect the logic of this embodiment, that is, the steps are shown in the scope of the present application.
One technical scheme adopted for implementing the method in the embodiment is as follows:
the FPGA architecture is divided into the following devices of various levels, and the devices are built in a hierarchical mode. The categories of devices from bottom layer to top layer include: the bottommost logic unit is named prim device; a basic logic unit named Grid device; a special basic logic unit is different from a common grid device, does not contain user programmable resources, and is mainly used for storing configuration points named as CRAM devices; a layer between the basic logic unit and the top layer structure model, which is composed of a plurality of Grid devices and CRAM devices and named as Tile devices; the top layer structure model is named as Architecture device and only comprises tile devices and interconnection among the tile devices.
For the development of each level of devices, as shown in fig. 3, the device corresponding to the left side in fig. 3 includes, from top to bottom according to the abstraction level: a golden function model (GBM), a behavioral level model (BMA), a circuit transistor level implementation, and a layout physical level implementation, with the devices in the left side of fig. 3 corresponding to these four levels from top to bottom, respectively.
Due to the complexity of the structural logic netlist, the building process is very complicated and is easy to make mistakes, so that a grid system (grid system) is constructed to standardize the arrangement of each device. The grid point system is a 2-D logic grid point system which is uniformly divided by using the regularity of the architecture at the device level, and various devices are distributed and placed on unique logic grid points.
And the complete device arrangement and the connection among the devices form the whole content of the logic netlist.
After the unit modeling is realized by verilog language and the modeling of the top structure level is realized by custom language, hardware developers can complete the development of the hardware logic netlist. After the hardware netlist is formed, non-user-programmable resources are planed by means of a corresponding compiling tool, the user-programmable resources are reserved, and the hardware netlist is analyzed into a software netlist.
Fig. 2 is a flowchart of a usage scenario according to an embodiment of the present invention, and fig. 2 shows a development flow of an FPGA hardware netlist, which includes the following steps 1 to 7:
1. formulating a design specification: and a system architecture engineer formulates a model design specification which is in accordance with the internal use of hardware in the project according to the module design specification and a software model design specification provided by the FPGA software design flow.
2. Designing a module: according to the module design specification and a model design specification file determined by the common discussion of software and hardware, a system architecture engineer and a module design engineer carry out module design together, and the module design specifically comprises the model design of each abstract level of each level of device.
3. Module verification: and the verification engineer performs functional verification on the model file according to the description of the module design specification, performs communication feedback on the model file and a module designer at a place where the design specification is inconsistent with the model file, sends out a bug in the bug system, and performs necessary modification and adjustment on the model designer until all verifications are passed, thereby finally forming a model verification summary file.
4. Designing a top layer: and (3) placing tile devices on the defined lattice point system by a system architecture engineer according to the full-chip design specification by using a custom language, and performing interconnection design to form a final full-chip top netlist.
5. Verifying and designing: and the verification engineer makes a verification plan according to the circuit module specification, plans a verification case and passes the in-project review.
6. And (4) top layer verification: and the verification engineer performs functional verification on the verilog top-level netlist according to the top-level design specification.
7. Data transmission and inspection: and the research and development engineer transmits the module model file passing the verification and the top-level model design file to a software research and development system after basic grammar check.
Fig. 3 is a schematic diagram of verifying relationships according to an embodiment of the present invention, and fig. 3 shows device development modes related to various functional levels and verification of various abstract level models.
Device nomenclature is abbreviated as follows:
1. the grid device is abbreviated as GD and corresponds to the hardware device in fig. 3;
2. the abbreviation TD for tile device corresponds to the grid cell in fig. 3;
3. the acronym AD for architecture device corresponds to the top-level netlist in fig. 3, also known as the top-level structure model.
And (4) verification description:
1. the one-way arrow represents the verification of the subset. The arrow ends are subsets.
2. The double-headed arrows indicate equality verification, and the functionality or netlist structure of both ends must be identical.
Specific validation is indicated by 'V'. For example, verification between GD, denoted GDV _. By analogy, TDV, ADV.
GDV-12 verifies the correctness of GD-2 by dynamic simulation, GDV-23 verifies that GD-2 and GD-3 are equivalent by formal verification, and GDV-34 verifies that GD-3 and GD-4 are equivalent by layout vs circuit (LVS: layout vs. schema).
TDV _21 is a one-way authentication. The connection relation of TD _1 is ensured to still exist in TD _2, TDV _23 is bidirectional verification, the functional consistency of the TD _1 and TDV _23 is ensured by a formal verification mode, and TDV _34 is a bidirectional LVS.
ADV _21 is a one-way authentication. The connection relation of the AD _1 is ensured to still exist in the AD _2, the ADV _23 is bidirectional verification, the functional consistency of the AD _2 and the ADV _34 is ensured by a formal verification mode, and the ADV _34 is a bidirectional LVS.
Fig. 4 is a wiring diagram of unit electronic devices according to an embodiment of the present invention, showing an actual connection relationship of the respective unit electronic devices.
Fig. 5 is a schematic diagram of a lattice unit according to an embodiment of the present invention, where the lattice unit is composed of a number of general basic logic units (grid devices), special basic logic units (CRAM devices), and interconnections between the general basic logic units and the special basic logic units. The CRAM device is mainly used for storing configuration point resources, and other basic logic units (grid devices) are programmable resources available for users. The lattice point unit (Tile device) is a layer made by hardware modularization and is a virtual layer, which is convenient for generating a bit stream file.
FIG. 6 is a diagram of a top-level netlist according to an embodiment of the invention, as shown in FIG. 6, in the hardware netlist, the hardware netlist is composed of a number of lattice point units and their interconnections, and at the level of the top-level structure model, the lattice point units exhibit a 2D arrangement under the specification of a lattice point system. When the compiling tool analyzes the hardware netlist, the grid point unit level can be automatically removed, the programmable information is extracted, and the software netlist is generated. Therefore, the top-level structure model of the software netlist is composed of a plurality of user-programmable grid devices and interconnections among the grid devices.
Both the lattice cell and the top netlist have their own lattice system. The lattice point unit and the top-level structure model (architecture device) are in different levels, although they are defined independently, the two lattice point systems must be ensured to be completely overlapped, so that the lattice point unit and the basic logic unit (grid device) under the top-level structure model can be ensured to be completely overlapped without deviation, unnecessary operation is reduced, and human comprehension obstacles are reduced.
Through the above description of the embodiments, those skilled in the art can clearly understand that the method of the embodiments can be implemented by software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (which may be a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.
The top netlist of the software layer in the embodiment is automatically analyzed based on hardware equipment, and by means of a special device modeling method, the top structure level connection and a corresponding compiling tool are realized through a user-defined language, so that the automation is greatly realized, and manual factors are eliminated, and the consistency of the software netlist and the hardware netlist can be ensured. Meanwhile, software and hardware can be simultaneously researched and developed, all versions can be uniformly managed, the communication cost on the versions is reduced, and the research and development efficiency is accelerated.
Fig. 7 is an exemplary block diagram of an apparatus for creating a top netlist of an FPGA according to an embodiment of the present invention, and the apparatus for creating a top netlist of an FPGA according to an embodiment of the present invention is described in detail below with reference to fig. 7, where the apparatus 100 for creating a top netlist of an FPGA includes: partitioning module 11, mapping module 12, verification module 13, and netlist definition module 14.
The dividing module 11 is configured to divide the plurality of unit electronic devices into the same module according to a predefined division standard.
According to one example of this embodiment, the number of cell electronics in the same module includes a register and at least one of a nand gate or a nor gate. For example. One module may include ten nand gates and one register, or may include ten nor gates and one register.
According to an example of the embodiment, the predefined division standard is designed to improve the utilization rate of each electronic device, and what unit electronic devices need to be divided into the same module may be designed according to the actual needs of the user, which is not limited herein.
A mapping module 12 for mapping the divided module to a grid cell.
And the verification module 13 is configured to verify the equivalence between the module in the lattice unit and the plurality of unit electronic devices according to the actual connection and function of the unit electronic devices.
In one embodiment, the netlist definition module 14 is specifically configured to:
the table name of the top netlist and the coordinates of each lattice cell are defined.
In one embodiment thereof, the apparatus further comprises:
the hierarchy definition module is used for respectively defining the same divided module through expressions of different hierarchies;
the mapping module 12 is further configured to map the divided modules to grid point units at corresponding levels;
the verification module 13 is also used for verifying the peer-to-peer performance of the same module in the grid cell in different levels;
In one embodiment, the verification module 13 is specifically configured to verify the peer-to-peer performance of the same module in adjacent levels respectively according to a sequence from a low level to a high level, where a lowest level in the different levels is a level corresponding to the unit electronic device.
In one embodiment, the verification module 13 is also used to verify the identity of the same module in the top netlist in different levels.
In one embodiment, the unit electronic devices in the same module include a register and at least one of a nand gate and a nor gate.
It should be noted that the device embodiment and the method embodiment belong to the same concept, and specific implementation processes thereof are described in the method embodiment in detail, and technical features in the method embodiment are correspondingly applicable in the device embodiment, which is not described herein again.
According to the embodiment, the computer device comprises a memory, a processor and a computer program which is stored on the memory and can run on the processor, and the processor executes the program to realize the method for creating the FPGA top-level netlist.
Fig. 8 is a schematic diagram of an internal structure of a computer device in one embodiment, and the computer device may be a server. Referring to fig. 8, the computer apparatus includes a processor, a memory, an input device, a display screen, and a network interface connected through a system bus. The memory includes a nonvolatile storage medium and an internal memory, where the nonvolatile storage medium of the computer device may store an operating system and computer readable instructions, and when the computer readable instructions are executed, the computer readable instructions may cause the processor to execute a method for creating a top netlist of an FPGA according to embodiments of the present application, and a specific implementation process of the method may refer to specific contents of embodiments in fig. 1 to 6, which is not described herein again. The processor of the computer device is used for providing calculation and control capability and supporting the operation of the whole computer device. The internal memory may have stored therein computer readable instructions that, when executed by the processor, cause the processor to perform a method for creating a top netlist of an FPGA. The input device of the computer equipment is used for inputting various parameters, the display screen of the computer equipment is used for displaying, and the network interface of the computer equipment is used for network communication. Those skilled in the art will appreciate that the architecture shown in fig. 8 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
According to an embodiment of the present invention, a computer-readable storage medium is provided, on which a computer program is stored, and the computer program, when executed by a processor, implements the steps in the method for creating the FPGA top netlist.
According to an example of this embodiment, all or part of the processes in the methods of the embodiments described above may be implemented by a computer program to instruct related hardware, where the program may be stored in a computer-readable storage medium, and in this embodiment of the present invention, the program may be stored in the storage medium of a computer system and executed by at least one processor in the computer system, so as to implement the processes including the embodiments of the methods described above. The storage medium includes, but is not limited to, a magnetic disk, a flash disk, an optical disk, a Read-Only Memory (ROM), and the like.
According to the method, the device, the computer equipment and the medium for creating the FPGA top netlist, a plurality of unit electronic devices are divided into the same module, the divided module is mapped to the lattice point unit, the equivalence of the module in the lattice point unit and the plurality of unit electronic devices is verified according to the actual connection and functions of the unit electronic devices, when the equivalence is verified to be completely equivalent, all the lattice point units are finally defined as the top netlist, the consistency of the top netlist on a software level and the electronic devices on hardware can be ensured, the adjustment time consumed due to the fact that the design of the software netlist and the hardware equipment are inconsistent in later use is reduced, and the overall research and development efficiency is improved.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (7)
1. A method for creating a top netlist of an FPGA, the method comprising:
dividing a plurality of unit electronic devices into the same module according to a predefined division standard;
respectively defining the same divided module through expressions of different levels;
mapping the divided modules to grid point units under corresponding levels;
verifying the peering of the same module in the grid cell in different levels;
when the equality of the same module in the lattice point units in different levels is completely equal, respectively defining all lattice point units under each level as a top-level netlist;
verifying the equivalence of the modules in the lattice unit and the plurality of unit electronic devices according to the actual connection and functions of the unit electronic devices;
when the verified equivalence is completely equal, defining all the lattice point units as a top-level netlist;
verifying the peering of the same module in the top netlist in different levels;
wherein the step of verifying the peering of the modules in the grid cell with the number of cell electronics comprises:
and respectively verifying the equality of the same module in adjacent levels according to the sequence of the levels from low to high, wherein the lowest level in different levels is the level corresponding to the unit electronic device.
2. The method of claim 1, wherein the step of defining all of the lattice cells as a top level netlist comprises:
and defining the table name of the top netlist and the coordinates of each lattice point unit.
3. The method of any of claims 1 or 2, wherein the number of cell electronics in the same module comprises a register and further comprises at least one of a nand gate or a nor gate.
4. An apparatus for creating a top netlist of an FPGA, the apparatus comprising:
the dividing module is used for dividing the unit electronic devices into the same module according to a predefined dividing standard; respectively defining the same divided module through expressions of different levels;
a mapping module for mapping the divided modules to grid point units under corresponding levels;
verifying the peering of the same module in the grid cell in different levels;
when the equality of the same module in the lattice point units in different levels is completely equal, respectively defining all lattice point units under each level as a top-level netlist;
the verification module is used for verifying the equivalence of the modules in the lattice point unit and the plurality of unit electronic devices according to the actual connection and functions of the unit electronic devices;
a netlist definition module, configured to define all the lattice point units as a top netlist when the verified equivalence is fully-equal; verifying the peering of the same module in the top netlist in different levels;
wherein the step of verifying the peering of the modules in the grid cell with the number of cell electronics comprises:
and respectively verifying the equality of the same module in adjacent levels according to the sequence of the levels from low to high, wherein the lowest level in different levels is the level corresponding to the unit electronic device.
5. The apparatus of claim 4, wherein the netlist definition module is specifically configured to:
and defining the table name of the top netlist and the coordinates of each lattice point unit.
6. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the method of creating a top netlist of an FPGA as claimed in any one of claims 1 to 3 when executing the program.
7. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 3.
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| CN112257357B (en) * | 2020-09-14 | 2022-09-13 | 深圳市紫光同创电子有限公司 | Method and device for constructing top-level circuit of FPGA (field programmable Gate array) chip and storage medium |
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