CN107944183A - Creation method, device, computer equipment and the medium of FPGA top layer netlists - Google Patents
Creation method, device, computer equipment and the medium of FPGA top layer netlists Download PDFInfo
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- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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Abstract
The embodiment of the present invention provides a kind of creation method, device, computer equipment and the medium of FPGA top layers netlist, belongs to on-site programmable gate array FPGA technical field.The creation method of the FPGA top layer netlists, this method include：According to the pre-defined criteria for classifying, several unit electronic devices are divided into same module；The module of division is mapped to lattice point unit；According to the actual line and function of the unit electronic device, the equity of the module and several unit electronic devices in the lattice point unit is verified；When the equity of verification is equity completely, all lattice point units are defined as top layer netlist.The application can ensure the top layer netlist of software view and the uniformity of the electronic device on hardware, reduce the later stage when using due to software netlist design Yu the inconsistent consumption of hardware device adjustment time, improve overall efficiency of research and development.
Description
Technical field
The present invention relates to on-site programmable gate array FPGA technical field, more particularly to a kind of wound of FPGA top layers netlist
Construction method, device, computer equipment and medium.
Background technology
FPGA (Field-Programmable Gate Array) field programmable gate array is in PAL
(Programmable Array Logic, programmable logic array), CPLD (Complex Programmable Logic
Device, Complex Programmable Logic Devices) etc. the product that further develops on the basis of programming device.It is as special collection
Occur into a kind of semi-custom circuit in circuit ASIC fields, not only solved the deficiency of custom circuit, but also overcome original
The shortcomings that programming device gate circuit number is limited.
The research and development of FPGA are divided into chip hardware research and development and the research and development of Software Development Tools, in chip hardware R＆D process, relate to
And the work such as generation and verification to the full chip functions netlist of hardware, and the research and development of Software Development Tools include placement-and-routing with
And process, the research and development premise of Software Development Tools such as bit stream file generation are the need for correct software netlist.
Since in the conventional technology, the establishment of software netlist is completed to define afterwards in hardware design, is set for hardware
Standby and software netlist function uniformity is difficult to ensure that, when the design of software netlist is inconsistent with hardware device, the discovery of problem
And adjustment is all more time-consuming, reduces efficiency of research and development.
The content of the invention
The embodiment of the present invention provides a kind of creation method, device, computer equipment and the medium of FPGA top layers netlist, can be with
Ensure the uniformity of hardware device and software netlist function, so as to improve efficiency of research and development.
Technical solution is as follows used by the present invention solves above-mentioned technical problem：
A kind of creation method of the FPGA top layers netlist provided according to an aspect of the present invention, this method include：
According to the pre-defined criteria for classifying, several unit electronic devices are divided into same module；
The module of division is mapped to lattice point unit；
According to the actual line and function of the unit electronic device, the module and several lists in the lattice point unit are verified
The equity of first electronic device；
When the equity of verification is equity completely, all lattice point units are defined as top layer netlist.
In one of which embodiment, the step of all lattice point units are defined as top layer netlist by this, includes：
Define the table name of the top layer netlist and the coordinate of each lattice point unit.
In one of which embodiment, several unit electronic devices are divided into same module by this step of it
Afterwards, this method further includes：
The same module of division is defined respectively by the statement of different levels；
The step of module of division is mapped to lattice point unit by this includes：
The lattice point unit module of division being mapped under corresponding level；
Verify the equity of the same module in different levels in the lattice point unit；
When the equity of the same module in the lattice point unit in different levels is equity completely, respectively by each level
Under the possessive case dot element be defined as top layer netlist.
In one of which embodiment, module and several unit electronic devices in the verification lattice point unit
The step of equity, includes：
According to the order of level from low to high, the equity of same module in adjacent level, the different levels are separately verified
In lowest hierarchical level be the level corresponding to the unit electronic device.
In one of which embodiment, the possessive case dot element under each level is defined as top net respectively at this
After the step of table, this method further includes：
Verify the equity of the same module in the top layer netlist in different levels.
In one of which embodiment, the same mould several unit electronic devices in the block include register, also wrap
Include at least one of NAND gate or nor gate.
A kind of creating device of the FPGA top layers netlist provided according to another aspect of the present invention, the device include：
Division module, for according to the pre-defined criteria for classifying, several unit electronic devices to be divided into same mould
Block；
Mapping block, for the module of division to be mapped to lattice point unit；
Authentication module, for the actual line and function according to the unit electronic device, verifies the mould in the lattice point unit
The equity of block and several unit electronic devices；
Netlist definition module, for when the equity of verification is equity completely, all lattice point units to be defined as
Top layer netlist.
In one of which embodiment, which is specifically used for：
Define the table name of the top layer netlist and the coordinate of each lattice point unit.
A kind of computer equipment provided according to a further aspect of the invention, including memory, processor and be stored in
On memory and the computer program that can run on a processor, the processor realize above-mentioned FPGA top nets when performing the program
The creation method of table.
A kind of computer-readable recording medium provided according to a further aspect of the invention, is stored thereon with computer journey
Sequence, the program realize the step in the creation method of above-mentioned FPGA top layers netlist when being executed by processor.
The present invention by several unit electronic devices by being divided into same module, then the module of division is mapped to lattice
Dot element, then according to the actual line and function of the unit electronic device, verifies that the module in the lattice point unit is some with this
The equity of a unit electronic device, when the equity of verification is equity completely, finally defines all lattice point units
For top layer netlist, it is ensured that the top layer netlist of software view and the uniformity of the electronic device on hardware, reducing the later stage makes
Used time due to the adjustment time of design Yu the inconsistent consumption of hardware device of software netlist, improves overall efficiency of research and development.
Brief description of the drawings
Fig. 1 is the flow chart according to the creation method of the FPGA top layer netlists of one embodiment of the present of invention；
Fig. 2 is the usage scenario flow chart according to one embodiment of the present of invention；
Fig. 3 is the verification relation schematic diagram according to one embodiment of the present of invention；
Fig. 4 is the schematic wiring diagram according to the unit electronic device of one embodiment of the present of invention；
Fig. 5 is the schematic diagram according to the lattice point unit of one embodiment of the present of invention；
Fig. 6 is the schematic diagram according to the top layer netlist of one embodiment of the present of invention；
Fig. 7 is the exemplary block diagram according to the creating device of the FPGA top layer netlists of one embodiment of the present of invention；
Fig. 8 is the internal structure schematic diagram according to the computer equipment of one embodiment of the present of invention.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to the accompanying drawings and embodiments, it is right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Fig. 1 be according to the flow chart of the creation method of the FPGA top layer netlists of one embodiment of the present of invention, with reference to
Fig. 1 is described in detail a kind of creation method of FPGA top layers netlist according to an embodiment of the invention, as shown in Figure 1, should
Method comprises the following steps S101 to S104.
Several unit electronic devices are divided into same module by the pre-defined criteria for classifying of S101, basis.
According to the present embodiment example, the same mould several unit electronic devices in the block include register, also
Including at least one of NAND gate or nor gate.Such as.One module can include ten NAND gates and a register,
It can include ten nor gates and a register.
According to the present embodiment example, the standard of pre-defined division is to improve the utilization rate of each electronic device
As a purpose, specifically need which unit electronic device being divided into same module and can be set according to the actual demand of user
Meter, is not limited herein.
S102, by the module of division be mapped to lattice point unit.
S103, actual line and function according to the unit electronic device, if verify module in the lattice point unit with should
The equity of dry unit electronic device.
S104, when verification the equity for completely equity when, all lattice point units are defined as top layer netlist.
In one of which embodiment, all lattice point units are defined as top layer netlist by this in above-mentioned steps S104
Step includes：
Define the table name of the top layer netlist and the coordinate of each lattice point unit.
In one of which embodiment, several unit electronic devices are divided into same module by this step of it
Afterwards, this method further includes：
The same module of division is defined respectively by the statement of different levels；
The step of module of division is mapped to lattice point unit by this includes：
The lattice point unit module of division being mapped under corresponding level；
Verify the equity of the same module in different levels in the lattice point unit；
When the equity of the same module in the lattice point unit in different levels is equity completely, respectively by each level
Under the possessive case dot element be defined as top layer netlist.
In one of which embodiment, module and several lists in the lattice point unit are verified in above-mentioned steps S103
The step of equity of first electronic device, includes：
According to the order of level from low to high, the equity of same module in adjacent level, the different levels are separately verified
In lowest hierarchical level be the level corresponding to the unit electronic device.
In one of which embodiment, after the step of above-mentioned steps S104, this method further includes：
Verify the equity of the same module in the top layer netlist in different levels.
According to the present embodiment example, the label of above-mentioned steps S101~S104 is not used to limit in the present embodiment
The sequencing of each step, the numbering of each step are intended merely to allow general reference step when describing each step
Label easily referred to, represented as long as the order that each step performs does not influence the logic of the present embodiment in the application
Within the scope of being claimed.
To realize that a kind of technical solution that the method in the present embodiment uses is as follows：
The framework of FPGA is divided into following various levels of device, is set up and formed in a manner of stratification.From bottom to
The species of top layer device includes：Bottom logic unit, is named as prim device；Basic logic unit, is named as Grid
device；A kind of special basic logic unit, different with common grid device, it does not include user-programmable resource,
It is mainly used to store collocation point, is named as CRAM device；One between basic logic unit and top level structure model
Level, is made of several Grid device and CRAM device, is named as Tile device；Top level structure model, life
Entitled Architecture device, only comprising tile device and its between interconnection.
Research and development for each level device, as shown in figure 3, in corresponding diagram 3 left side equipment, according to abstraction hierarchy from top to
Bottom includes：Gold functional mode (golden model：GBM), behavioral scaling model (behavioral model：BMA), circuit
Transistor level is realized, and domain physical level is realized, on the left of Fig. 3 in equipment it is corresponding respectively with this four levels under upper.
Due to the complexity of framework logic netlist, build process is not only very cumbersome, and error-prone, then builds
Lattice system (grid system) carrys out the arrangement of each device of specification.So-called lattice system is exactly the level in device, utilizes frame
The regularity of structure, the uniform logic lattice system for dividing 2-D, various devices are all allocated and are placed on unique logic lattice point
On.
Regular device arrangement adds the connection between device, that is, constitutes logic netlist full content.
Modelon Modeling can be realized by verilog language, and the modeling of top level structure level is realized by self-defined language,
With after both, hardware research staff can complete the research and development of hardware logic netlist.Form hardware netlist and then borrow
Corresponding compilation tool is helped, excludes non-user programmable resource, retains user-programmable resource, hardware netlist is parsed into software
Netlist.
Fig. 2 is the usage scenario flow chart according to one embodiment of the present of invention, and Fig. 2 shows that FPGA hardware netlist is researched and developed
Flow, its processes of research ＆ development following steps 1 to step 7：
1. formulate design specification：System architecture engineer carries according to module design specification, and FPGA Software for Design flows
The software model design specification of confession, formulates the model design specification for meeting and being used in this project inside hardware.
2. module designs：According to module design specification, and the model design specification file that software and hardware is decided through discussion jointly,
System architecture engineer and module design engineer carry out module design jointly, have specifically included each each abstraction hierarchy of level device
Modelling.
3. module verification：Verify description of the engineer according to module design specification, functional verification is carried out to model file, it is right
Model file and the inconsistent place of design specification, and module designer carry out communication feedback, and send bug in bug systems,
Modelling personnel carry out necessary modification adjustment, are verified until all, ultimately form model verification and summarize file.
4. Top-layer Design Method：System architecture engineer is according to full chip design specification, using self-defined language, by tile
Device is placed on the lattice system defined, and carries out interconnection design, forms final full chip top-layer netlist.
5. verification design：Engineer is verified according to circuit module specification institution demonstration plan, Planning Validation use-case, and is passed through
Evaluation in project.
6. top layer is verified：Verify that according to Top-layer Design Method specification, functional verification is carried out to verilog top layers netlist by engineer.
7. data transfer and inspection：Engineer is researched and developed by by the modular model file of verification and top layer modelling text
Part, after basic syntax check, is transferred to software development systems.
Fig. 3 is the verification relation schematic diagram according to one embodiment of the present of invention, and Fig. 3, which is shown, is related to each function
The device R＆D Approach of level, and the verification of each abstraction hierarchy model.
Device name abbreviation is as follows：
1st, grid device are abbreviated as GD, hardware device in corresponding diagram 3；
2nd, tile device are abbreviated as TD, lattice point unit in corresponding diagram 3；
3rd, architecture device are abbreviated as AD, the top layer netlist in corresponding diagram 3, also referred to as top level structure model.
Verify explanation：
1. unidirectional arrow represents the verification of subset.Arrow end is subset.
2. four-headed arrow represents identity property verification, the function or netlist structure at both ends must be equal.
Specific verification is indicated with ' V'.Such as the verification between GD, it is denoted as GDV_.And so on, TDV_,
ADV_。
3.GDV_12 verifies the correctness of GD_2 with dynamic simulation, and GDV_23 verifies GD_2 and GD_3 with formal verification
It is of equal value, GDV_34 is with domain vs circuits (LVS:Layout vs schematic) verify that GD_3 and GD_4 are of equal value.
4.TDV_21 is unidirectional verification.Ensure that the connection relation of TD_1 still exists in TD_2, TDV_23 is two-way
Verification, ensures the two function uniformity, TDV_34 is two-way LVS with formal verification mode.
5.ADV_21 is unidirectional verification.Ensure that the connection relation of AD_1 still exists in AD_2, ADV_23 is two-way
Verification, ensures the two function uniformity, ADV_34 is two-way LVS with formal verification mode.
Fig. 4 is according to the schematic wiring diagram of the unit electronic device of one embodiment of the present of invention, shows unit
The actual connection relation of electronic device.
Fig. 5 is common by several according to the schematic diagram of the lattice point unit of one embodiment of the present of invention, the lattice point unit
Basic logic unit (grid device), special basic logic unit (CRAM device) and each between interconnection
Composition.CRAM device are mainly used to storage configuration point resource, and other basic logic units (grid device) can for user
Programmable resource.The level that lattice point unit (Tile device) is done by hardware modularity, is a virtual layer
It is secondary, easy to the generation of bit stream file.
Fig. 6 is the schematic diagram according to the top layer netlist of one embodiment of the present of invention, as shown in fig. 6, in hardware netlist,
By several lattice point units and its between interconnection form, in top level structure model hierarchy, rule of the lattice point unit in lattice system
Under model, 2D arrangements are showed.Compilation tool can remove lattice point unit level automatically when parsing hardware netlist, and extraction is programmable
Information, generates software netlist.Therefore, the top level structure model of software netlist, by the grid device of several user-programmables
Interconnection composition between and its.
Lattice point unit and top layer netlist have the lattice system of oneself.Lattice point unit and top level structure model
(architecture device) is in different levels, although they define respective independent, two lattice point systems respectively
System, which must assure that, to be completely superposed, and is so ensured that under top level structure model, lattice point unit and basic logic unit
(grid device) is completely superposed, and is not in the situation of offset, reduces unnecessary operation, reduces the obstacle artificially understood.
Through the above description of the embodiments, those skilled in the art can be understood that above-described embodiment side
Method can add the mode of required general hardware platform to realize by software, naturally it is also possible to be realized by hardware.Based on this
The understanding of sample, the part that technical scheme substantially in other words contributes the prior art can be with software products
Form embodies, which is stored in a storage medium (such as ROM/RAM, magnetic disc, CD), if including
Dry instruction is used so that a station terminal equipment (can be computer, server, or network equipment etc.) the execution present invention is each
Method described in embodiment.
The top layer netlist of software view is parsed automatically based on hardware device in the present embodiment, and by special device
Part modeling method, the connection for the top level structure level realized by customized language and corresponding compilation tool, it is greatly real
Show automation, reject artifact, therefore can ensure the uniformity of software netlist and hardware netlist.Meanwhile software and hardware also may be used
To be carried out at the same time research and development, all version updatings can uniformly be managed, reduce the communication cost on version, accelerate and grind
Send out efficiency.
Fig. 7 be according to the exemplary block diagram of the creating device of the FPGA top layer netlists of one embodiment of the present of invention,
The creating device of FPGA top layers netlist according to an embodiment of the invention is described in detail with reference to Fig. 7, such as Fig. 7 institutes
Show, the creating device 100 of the FPGA top layer netlists includes：Division module 11, mapping block 12, authentication module 13 and netlist definition
Module 14.
Division module 11, for according to the pre-defined criteria for classifying, several unit electronic devices being divided into same
Module.
According to the present embodiment example, the same mould several unit electronic devices in the block include register, also
Including at least one of NAND gate or nor gate.Such as.One module can include ten NAND gates and a register,
It can include ten nor gates and a register.
According to the present embodiment example, the standard of pre-defined division is to improve the utilization rate of each electronic device
As a purpose, specifically need which unit electronic device being divided into same module and can be set according to the actual demand of user
Meter, is not limited herein.
Mapping block 12, for the module of division to be mapped to lattice point unit.
Authentication module 13, for the actual line and function according to the unit electronic device, is verified in the lattice point unit
Module and the equity of several unit electronic devices.
Netlist definition module 14, for when the equity of verification is equity completely, all lattice point units to be defined
For top layer netlist.
In one of which embodiment, which is specifically used for：
Define the table name of the top layer netlist and the coordinate of each lattice point unit.
In one of which embodiment, which further includes：
Level definition module, for the same module of division to be defined respectively by the statement of different levels；
The mapping block 12 is additionally operable to the lattice point unit being mapped to the module of division under corresponding level；
The authentication module 13 is additionally operable to the equity of the same module in the lattice point unit in verification different levels；
The equity that netlist definition module 14 is additionally operable to work as the same module in different levels in the lattice point unit is complete
When reciprocity, the possessive case dot element under each level is defined as top layer netlist respectively.
In one of which embodiment, which is specifically used for the order according to level from low to high, respectively
Verify the equity of same module in adjacent level, the lowest hierarchical level in the different levels is corresponding to the unit electronic device
Level.
In one of which embodiment, which is additionally operable in the top layer netlist in verification different levels
The equity of same module.
In one of which embodiment, above-mentioned same mould several unit electronic devices in the block include register, also
Including at least one of NAND gate or nor gate.
It should be noted that above device embodiment belongs to same design with embodiment of the method, it is detailed that it implements process
See embodiment of the method, and the technical characteristic in embodiment of the method is corresponding applicable in device embodiment, which is not described herein again.
According to a kind of computer equipment provided in this embodiment, including memory, processor and storage are on a memory simultaneously
The computer program that can be run on a processor, the processor realize the establishment side of above-mentioned FPGA top layers netlist when performing the program
Method.
Fig. 8 is the internal structure schematic diagram of one embodiment Computer equipment, which can be server.
With reference to Fig. 8, which includes processor, memory, input unit, display screen and the network connected by system bus
Interface.Wherein, which includes non-volatile memory medium and built-in storage, and the non-volatile memories of the computer equipment are situated between
Matter can storage program area and computer-readable instruction, which is performed, and may be such that processor performs sheet
Apply for a kind of creation method of FPGA top layers netlist of each embodiment, the specific implementation process of this method refers to each realities of Fig. 1 to 6
The particular content of example is applied, details are not described herein.The processor of the computer equipment is used to provide calculating and control ability, and support is whole
The operation of a computer equipment.Computer-readable instruction can be stored in the built-in storage, which is processed
When device performs, it may be such that processor performs a kind of creation method of FPGA top layers netlist.The input unit of computer equipment is used for
The input of parameters, for being shown, the network interface of computer equipment is used to carry out net the display screen of computer equipment
Network communicates.It will be understood by those skilled in the art that the structure shown in Fig. 8, only part knot relevant with application scheme
The block diagram of structure, does not form the restriction for the computer equipment being applied thereon to application scheme, specific computer equipment
It can include, than more or fewer components shown in figure, either combining some components or arranging with different components.
A kind of computer-readable recording medium provided according to embodiments of the present invention, is stored thereon with computer program, should
The step in the creation method of above-mentioned FPGA top layers netlist is realized when program is executed by processor.
According to the present embodiment example, all or part of flow in above-described embodiment method, can pass through calculating
Machine program instructs relevant hardware to complete, and described program can be stored in a computer read/write memory medium, such as this hair
In bright embodiment, which can be stored in the storage medium of computer system, and by least one in the computer system
Processor performs, to realize the flow for including the embodiment such as above-mentioned each method.The storage medium includes but not limited to magnetic disc, excellent
Disk, CD, read-only memory (Read-Only Memory, ROM) etc..
Creation method, device, computer equipment and the medium of a kind of FPGA top layers netlist provided in this embodiment, pass through by
Several unit electronic devices are divided into same module, then the module of division is mapped to lattice point unit, then according to the list
The actual line and function of first electronic device, verify the equity of the module and several unit electronic devices in the lattice point unit
Property, when the equity of verification is equity completely, all lattice point units are finally defined as top layer netlist, it is ensured that soft
The top layer netlist of part aspect and the uniformity of the electronic device on hardware, due to the design of software netlist when reducing later stage use
With the adjustment time of the inconsistent consumption of hardware device, overall efficiency of research and development is improved.
Each technical characteristic of embodiment described above can be combined arbitrarily, to make description succinct, not to above-mentioned reality
Apply all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, the scope that this specification is recorded all is considered to be.
Embodiment described above only expresses the several embodiments of the present invention, its description is more specific and detailed, but simultaneously
Cannot therefore it be construed as limiting the scope of the patent.It should be pointed out that come for those of ordinary skill in the art
Say, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the protection of the present invention
Scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (10)
- A kind of 1. creation method of FPGA top layers netlist, it is characterised in that the described method includes：According to the pre-defined criteria for classifying, several unit electronic devices are divided into same module；The module of division is mapped to lattice point unit；According to the actual line and function of the unit electronic device, verify module in the lattice point unit with it is described several The equity of unit electronic device；When the equity of verification is equity completely, all lattice point units are defined as top layer netlist.
- 2. according to the method described in claim 1, it is characterized in that, described be defined as top layer netlist by all lattice point units The step of include：Define the table name of the top layer netlist and the coordinate of each lattice point unit.
- 3. according to the method described in claim 1, it is characterized in that, it is described several unit electronic devices are divided into it is same After the step of module, the method further includes：The same module of division is defined respectively by the statement of different levels；The described the step of module of division is mapped to lattice point unit, includes：The lattice point unit module of division being mapped under corresponding level；Verify the equity of the same module described in different levels in lattice point unit；When the equity of the same module in lattice point unit described in different levels is equity completely, respectively by under each level The possessive case dot element be defined as top layer netlist.
- If 4. according to the method described in claim 3, it is characterized in that, module in the verification lattice point unit with it is described The step of equity of dry a unit electronic device, includes：According to the order of level from low to high, the equity of same module in adjacent level is separately verified, in the different levels Lowest hierarchical level be the level corresponding to the unit electronic device.
- 5. according to the method described in claim 3, it is characterized in that, described respectively by all lattice points under each level Unit was defined as after the step of top layer netlist, and the method further includes：Verify the equity of the same module in the top layer netlist in different levels.
- 6. method according to any one of claims 1 to 5, it is characterised in that described same mould several units in the block Electronic device includes register, further includes at least one of NAND gate or nor gate.
- 7. a kind of creating device of FPGA top layers netlist, it is characterised in that described device includes：Division module, for according to the pre-defined criteria for classifying, several unit electronic devices to be divided into same module；Mapping block, for the module of division to be mapped to lattice point unit；Authentication module, for the actual line and function according to the unit electronic device, verifies the mould in the lattice point unit The equity of block and several unit electronic devices；Netlist definition module, for when the equity of verification is equity completely, all lattice point units to be defined as Top layer netlist.
- 8. device according to claim 7, it is characterised in that the netlist definition module is specifically used for：Define the table name of the top layer netlist and the coordinate of each lattice point unit.
- 9. a kind of computer equipment, including memory, processor and storage are on a memory and the meter that can run on a processor Calculation machine program, it is characterised in that the processor is realized such as the FPGA of any one of claim 1 to 6 when performing described program The creation method of top layer netlist.
- 10. a kind of computer-readable recording medium, is stored thereon with computer program, it is characterised in that described program is processed Realized when device performs such as the step in any one of claim 1 to 6 the method.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN112257357A (en) * | 2020-09-14 | 2021-01-22 | 深圳市紫光同创电子有限公司 | Method and device for constructing top circuit of FPGA chip and storage medium |
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