CN104573148A

CN104573148A - Method for lowering electricity leakage power consumption of time sequence device in circuit

Info

Publication number: CN104573148A
Application number: CN201310485457.1A
Authority: CN
Inventors: 周舒哲; 董森华; 陈彬; 燕昭然
Original assignee: Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Beijing Empyrean Technology Co Ltd
Priority date: 2013-10-17
Filing date: 2013-10-17
Publication date: 2015-04-29
Anticipated expiration: 2033-10-17
Also published as: CN104573148B

Abstract

Disclosed is a method for lowering electricity leakage power consumption of a time sequence device in a circuit. As size of an integrated circuit is constantly reduced, proportion that the electricity leakage power consumption accounts in total power consumption is constantly increased, a clock system is complex increasingly, proportion that the time sequence device accounts is constantly increased, effective lowering of the electricity leakage power consumption of the time sequence device cannot be ignored already. Technology of replacing low threshold voltage (LVT) with high threshold voltage (HVT) is adopted to lower the electricity leakage power consumption, and a main difficulty lies on that time sequence constraint of the circuit cannot be violated. According to characteristics of the time sequence device, two time delay changes including setup constraint and time delay from a clock end to an output end are analyzed; a method for building an association table among the time sequence devices is provided to record information of the association table among all time sequence devices; aiming at the requirement that an optimized circuit does not violates constraint of time sequence, a method of utilizing comparison between time delay variable (delta) and time relay allowance (slack) and the association table to filter replaceable time sequence devices is provided, so that the objective of lowering the electricity leakage power consumption is achieved.

Description

A kind of method reducing sequential element leakage power consumption in circuit

Technical field

Reduce the method for sequential element leakage power consumption in circuit be eda tool under the Timing Constraints not violating circuit, by the sequential device of low threshold voltage (LVT) being changed into the sequential device of high threshold voltage (HVT), to reduce the method for electricity leakage power dissipation.The invention belongs to EDA design field.

Background technology

Along with integrated circuit feature size constantly reduces, very general with the technology reducing dynamic power consumption by reducing supply voltage.Meanwhile, in order to the performance of holding circuit, usually select the device of low threshold voltage with realizing circuit function.But the application of the device of low threshold voltage, makes the ratio accounted in total power consumption of electricity leakage power dissipation constantly promote.We are by the time delay of estimation circuit, under the condition not violating temporal constraint, by a part of low threshold voltage device change the device of high threshold voltage into, to reach the object reducing electricity leakage power dissipation.

When holding circuit performance, the method utilizing two Vt technology to reduce electricity leakage power dissipation is widely used.On the one hand, the displacement of logical combination device is less on sequential impact.According to the result of static timing analysis, the surplus (slack) that current device postpones can be learnt, the delay difference (delta) that displacement occurs can be calculated simultaneously, thus determine to replace this unit.On the other hand, ratio shared in the former circuit of sequential device is less, and larger on the impact of sequential.Therefore, engineers, when utilizing two Vt replacement technique to fall electricity leakage power dissipation, usually can neglect sequential device.

Under current process node, circuit function becomes increasingly complex, and clock system is more and more huger, and the power consumption of sequential device can not be ignored in circuit.There are two features in the displacement of sequential device cell: 1) usually can affect setup time and the clock signal time delay to Q point, and the cost of time delay also can be larger than conventional combination device simultaneously; 2) may be interrelated between sequential device, this makes the estimation postponed need to consider that can relevant sequential device replace simultaneously.

We propose a kind of method reducing sequential element leakage power consumption in circuit herein: the change postponed to Q point by the change and clock signal calculating the setup time, set up the annexation between sequential device, to ensure that the temporal constraint that can not affect circuit replaced by sequential device simultaneously simultaneously.

Summary of the invention

The present invention proposes a kind of method reducing sequential element leakage power consumption in circuit, and this method considers the delay variation feature of sequential device displacement, and considers the incidence relation between sequential device.Illustrate above feature herein, propose corresponding solution, ensure that to greatest extent and replace sequential device simultaneously and do not destroy temporal constraint.

Sequential device is also with regard to trigger (Flip Flop), and it is a kind of device storing digital signal, has input end and output terminal, and has a special input end to be used for input clock signal.When received during clock signal, output terminal just can upgrade output signal according to input signal.Between two clock signals, the signal of output terminal all can not change.Be to the difference of logical signal: the output of logical signal is relevant with current input signal; And the output signal of trigger to be input signal when arriving to a upper clock signal relevant.

Fig. 1 is D flip flop, and input signal arrives D port, and clock signal arrives triangular marker place, outputs signal and exports from Q or QN end.D flip flop is that rising edge triggers, and namely when clock signal becomes 1 from 0, the signal of output terminal Q can according to the signal update of D end, and QN is just contrary with the signal of D.

In order to better calculation delay, we can be device setup delay model usually.Each Time Delay Model, a signal paths of usual respective devices.The signal path of a not gate A->Z is shown in Fig. 2, and the Changing Pattern of path two end signal.Due to the singularity of sequential device function, setup delay model usually can be more complicated.The Time Delay Model of foundation from input end to output terminal that can not be simple, because there is clock signal to control the transmission of data-signal.Usually, we can define two kinds of Time Delay Models: 1) from input end to clock end, as Fig. 3, and there is a setup constraint, before referring to that clock signal arrives, data-signal must shift to an earlier date ready time-constrain; 2) from clock end to output terminal, as Fig. 4, this is that signal is transferred to from the clock arrival moment Time Delay Model set up needed for output terminal.

Above Time Delay Model can be utilized, carry out static timing analysis.Calculate the delay surplus (slack) of often kind of device, compare with the amount of delay (delta) needed for displacement parallel operation part.As delta<slack, effectively can replace, and not violate temporal constraint.

In order to raise the efficiency, we can exchange a collection of unit component for usually in batches, then carry out the renewal of time delay value.Combinational logic circuit, by the mode of topological sorting, finds out the incoherent unit of a collection of sequential.Relevance between sequential device cannot be discharged with topological sorting, usually there will be inter-related situation, as shown in Figure 5.

We propose a kind of method setting up sequential device contingency table: first, based on the annexation of circuit, by traveling through from all sequential device output end Q to next sequential device input D, can obtain the Q point that all D point has annexation; Then according to the contingency table of D point, we can analyze the contingency table drawing all D points that Q point connects; Finally these two tables are merged, the contingency table that all sequential devices are put can be drawn.

When permute unit, we are by this contingency table, the dimension of sequential device according to association are sorted.Then, the Delay Variation value (delta) calculated in conjunction with Time Delay Model and already present delay surplus (slack), analyze delta and whether be less than slack value, determine that can active cell replaced.Meanwhile, after current permutation consumes a part of surplus, whether the sequential device of those associations also has enough delay surpluses to replace, if not, must be excluded from replaceable set.

Accompanying drawing explanation

Fig. 1 D flip flop

The signalling channel of Fig. 2 not gate and waveform relationship

The signalling channel that Fig. 3 setup retrains and waveform relationship

Fig. 4 clock end is to the signalling channel of output terminal and waveform relationship

Interrelated between Fig. 5 sequential device

concrete implementation step:

The method utilizing LVT to be replaced into HVT sequential device carries out electricity leakage power dissipation optimization, and operating process is as follows:

1) prepare circuit meshwork list, the Lib storehouse of standard block and Sdc file, carry out static timing analysis;

2) find out likely replaced timing unit, and calculate the delay variation (delta) needed for displacement;

3) filter out amount of delay and be greater than the unit postponing surplus (slack);

4) set up the contingency table of sequential device, and carry out ascending order arrangement according to associated apparatus number;

5) choose disposable units in order, get rid of other timing units that selected cell can have influence on simultaneously;

After having replaced, need to upgrade delay data, follow-up circuit optimization step can be proceeded.

Claims

1. reduce a method for sequential element leakage power consumption in circuit, the principal character relating to EDA design tool is:

(1) definition of two kinds of signalling channels and waveform delay in sequential device: one is that clock signal has setup temporal constraint (namely input signal needed ready time-constrain before clock signal) to input signal; Another kind is the time delay after clock signal arrives needed for output signal output;

(2) by traversal circuit diagram, the method for contingency table between sequential device is set up;

(3) by changing value and the sequential device contingency table of two kinds of waveform delay, judge that can sequential device carry out the Low Power Loss Solution that LVT replaces with HVT in order.

2. there is the combination of feature (1), (2), (3).

3. there is the combination of feature (2), (3).