CN101021882A - Design method for lowering large scale integrated circuit electricity leakage power dissipation - Google Patents
Design method for lowering large scale integrated circuit electricity leakage power dissipation Download PDFInfo
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- CN101021882A CN101021882A CN 200710078337 CN200710078337A CN101021882A CN 101021882 A CN101021882 A CN 101021882A CN 200710078337 CN200710078337 CN 200710078337 CN 200710078337 A CN200710078337 A CN 200710078337A CN 101021882 A CN101021882 A CN 101021882A
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- 238000003786 synthesis reaction Methods 0.000 claims description 7
- 238000012731 temporal analysis Methods 0.000 claims description 5
- 238000000700 time series analysis Methods 0.000 claims description 5
- 230000009977 dual effect Effects 0.000 claims description 4
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Abstract
This invention puts forward a design method for carrying out netlist logic combination to large scale IC with a dual-threshold method to reduce leakage and power loss, which first of all defines a set Q and uses the time sequence restriction with a loosen demand on Hvt library and time sequence for combination to get an initial Hvt netlist and carry out time sequence analysis and store the path information with time sequence deviation in the set Q and computing the delay time of each logic block of each path in the set Q and consumed static power loss, converting all logic blocks on the time sequence deviation paths to Lvt library to get the corrected netlist, changing the time sequence demand in Q circuit to strict time sequence restriction and paths converted to Lvt library in the set use Hvt library in priority repeatedly till there is not timed error and the leakage power reaches to the minimum.
Description
Technical field
The present invention relates to a kind of method for designing that reduces large scale integrated circuit electricity leakage power dissipation, specially refer to the method for designing that adopts the dual threshold voltage method to reduce large scale integrated circuit electricity leakage power dissipation.
Background technology
Along with the develop rapidly of semiconductor technology, the integrated level of integrated circuit is more and more higher, and the consumption of power is also increasing.Power consumption of integrated circuit generally is divided into two classes: a class is a dynamic power consumption, the power consumption that the function saltus step causes when being the integrated circuit operate as normal, one class is quiescent dissipation (a steelyard slepsydra electrical power consumed again), is the power consumption that circuit produces when being in inactive state or stationary state.
Along with integrated circuit fabrication process further improves, integrated circuit (IC) design has marched toward the epoch of deep-submicron and even sub-micro, and the metal-oxide semiconductor (MOS) door (abbreviating MOS as) that constitutes SIC (semiconductor integrated circuit) also constantly reduces.Because the existence of short-channel effect causes the increase of leakage current, finally causes electricity leakage power dissipation increasing.At present, the method for designing of comparatively effectively controlling electricity leakage power dissipation adopts the dual threshold voltage method that integrated circuit is netted the table logic synthesis exactly, and the ordered pair circuit is adjusted during again according to the net table that obtains.This method adopts two kinds of logical block cell libraries, a kind of is high threshold standard cell lib (abbreviating the Hvt storehouse as), but mos field effect transistor (abbreviate MOSFET) that time-delay bigger less by leakage current constitutes, another kind is low threshold criteria cell library (abbreviating the Lvt storehouse as), is made of the big but less MOSFET that delays time of leakage current.
Generally speaking, with the leakage current in a kind of Hvt of logical block and Lvt storehouse with there is following proportionate relationship time delay:
Time delay: Lvt: Hvt=1: 2
Leakage current: Lvt: Hvt=20: 1
In order to control electricity leakage power dissipation, just to control leakage current, in net table logic synthesis process, usually the high threshold standard block is applied in the circuit, but, can increases electricity leakage power dissipation too because the high threshold standard block is longer relatively time delay.Therefore, must consider leakage current and optimum matching between time delay in the circuit.
At present, the design cycle of prior art large scale integrated circuit net table logic synthesis (abbreviating Synthesis as) stage low-power consumption is generally: at first, it is comprehensive to net table with Lvt storehouse and relatively stricter temporal constraint, then, according to the net table sequential that obtains, carry out the processing in preferential use Hvt storehouse repeatedly in the path that timing off-set does not take place, till no timing error and power consumption number also reach minimum.
Said method is changed the replacing of only path that timing off-set does not take place being implemented the Hvt storehouse in the operation at non-critical path, therefore, Hvt library unit proportion is less, reduces the DeGrain of circuit power consumption, can't design the integrated circuit that satisfies the low-power consumption requirement sometimes.According to the result of emulation, comparatively speaking, this method speed is slow, and the amount that leakage current reduces is also smaller.
Summary of the invention
The present invention proposes a kind of employing dual threshold method large scale integrated circuit is netted the table logic synthesis, to reduce the method for designing of large scale integrated circuit electricity leakage power dissipation.Method for designing of the present invention is when netting the table logic synthesis to large scale integrated circuit, the definition set Q of elder generation also requires looser temporal constraint to carry out comprehensively with Hvt storehouse and sequential, obtain an initial Hvt storehouse net table and carry out time series analysis, the routing information that timing off-set takes place is kept among the set Q each logical block x of each paths among the set of computations Q
iT time delay
Ph(x
i) and the quiescent dissipation P that consumes
h(x
i); All change the logical block that takes place on the timing off-set path into the Lvt storehouse, obtain proofreading and correct the net table; The sequential of circuit among the set Q is required to change into the temporal constraint of comparison strictness, and preface constraint at this moment down, the processing that preferential use Hvt storehouse is carried out in the path that replaces to the Lvt storehouse among the pair set Q repeatedly is till no timing error and circuit electricity leakage power dissipation reach minimum.
When the processing in preferential use Hvt storehouse is carried out in method for designing of the present invention replaces to the Lvt storehouse in pair set Q path repeatedly, the difference and quiescent dissipation difference and set up the form E that comprises each logical block difference time delay and quiescent dissipation difference time delay of logical block is calculated T slack time among the set of computations Q of elder generation
Slack, search for the logical block of quiescent dissipation difference maximum among the form E, judge the T of this logical block correspondence
Slack-Δ t (x
i) whether be on the occasion of, if be on the occasion of, then replace the Lvt library unit, and make T with the Hvt library unit
Slack=T
Slack-Δ t (x
i), Δ P (x
i) be made as 0, if be negative value, then keep the Lvt library unit constant, Δ P (x
i) be made as 0, repeated searching, judgement, all logical blocks in integrated circuit all do not satisfy T
Slack-Δ t (x
iThe condition of) 〉=0 is finally netted table.
Adopt method for designing of the present invention when time series analysis, to carry the time in the path delay of time in model (the abbreviating wire load mode as) counting circuit according to line, judge whether to satisfy set up setup time (the abbreviating setuptime as) of regulation, satisfied then be considered as not occurring timing off-set, otherwise be considered as occurring timing off-set.
Adopt method for designing of the present invention can more use the logical block of Hvt cell library, give full play to the less characteristic of Hvt cell library logical block leakage current, can seek the reduction of power by means of the supression of leakage current.
Description of drawings
Fig. 1: the FB(flow block) that is integrated circuit net table logic synthesis method in the method for designing of the present invention.
Fig. 2: be that the FB(flow block) that handle in preferential use Hvt storehouse is carried out in the path that replaces to the Lvt storehouse among the method for designing pair set Q of the present invention repeatedly.
Below in conjunction with the drawings and the specific embodiments determination methods of the present invention is described in detail
1, definition set Q also carries out comprehensively obtaining Hvt storehouse net table 101 with Hvt storehouse and looser temporal constraint, and adopting the purpose of looser temporal constraint here is in order to add Hvt logical block as much as possible;
2, initial Hvt storehouse net table 101 is carried out time series analysis, promptly net table 101 is carried out delay time analysis:
Carry the time in the path delay of time in model (the abbreviating wire load mode as) counting circuit according to line, that judges whether it satisfy regulation sets up setup time (abbreviating setup time as) (judging promptly whether sequential is offset), if timing off-set do not occur, then net table 101 can directly offer the subsequent handling use; If timing off-set then enters next step;
3, the path that occurs timing off-set in the net table 101 is kept among the set Q, and each logical block x of each paths among the set of computations Q
iT time delay
Ph(x
i) and the quiescent dissipation P that consumes
h(x
i);
4, the logical block that will take place on the timing off-set path all changes the Lvt storehouse into, obtains proofreading and correct net table 401;
5, the sequential that will gather circuit among the Q requires to change into the temporal constraint of comparison strictness;
6, the path that replaces to the Lvt storehouse among the pair set Q processing of carrying out preferential use Hvt storehouse repeatedly is till no timing error and circuit electricity leakage power dissipation reach minimum;
7, obtain final net table 601.
The net table 601 that finally obtains is exactly a low-power consumption net table that adopts method for designing of the present invention to obtain.Because it is primary comprehensive directly to adopt the Hvt storehouse to carry out,, and help the improvement of sequential so the amount of Hvt library unit improves greatly.
Accompanying drawing 2 is that the FB(flow block) that handle in preferential use Hvt storehouse is carried out in the path that replaces to the Lvt storehouse among the method for designing pair set Q of the present invention repeatedly.As seen from the figure, this treatment scheme comprises following key step:
1, each logical block x of each paths among the set of computations Q
iT time delay
Pl(x
i) and the quiescent dissipation P that consumes
l(x
i);
2, calculate each logical block x
iUnder identical input condition, adopt the difference and quiescent dissipation difference time delay in different units storehouse:
Time delay difference: Δ t (x
i)=t
Ph(x
i)-t
Pl(x
i)
Quiescent dissipation difference: Δ P (x
i)=P
l(x
i)-P
h(x
i)
In the formula: t
Ph(x
i) and t
Pl(x
i) be respectively logical block x
iUnder identical input condition, adopt the time delay in Hvt storehouse and Lvt storehouse, P
l(x
i) and P
h(x
i) be respectively logical block x
iUnder identical input condition, adopt the quiescent dissipation in Hvt storehouse and Lvt storehouse;
3, T slack time of each paths among the set of computations Q
Slack:
In the formula: T
MaxBe the confinement time of each paths among the set Q, x
iT when adopting the Hvt library unit
p(x
i)=t
Ph(x
i), x
iT when adopting the Lvt library unit
p(x
i)=t
Pl(x
i), t
d(x
i) be x
iAnd the transmission delay between the last logical block;
4, set up form E, comprise T slack time of each paths among the set Q
SlackAnd each logical block x of this path correspondence
iDifference Δ t (x time delay
i) and quiescent dissipation difference DELTA P (x
i);
5, T among the search form E
Slack〉=0 circuit is searched quiescent dissipation difference DELTA P (x in this circuit
i) maximum logical block;
6, judge whether T
Slack-Δ t (x
i) 〉=0 (Δ t (x in the formula
i) be Δ P (x
i) respective value), be then with x
iLibrary unit become the Hvt library unit, and make T among the form E
Slack=T
Slack-Δ t (x
i), x among the form E
iQuiescent dissipation difference DELTA P (x
i) be made as 0, no longer participate in search, repeated execution of steps 5, otherwise carry out next step;
7, keep x
iThe Lvt library unit constant, Δ P (x
i) be made as 0, no longer participate in search, repeated execution of steps 5;
8, repeating step 5,6,7, and all logical blocks in integrated circuit all do not satisfy T
Slack-Δ t (x
iThe condition of) 〉=0;
9, obtain final net table 601.
According to simulation result, the amount of Hvt library unit has improved approximately 120% in the low-power consumption net table that method for designing of the present invention obtains than the prior art method for designing, and leakage current is approximately 1/3 of prior art method for designing.
Having adopted time delay among the method for designing embodiment of the present invention is Lvt: Hvt=1: 2, and leakage current is Lvt: Hvt=20: 1 cell library, obviously, also can adopt the library file that changes a lot under other process conditions.
Method for designing of the present invention also can have other various embodiments; under the situation of spirit that does not deviate from method for designing of the present invention and essence thereof; those skilled in the art work as can make various corresponding changes or distortion according to method for designing of the present invention, but these corresponding changes or distortion all belong to the claim protection domain of method for designing of the present invention.
Claims (3)
1, a kind of method for designing that adopts the dual threshold method to reduce electricity leakage power dissipation, logical block in the integrated circuit is made up of Lvt storehouse and Hvt storehouse, it is characterized in that: when large scale integrated circuit being netted the table logic synthesis, the definition set Q of elder generation also requires looser temporal constraint to carry out comprehensively with Hvt storehouse and sequential, obtain an initial Hvt storehouse net table and carry out time series analysis, the routing information that timing off-set takes place is kept among the set Q each logical block x of each paths among the set of computations Q
iT time delay
Ph(x
i) and the quiescent dissipation P that consumes
h(x
i), all change the logical block that takes place on the timing off-set path into the Lvt storehouse, obtain proofreading and correct the net table, the sequential of circuit among the set Q is required to change into the temporal constraint of comparison strictness, and preface constraint at this moment down, and the processing that preferential use Hvt storehouse is carried out in the path that replaces to the Lvt storehouse among the pair set Q repeatedly is till no timing error and circuit electricity leakage power dissipation reach minimum.
2, according to the described method for designing of claim 1, it is characterized in that: when the processing in preferential use Hvt storehouse is carried out in the path that replaces to the Lvt storehouse in pair set Q repeatedly, T slack time of difference time delay of logical block, quiescent dissipation difference and each paths among the first set of computations Q
Slack, and set up the form E comprise each logical block difference time delay and quiescent dissipation difference in each paths slack time and the path, the logical block of quiescent dissipation difference maximum among the search form E is judged the T of this logical block correspondence
Slack-Δ t (x
i) whether be on the occasion of, if be on the occasion of, then replace the Lvt library unit, and make T with the Hvt library unit
Slack=T
Slack-Δ t (x
i), Δ P (x
i) be made as 0, if be negative value, then keep the Lvt library unit constant, Δ P (x
i) be made as 0, repeated searching, judgement, all logical blocks in integrated circuit all do not satisfy T
Slack-Δ t (x
iThe condition of) 〉=0 is finally netted table.
3, according to the described method for designing of claim 1, it is characterized in that: carry the time in the path delay of time in model (the abbreviating wire load mode as) counting circuit according to line during time series analysis, judge whether to satisfy set up setup time (the abbreviating setup time as) of regulation, satisfied then be considered as not occurring timing off-set, otherwise be considered as occurring timing off-set.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100783374A CN100481092C (en) | 2007-03-27 | 2007-03-27 | Design method for lowering large scale integrated circuit electricity leakage power dissipation |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100783374A CN100481092C (en) | 2007-03-27 | 2007-03-27 | Design method for lowering large scale integrated circuit electricity leakage power dissipation |
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| CN100481092C CN100481092C (en) | 2009-04-22 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101826124A (en) * | 2009-03-06 | 2010-09-08 | 台湾积体电路制造股份有限公司 | System and method for performance modeling of integrated circuit |
| CN104573148A (en) * | 2013-10-17 | 2015-04-29 | 北京华大九天软件有限公司 | Method for lowering electricity leakage power consumption of time sequence device in circuit |
| CN107526874A (en) * | 2017-07-28 | 2017-12-29 | 广州星海集成电路基地有限公司 | A kind of low power consumption integrated circuit design method based on dual threashold threshold voltage |
| CN110457868A (en) * | 2019-10-14 | 2019-11-15 | 广东高云半导体科技股份有限公司 | The comprehensive optimization method and device of fpga logic, system |
| CN112214097A (en) * | 2020-10-20 | 2021-01-12 | 天津飞腾信息技术有限公司 | Method, device, equipment and storage medium for reducing low threshold unit |
-
2007
- 2007-03-27 CN CNB2007100783374A patent/CN100481092C/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101826124A (en) * | 2009-03-06 | 2010-09-08 | 台湾积体电路制造股份有限公司 | System and method for performance modeling of integrated circuit |
| CN101826124B (en) * | 2009-03-06 | 2016-06-29 | 台湾积体电路制造股份有限公司 | The System and method for of performance modeling of integrated circuit |
| CN104573148A (en) * | 2013-10-17 | 2015-04-29 | 北京华大九天软件有限公司 | Method for lowering electricity leakage power consumption of time sequence device in circuit |
| CN104573148B (en) * | 2013-10-17 | 2017-11-14 | 北京华大九天软件有限公司 | A kind of method of sequential element leakage power consumption in reduction circuit |
| CN107526874A (en) * | 2017-07-28 | 2017-12-29 | 广州星海集成电路基地有限公司 | A kind of low power consumption integrated circuit design method based on dual threashold threshold voltage |
| CN110457868A (en) * | 2019-10-14 | 2019-11-15 | 广东高云半导体科技股份有限公司 | The comprehensive optimization method and device of fpga logic, system |
| CN112214097A (en) * | 2020-10-20 | 2021-01-12 | 天津飞腾信息技术有限公司 | Method, device, equipment and storage medium for reducing low threshold unit |
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| Publication number | Publication date |
|---|---|
| CN100481092C (en) | 2009-04-22 |
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