CN115796088A - Voltage distribution method for double-track standard cell library - Google Patents
Voltage distribution method for double-track standard cell library Download PDFInfo
- Publication number
- CN115796088A CN115796088A CN202211472809.5A CN202211472809A CN115796088A CN 115796088 A CN115796088 A CN 115796088A CN 202211472809 A CN202211472809 A CN 202211472809A CN 115796088 A CN115796088 A CN 115796088A
- Authority
- CN
- China
- Prior art keywords
- path
- unit
- vddh
- replacement
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention provides a voltage distribution method for a double-track standard cell library, which comprises the following steps: the unit rough replacement based on the sensitivity is that the replacement sensitivity of each unit is calculated according to the delay and the power consumption of each unit, and partial high-voltage units in the circuit are replaced by low-voltage units according to the sequence of the replacement sensitivity from high to low, so that a target chip with the estimated value of each path delay margin being the minimum positive value is obtained; and then, carrying out unit fine adjustment based on path unit classification on the target chip, namely, carrying out classification processing on each path in the target chip and units in each path, and then, executing replacement adjustment of the units, so that the occurrence of the condition that a low-voltage unit drives a high-voltage unit is further reduced while time sequence violation is eliminated, the target chip with the delay allowance accurate value of each path being the minimum positive value is obtained, and meanwhile, the circuit power consumption is reduced to the maximum extent.
Description
Technical Field
The invention relates to the field of special integrated circuit design, in particular to a voltage distribution method for a double-track standard cell library.
Background
With the reduction of the process size and the improvement of the chip integration level, the power consumption of a single transistor is reduced, but the number of transistors in a unit area of a chip is greatly increased, so that the unit area power consumption and the overall power consumption of an integrated circuit are increased at an incredible speed. The higher power consumption per unit area means that the chip will operate at higher temperature, which in turn leads to a series of problems, such as increased signal noise, mechanical cracks, increased chemical corrosion, increased leakage current, etc. In addition, the increase of the chip power consumption also brings a serious challenge to the power supply endurance problem of the product. In recent years, with the rapid development of portable smart devices, devices such as smart phones and tablet smart watches have been incorporated into the aspects of people's lives. These products often use chips with advanced processes, performance is rapidly improved year by year, the products are light and thin, and batteries are often used for power supply. The requirements on heat dissipation and endurance of the equipment are extremely high. Therefore, in order to improve the endurance time of the device and the market competitiveness, one of the methods is to reduce the power consumption of the device.
In past circuit designs, all circuits used the same supply voltage, but as the supply voltage continued to drop with process advances, the advent of multiple supply voltage technology has provided designers with the potential to reduce circuit power consumption. Multiple supply voltage technology is taking an increasingly important position in low power consumption designs.
The principle of the dual-power voltage method is that power is inversely proportional to the square of voltage, so that dynamic power consumption can be effectively reduced by reducing voltage, and because reducing power supply voltage can increase time delay and reduce the performance of a circuit, a low-voltage unit is required to be adopted on the premise of ensuring time sequence convergence and meeting the performance requirement, and a general dual-power voltage method adopts two standard units of power supply voltage: a high supply voltage unit and a low supply voltage unit. When the low voltage unit drives the high voltage unit, the high voltage unit may generate a leakage current, so that, when the unit is distributed, consideration needs to be given to reducing the case where the low voltage unit drives the high voltage unit. In the prior art, the CVS and the ECVS both allocate proper power to the gates through the circuit with reverse topological level sequence from the primary output to the primary input, but the influence of the increment of the gate delay and the decrement of the gate power consumption on the total delay and the total power consumption of the circuit after the power is allocated is not considered. In fact, the delay variation of the gates after the power is distributed to the gates on different paths is different, which affects the accuracy of power consumption optimization. Therefore, it is necessary to design a low power consumption voltage distribution method capable of improving the power consumption optimization precision to reduce the power consumption of the circuit to the maximum extent.
Disclosure of Invention
The invention aims to provide a voltage distribution method for a dual-rail standard cell library in order to overcome the defects of the existing low-power consumption technology.
In order to achieve the purpose, the invention provides the following technical scheme: a voltage distribution method facing a dual-rail standard cell bank comprises the following steps: the method comprises the steps of firstly carrying out unit rough replacement based on sensitivity on each double-track standard unit on each path in a target chip to obtain the target chip of which the estimated value of each path delay margin is the minimum positive value, then carrying out unit fine adjustment based on path unit classification on the target chip to eliminate errors caused by rough estimation of the margin during rough replacement of the delay margin, obtaining the target chip of which the accurate value of each path delay margin is the minimum positive value, and simultaneously reducing the power consumption of the circuit to the maximum extent.
Furthermore, the double-track standard cell library is composed of a high Voltage (VDDH) standard cell and a low Voltage (VDDL) standard cell, the VDDH standard cell and the VDDL standard cell are connected with the same group of high and low voltage power lines, a PMOS source end and a substrate end in the VDDH standard cell are connected with the high voltage power line for power supply, the low voltage power line is suspended, a PMOS source end in the VDDL standard cell is connected with the low voltage power line for power supply, and the substrate end is connected with the high voltage power line for power supply.
Further, the coarse replacement of the sensitivity-based cell comprises the steps of:
s1: performing logic synthesis by using a VDDH standard unit to obtain a target chip of a full VDDH unit, generating a gate-level netlist of the full VDDH unit, and performing rear-end layout and wiring on the target chip;
s2: performing static timing analysis on a target chip with all VDDH units to obtain delay margins sleep of all paths in the target chip, and delay (VDDH) and power consumption power (VDDH) of each VDDH unit;
s3: calculating delay (VDDL) and power consumption power (VDDL) after each VDDH unit is replaced by a corresponding VDDL unit, and further calculating a replacement delay difference delta delay, a replacement power consumption difference delta power and replacement sensitivity of each unit;
s4: randomly selecting a path based on a target chip of all VDDH units, and sequencing all the VDDH units on the path from high to low according to the corresponding replacement sensitivity; sequentially replacing the VDDH units on the path with VDDL units in sequence, obtaining a path delay margin slack and a replacement delay difference delta delay of the unit according to static time sequence analysis after each unit replacement, estimating and updating the path delay margin slack, and continuing to replace the next VDDH unit if the estimated value of the path delay margin slack is positive after updating; if the estimated value of the path delay margin slack is negative after updating, the current VDDH unit replacement is cancelled, the rough replacement of the path is finished, and all units in the path are marked to be in a fixed state after the rough replacement of the path is finished;
s5: switching to the next path which is not roughly replaced, estimating and updating the path delay margin sleep according to the path delay margin sleep obtained by static timing analysis and the replacement delay difference delta delay of the unit with the fixed state in the path, and sequencing all VDDH units with the unfixed state on the path according to the sequence of the corresponding replacement sensitivity from high to low;
s6: sequentially replacing VDDH units in a non-fixed state on the path with VDDL units according to the sequence of replacement sensitivity from high to low, continuously estimating and updating the path delay margin sleep according to the replacement delay time difference delta delay of the unit after each unit replacement, continuously replacing the next VDDH unit if the estimated value of the path delay margin sleep is positive, canceling the replacement of the VDDH unit this time if the estimated value of the path delay margin sleep is negative, finishing the rough replacement of the path, and marking all units in the non-fixed state in the path as a fixed state after the rough replacement of the path is finished;
s7: judging whether a path which is not roughly replaced exists or not, if so, entering a step S6; if not, the unit rough replacement of the target chip is completed, a rough gate-level netlist is output, and all units in the target chip are restored to a non-fixed state.
Further, the sensitivity-based unit roughly replaces the delay (VDDL), the power consumption power (VDDL), and the replacement delay difference Δ delay in step S3, and the calculation formulas of the replacement power consumption difference Δ power and the replacement sensitivity are as follows:
Δdelay＝delay(VDDL)-delay(VDDH)
Δpower＝|power(VDDL)-power(VDDH)|
wherein alpha is a scale factor and is obtained by simulation fitting; VDDH is the voltage value of the high voltage power supply; VDDL is low voltage power supply voltage; the VTH is the threshold voltage of the transistor in the dual-rail standard cell library, and is obtained from a transistor simulation model or simulation provided by a process plant.
Further, the unit fine adjustment based on the path unit classification comprises the following steps:
the first step is as follows: randomly selecting a path which is not subjected to fine adjustment, and carrying out time sequence analysis on the path by using a static time sequence analysis tool to obtain an accurate value of a delay margin of the path;
the second step is that: if the delay margin accurate value of the path is less than 0, the path is a time sequence violation path, and an A-type replacement strategy is executed on the path; if the delay allowance accuracy value of the path is greater than 0, the path is a time sequence compliance path, and a B-type replacement strategy is executed on the path;
the third step: after the fine adjustment of the path is completed, all units in the path are marked as a fixed state, and then the fixed units are not replaced;
the fourth step: judging whether paths which are not finely adjusted exist or not, and if so, returning to the first step; and if not, finishing fine adjustment of the unit of the target chip and outputting the final gate-level netlist.
Further, the executing the class a policy includes the following steps:
the first step is as follows: dividing the VDDL units in the non-fixed state in the A-type path into three types A1, A2 and A3, wherein the A1 type is an isolated VDDL unit, namely front and rear stage units are VDDL units of the VDDH unit, the A2 type is a boundary VDDL unit, namely only one of the front stage unit or the rear stage unit is the VDDL unit of the VDDH unit, and the A3 type is a middle VDDL unit, namely the front and rear stage units are VDDL units of the VDDL unit;
the second step is that: sequencing the VDDL units in the path in a non-fixed state according to the sequence of A1, A2 and A3, and sequencing the inside of each category from low to high according to the unit replacement power consumption difference delta power;
the third step: sequentially replacing the VDDL units in the path in the unfixed state with the VDDH units according to the sequence in the second step, performing static time sequence analysis again after each replacement, updating the accurate value of the delay allowance of the path, and if the accurate value of the delay allowance is negative, continuing to replace the VDDL in the next unfixed state; if the delay margin accuracy value is positive, finishing the fine adjustment of the path.
Further, the class B policy includes the following steps:
the first step is as follows: dividing the VDDH units in the non-fixed state in the B-type path into three types B1, B2 and B3, wherein the B1 type is an isolated VDDH unit, namely front and rear stage units are VDDH units of the VDDL unit, the B2 type is a boundary VDDH unit, namely only one of the front stage unit or the rear stage unit is the VDDH unit of the VDDL unit, and the B3 type is a middle VDDH unit, namely the front and rear stage units are VDDH units of the VDDH unit;
the second step: sequencing the VDDH units in the path in a non-fixed state according to the sequence of B1, B2 and B3, and sequencing the interior of each category from low to high according to the replacement delay difference delta delay;
the third step: sequentially replacing the VDDH units in the path in the unfixed state with VDDL units according to the sequence in the second step, performing static time sequence analysis again after each replacement, updating the accurate value of the delay allowance of the path, and if the accurate value of the delay allowance is positive, continuing to replace the VDDH unit in the next unfixed state; and if the accurate value of the delay allowance is negative, the current replacement of the VDDH unit is cancelled, and the fine adjustment of the path is finished.
Compared with the prior art, the voltage distribution method for the double-track standard cell library has the following benefits:
1. the unit rough replacement method based on the sensitivity realizes quick replacement by a method of roughly calculating the sensitivity, avoids a large amount of repeated iterations of a time sequence analysis tool, and saves time;
2. the cell fine adjustment method based on the path cell classification reduces the occurrence of the condition that a low-voltage cell drives a high-voltage cell, and reduces the extra leakage power consumption generated by the driving.
Drawings
FIG. 1 is a flow chart of a voltage distribution method for a dual-rail standard cell library according to the present invention;
fig. 2 is a circuit structure comparison of the dual-rail standard cell proposed by the present invention and a conventional standard cell.
Detailed Description
The present invention will be described in further detail with reference to examples.
In this embodiment, as shown in fig. 1, as can be seen from a comparison between the circuit structures of the dual-rail standard cell and the conventional standard cell, the dual-rail standard cell library is composed of a VDDH standard cell and a VDDL standard cell, the VDDH standard cell and the VDDL standard cell are commonly connected to a same group of high-voltage and low-voltage power lines, a PMOS source terminal and a substrate terminal inside the VDDH standard cell are connected to a high-voltage power line for power supply, a low-voltage power line is suspended, a PMOS source terminal inside the VDDL standard cell is connected to a low-voltage power line for power supply, and a substrate terminal is connected to a high-voltage power line for power supply.
In this embodiment, as shown in fig. 2, it can be seen that the voltage distribution method for the dual-rail standard cell library provided by the present invention is implemented in two steps: coarse replacement of cells based on sensitivity and fine adjustment of cells based on path cell classification.
In this embodiment, the sensitivity-based unit rough replacement method calculates the replacement sensitivity of each unit according to the delay and power consumption of each unit, replaces a part of high-voltage units in the circuit with low-voltage units in the sequence from high to low in the replacement sensitivity, and completes the preliminary rough distribution of the high-voltage and low-voltage units, and includes the following specific operation steps:
s1: performing logic synthesis by using a VDDH standard unit, selecting ASIC synthesis in a synthesis mode to obtain a target chip of a full VDDH unit, generating a gate-level netlist of the full VDDH unit, and performing rear-end layout and wiring on the target chip;
s2: performing static time sequence analysis on a target chip with all VDDH units to obtain delay margins slack of all paths in the target chip, and delay (VDDH) and power consumption power (VDDH) of each VDDH unit;
s3: calculating the delay (VDDL) and the power consumption power (VDDL) of each VDDH unit after being replaced by the corresponding VDDL unit, further calculating the replacement delay difference delta delay, the replacement power consumption difference delta power and the replacement sensitivity of each unit, wherein the calculation formula is as follows:
Δdelay＝delay(VDDL)-delay(VDDH)
Δpower＝|power(VDDL)-power(VDDH)|
wherein alpha is a scale factor and is obtained by simulation fitting; VDDH is the voltage value of the high voltage power supply; VDDL is low voltage power supply voltage; VTH is the threshold voltage of the transistor in the double-track standard cell library, and is obtained from a transistor simulation model or simulation provided by a process plant;
s4: randomly selecting a path based on a target chip of all VDDH units, and sequencing all the VDDH units on the path from high to low according to the corresponding replacement sensitivity; then sequentially replacing VDDH units on the path with VDDL units in sequence, obtaining the path delay margin sleep and the replacement delay difference delta delay of the unit according to static time sequence analysis after each unit replacement, and estimating and updating the path delay margin sleep in the following way:
slack(new)＝slack(old)-Δdelay
wherein, the slack (old) is a delay allowance before replacement; the sleep (new) is the delay margin after replacement; if the estimated value of the path delay margin sleep is positive after updating, continuing to replace the next VDDH unit; if the estimated value of the path delay margin slack is negative after updating, the current VDDH unit replacement is cancelled, the rough replacement of the path is finished, and all units in the path are marked to be in a fixed state after the rough replacement of the path is finished;
s5: switching to the next path without rough replacement, and estimating and updating the path delay margin sleep according to the path delay margin sleep obtained by static timing analysis and the replacement delay difference Δ delay of the existing fixed-state unit in the path as follows:
slack(new)＝slack(old)-Δdelay
wherein, the slack (old) is a delay allowance before replacement; the sleep (new) is the delay margin after replacement;
then sequencing all the VDDH units in the non-fixed state on the path from high to low according to the corresponding replacement sensitivity;
s6: sequentially replacing VDDH units in a non-fixed state on the path with VDDL units according to the sequence of the sensitivity from high to low, continuously estimating and updating the path delay margin slack according to the replacement delay time difference delta delay of the units after each unit replacement, wherein the estimation and updating of the path delay margin slack is as follows:
slack(new)＝slack(old)-Δdelay
wherein, the sleep (old) is a delay allowance before replacement; the sleep (new) is the delay margin after replacement; if the estimated value of the path delay margin sleep is positive after updating, continuing to replace the next VDDH unit, if the estimated value of the path delay margin sleep is negative after updating, canceling the VDDH unit replacement at this time, finishing the rough replacement of the path, and marking all units in the path in a non-fixed state as a fixed state after finishing the rough replacement of the path;
s8: judging whether paths which are not roughly replaced exist or not, if so, entering a step S6; if not, the unit rough replacement of the target chip is completed, a rough gate-level netlist is output, and all units in the target chip are restored to a non-fixed state.
In this embodiment, the unit fine adjustment method based on the path unit classification further optimizes the target chip, classifies each path and unit in each path in the target chip, and then performs the unit replacement adjustment, so as to further reduce the occurrence of the situation that the low-voltage unit drives the high-voltage unit and reduce the extra leakage power consumption caused by the occurrence of the time violation, while eliminating the time violation, and the specific operation steps are as follows:
the first step is as follows: randomly selecting a path which is not subjected to fine adjustment, and carrying out time sequence analysis on the path by using a static time sequence analysis tool to obtain an accurate value of a delay margin of the path;
the second step is that: if the delay margin accuracy value of the path is less than 0, the path is a time sequence violation path, and an A-type replacement strategy is executed on the path; if the delay allowance accuracy value of the path is greater than 0, the path is a time sequence compliance path, and a B-type replacement strategy is executed on the path;
the third step: after the fine adjustment of the path is completed, all units in the path are marked as a fixed state, and then the fixed units are not replaced;
the fourth step: judging whether paths which are not finely adjusted exist or not, and if so, returning to the first step; and if not, finishing fine adjustment of the unit of the target chip and outputting the final gate-level netlist.
The specific operation steps for executing the A-type strategy are as follows:
the first step is as follows: dividing the VDDL units in the non-fixed state in the A-type path into three types A1, A2 and A3, wherein the A1 type is an isolated VDDL unit, namely front and rear stage units are VDDL units of the VDDH unit, the A2 type is a boundary VDDL unit, namely only one of the front stage unit or the rear stage unit is the VDDL unit of the VDDH unit, and the A3 type is a middle VDDL unit, namely the front and rear stage units are VDDL units of the VDDL unit;
the second step is that: sequencing the VDDL units in the path in a non-fixed state according to the sequence of A1, A2 and A3, and sequencing the inside of each category from low to high according to the unit replacement power consumption difference delta power;
the third step: sequentially replacing the VDDL units in the path in the non-fixed state with the VDDH units according to the sequence in the second step, performing static time sequence analysis again after each replacement, updating the accurate value of the delay allowance of the path, and if the accurate value of the delay allowance is negative, continuing to replace the VDDL in the next non-fixed state; if the delay margin accuracy value is positive, finishing the fine adjustment of the path.
The specific operation steps for executing the B-type strategy are as follows:
the first step is as follows: dividing the VDDH units in the non-fixed state in the B type path into three types B1, B2 and B3, wherein the B1 type is an isolated VDDH unit, namely the front-stage unit and the rear-stage unit are all VDDL units of the VDDL unit, the B2 type is a boundary VDDH unit, namely only one of the front-stage unit or the rear-stage unit is a VDDH unit of the VDDL unit, and the B3 type is a middle VDDH unit, namely the front-stage unit and the rear-stage unit are all VDDH units of the VDDH unit;
the second step: sequencing the VDDH units in the path in a non-fixed state according to the sequence of B1, B2 and B3, and sequencing the interior of each category from low to high according to the replacement delay difference delta delay;
the third step: sequentially replacing the VDDH units in the path in the unfixed state with VDDL units according to the sequence in the second step, performing static time sequence analysis again after each replacement, updating the accurate value of the delay allowance of the path, and if the accurate value of the delay allowance is positive, continuing to replace the VDDH unit in the next unfixed state; and if the accurate value of the delay allowance is negative, the current replacement of the VDDH unit is cancelled, and the fine adjustment of the path is finished.
Although the invention has been described with reference to preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention should be determined by the appended claims.
Claims (7)
1. A voltage distribution method for a double-track standard unit library is characterized in that a unit rough replacement based on sensitivity is carried out on each double-track standard unit on each path in a target chip, a target chip with the estimated value of each path delay margin being the minimum positive value is obtained, unit fine adjustment based on path unit classification is carried out on the target chip, errors caused by rough replacement of the estimated value of the delay margin are eliminated, the target chip with the accurate value of each path delay margin being the minimum positive value is obtained, and meanwhile circuit power consumption is reduced to the maximum degree.
2. The voltage distribution method for the double-track standard cell library according to claim 1, wherein the double-track standard cell library is composed of a VDDH standard cell and a VDDL standard cell, the VDDH standard cell and the VDDL standard cell are commonly connected with a same group of high-voltage and low-voltage power lines, a PMOS source end and a substrate end inside the VDDH standard cell are connected with the high-voltage power line for power supply, the low-voltage power line is suspended, a PMOS source end inside the VDDL standard cell is connected with the low-voltage power line for power supply, and the substrate end is connected with the high-voltage power line for power supply.
3. The method according to claim 2, wherein the performing of the sensitivity-based cell coarse replacement comprises the steps of:
s1: performing logic synthesis by using a VDDH standard unit to obtain a target chip of a full VDDH unit, generating a gate-level netlist of the full VDDH unit, and performing rear-end layout and wiring on the target chip;
s2: performing static time sequence analysis on a target chip with all VDDH units to obtain delay margins slack of all paths in the target chip, and delay (VDDH) and power consumption power (VDDH) of each VDDH unit;
s3: calculating delay (VDDL) and power consumption power (VDDL) after each VDDH unit is replaced by the corresponding VDDL unit, and further calculating the replacement delay difference delta delay, the replacement power consumption difference delta power and the replacement sensitivity of each unit;
s4: randomly selecting a path based on a target chip of all VDDH units, and sequencing all the VDDH units on the path from high to low according to the corresponding replacement sensitivity; sequentially replacing the VDDH units on the path with VDDL units in sequence, obtaining a path delay margin slack and a replacement delay difference delta delay of the unit according to static time sequence analysis after each unit replacement, estimating and updating the path delay margin slack, and continuing to replace the next VDDH unit if the estimated value of the path delay margin slack is positive after updating; if the estimated value of the path delay margin sleep is negative after updating, canceling the current VDDH unit replacement, finishing the rough replacement of the path, and marking all units in the path in a fixed state after finishing the rough replacement of the path;
s5: switching to the next path which is not subjected to rough replacement, estimating and updating the path delay margin slack according to the path delay margin slack obtained by static timing analysis and the replacement delay difference delta delay of the existing fixed-state units in the path, and then sequencing all the VDDH units in the non-fixed state on the path from high to low according to the corresponding replacement sensitivity;
s6: sequentially replacing VDDH units in a non-fixed state on the path with VDDL units according to the sequence of replacement sensitivity from high to low, continuously estimating and updating the path delay margin sleep according to the replacement delay time difference delta delay of the unit after each unit replacement, continuously replacing the next VDDH unit if the estimated value of the path delay margin sleep is positive, canceling the replacement of the VDDH unit this time if the estimated value of the path delay margin sleep is negative, finishing the rough replacement of the path, and marking all units in the non-fixed state in the path as a fixed state after the rough replacement of the path is finished;
s7: judging whether a path which is not roughly replaced exists or not, if so, entering a step S6; if not, the unit rough replacement of the target chip is completed, a rough gate-level netlist is output, and all units in the target chip are restored to a non-fixed state.
4. The voltage distribution method for the dual-rail standard cell library according to claim 3, wherein the sensitivity-based cell roughly replaces the delay (VDDL), the power consumption (VDDL), the replacement delay difference Δ delay, the replacement power consumption difference Δ power, and the replacement sensitivity in step S3 by the following calculation formulas:
Δdelay＝delay(VDDL)-delay(VDDH)
Δpower＝|power(VDDL)-power(VDDH)|
wherein alpha is a scale factor and is obtained by simulation fitting; VDDH is the voltage value of the high voltage power supply; VDDL is low voltage power supply voltage value; the VTH is the threshold voltage of the transistor in the dual-rail standard cell library, and is obtained from a transistor simulation model or simulation provided by a process plant.
5. The method according to claim 4, wherein the step of performing the cell fine adjustment based on the path cell classification comprises the following steps:
the first step is as follows: randomly selecting a path which is not subjected to fine adjustment, and performing time sequence analysis on the path by using a static time sequence analysis tool to obtain an accurate value of a delay margin of the path;
the second step is that: if the delay margin accuracy value of the path is less than 0, the path is a time sequence violation path, and an A-type replacement strategy is executed on the path; if the delay allowance accuracy value of the path is greater than 0, the path is a time sequence compliance path, and a B-type replacement strategy is executed on the path;
the third step: after the fine adjustment of the path is completed, all units in the path are marked as a fixed state, and then the fixed units are not replaced;
the fourth step: judging whether paths which are not finely adjusted exist or not, and if so, returning to the first step; and if not, finishing fine adjustment of the unit of the target chip and outputting the final gate-level netlist.
6. The method according to claim 5, wherein executing the class A strategy comprises the following steps:
the first step is as follows: dividing the VDDL units in the non-fixed state in the A-type path into three types A1, A2 and A3, wherein the A1 type is an isolated VDDL unit, namely the front-stage unit and the rear-stage unit are all VDDL units of the VDDH unit, the A2 type is a boundary VDDL unit, namely only one of the front-stage unit or the rear-stage unit is a VDDL unit of the VDDH unit, and the A3 type is a middle VDDL unit, namely the front-stage unit and the rear-stage unit are all VDDL units of the VDDL unit;
the second step is that: sequencing the VDDL units in the path in a non-fixed state according to the sequence of A1, A2 and A3, and sequencing the inside of each category from low to high according to the unit replacement power consumption difference delta power;
the third step: sequentially replacing the VDDL units in the path in the non-fixed state with the VDDH units according to the sequence in the second step, performing static time sequence analysis again after each replacement, updating the accurate value of the delay allowance of the path, and if the accurate value of the delay allowance is negative, continuing to replace the VDDL in the next non-fixed state; if the delay margin accuracy value is positive, finishing the fine adjustment of the path.
7. The method according to claim 5, wherein the class B strategy comprises the following steps:
the first step is as follows: dividing the VDDH units in the non-fixed state in the B type path into three types B1, B2 and B3, wherein the B1 type is an isolated VDDH unit, namely the front-stage unit and the rear-stage unit are all VDDL units of the VDDL unit, the B2 type is a boundary VDDH unit, namely only one of the front-stage unit or the rear-stage unit is a VDDH unit of the VDDL unit, and the B3 type is a middle VDDH unit, namely the front-stage unit and the rear-stage unit are all VDDH units of the VDDH unit;
the second step: sequencing the VDDH units in the path in a non-fixed state according to the sequence of B1, B2 and B3, and sequencing the interior of each category from low to high according to the replacement delay difference delta delay;
the third step: sequentially replacing the VDDH units in the path in the unfixed state with VDDL units according to the sequence in the second step, performing static time sequence analysis again after each replacement, updating the accurate value of the delay allowance of the path, and if the accurate value of the delay allowance is positive, continuing to replace the VDDH unit in the next unfixed state; and if the accurate value of the delay margin is negative, the current replacement of the VDDH unit is cancelled, and the fine adjustment of the path is finished.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211472809.5A CN115796088A (en) | 2022-11-23 | 2022-11-23 | Voltage distribution method for double-track standard cell library |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211472809.5A CN115796088A (en) | 2022-11-23 | 2022-11-23 | Voltage distribution method for double-track standard cell library |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115796088A true CN115796088A (en) | 2023-03-14 |
Family
ID=85440406
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211472809.5A Pending CN115796088A (en) | 2022-11-23 | 2022-11-23 | Voltage distribution method for double-track standard cell library |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115796088A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116090399A (en) * | 2023-04-06 | 2023-05-09 | 中国人民解放军国防科技大学 | Trigger conversion method and device based on time margin established by data output end |
-
2022
- 2022-11-23 CN CN202211472809.5A patent/CN115796088A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116090399A (en) * | 2023-04-06 | 2023-05-09 | 中国人民解放军国防科技大学 | Trigger conversion method and device based on time margin established by data output end |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Yang et al. | Approximate XOR/XNOR-based adders for inexact computing | |
| Gupta et al. | Gate-length biasing for runtime-leakage control | |
| CN100350414C (en) | System and method for statistical timing analysis of digital circuits | |
| CN110442926B (en) | Statistical timing analysis method for integrated circuit under advanced process and low voltage | |
| EP1168205B1 (en) | Automatic circuit generation apparatus and method, and computer program product for executing the method | |
| CN110428048B (en) | Binaryzation neural network accumulator circuit based on analog delay chain | |
| US20090016141A1 (en) | Methods and Arrangements for Enhancing Power Management Systems in Integrated Circuits | |
| US8336012B2 (en) | Automated timing optimization | |
| US20090241079A1 (en) | Method and system for achieving power optimization in a hierarchical netlist | |
| CN115796088A (en) | Voltage distribution method for double-track standard cell library | |
| Sirisantana et al. | Enhancing yield at the end of the technology roadmap | |
| Rahman et al. | Design automation tools and libraries for low power digital design | |
| US8255859B2 (en) | Method and system for verification of multi-voltage circuit design | |
| US8813006B1 (en) | Accelerated characterization of circuits for within-die process variations | |
| US10223485B2 (en) | Reliability verification based on combining voltage propagation with simulation | |
| CN102664142B (en) | Insertion method for filling redundant polysilicon strip arrays in existing layout | |
| US20080072191A1 (en) | Sanity checker for integrated circuits | |
| US8539388B2 (en) | Method and apparatus for low power semiconductor chip layout and low power semiconductor chip | |
| CN100481092C (en) | Design method for lowering large scale integrated circuit electricity leakage power dissipation | |
| US7885798B2 (en) | Closed-loop modeling of gate leakage for fast simulators | |
| Vujkovic et al. | Optimized power-delay curve generation for standard cell ICs | |
| Xu et al. | Dynamic characteristics of power gating during mode transition | |
| Varatkar et al. | Stochastic networked computation | |
| CN113868991B (en) | Design method of digital standard cell under near-threshold power supply voltage | |
| Dierickx et al. | Propagating variability from technology to system level |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |