CN103425820A - Layout method for reducing buffer inserting number - Google Patents

Layout method for reducing buffer inserting number Download PDF

Info

Publication number
CN103425820A
CN103425820A CN2013102908331A CN201310290833A CN103425820A CN 103425820 A CN103425820 A CN 103425820A CN 2013102908331 A CN2013102908331 A CN 2013102908331A CN 201310290833 A CN201310290833 A CN 201310290833A CN 103425820 A CN103425820 A CN 103425820A
Authority
CN
China
Prior art keywords
length
line
peripheral cell
crucial
less
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2013102908331A
Other languages
Chinese (zh)
Other versions
CN103425820B (en
Inventor
陈钢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to CN201310290833.1A priority Critical patent/CN103425820B/en
Publication of CN103425820A publication Critical patent/CN103425820A/en
Application granted granted Critical
Publication of CN103425820B publication Critical patent/CN103425820B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

Disclosed is a layout method for reducing the buffer inserting number. The method mainly aims at reducing the number of buffer elements to be inserted so as to reduce the delay and congestion degree. In a layout process, a connecting line with the length larger than a key buffer length is selected, whether elements connected with the connecting line and peripheral elements of the elements satisfy moving conditions of the layout method or not is sequentially judged, and if yes, the elements are moved. The operation is repeated until lengths of all the connecting lines are enabled to be smaller than a preset maximum length by moving the elements. The buffer elements are inserted among the connecting lines with lengths exceeding the key buffer length now, and the step is repeated until finish of layout.

Description

A kind of layout method that reduces buffering insertion number
Technical field
The present invention relates to integrated circuit physical Design field, particularly a kind of layout, wiring and buffering are inserted and are mutually combined to reduce buffer number, improve the method for layout quality.
 
Background technology
The purpose of integrated circuit physical Design is that circuit meshwork list (netlist) is being met to the process of carrying out arrangement space under certain constraint condition.The key step of physical Design comprises layout (Placement), and wiring (Routing) builds Clock Tree (clock tree) and buffering insertion (buffer insertion) etc.Insert (repeater insertion) also referred to as relay element when wherein buffering is inserted with.
Circuit meshwork list is a figure who consists of element and line.The task of layout is that the element in circuit network is arranged in to geometrical plane or Zhong De appropriate location, space, and wiring is that the line between circuit component is made to Vehicle routing in plane or space.If after wiring, have long especially line between element, need in the middle of these lines, insert buffer element so, with the length that guarantees line within a certain length-specific scope.
The main target of layout is to make the time delay of circuit after wiring short as far as possible, and because the accurate Calculation cost of time delay is very high, so this target usually is simplified as and seeks the shortest route total length.To consider in addition some other factors, such as, layout area, required time of expending of the degree of crowding of element and line and placement-and-routing etc., these factors are expressed in the mode of constraint condition usually.The effect of layout finally will realize by connecting up.Modern layout software often combines with wiring software.Some layout software are the constraint condition as layout the estimated value of the crowded property of wiring and length of arrangement wire, and other layout software are directly used a fast wiring program to assess more accurately length of arrangement wire in layout.
Although the method that placement-and-routing combines occurred, most of placement-and-routing software does not insert direct combination with buffering.
The fundamental purpose that buffering is inserted is to accelerate the speed that signal transmits in circuit, shortens signal propagation delay.Signal delay be directly proportional with the resistance R of wire, and also the capacitor C with wire is directly proportional.And resistance and electric capacity are directly proportional with conductor length respectively, therefore, signal delay square is directly proportional with conductor length.That is to say, conductor length doubles, and signal delay increases by 4 times.So, half of signal delay when on two section leads of same length, the summation of signal delay only has this two section lead to connect together.Therefore, a long lead one is sliced into halves, middle with the impact damper connection, the signal delay of resulting new construction is likely shorter than the signal delay of original long lead.But impact damper itself also has delay, and need power consumption, so be not that impact damper is inserted The more the betterly.Crucial buffer length (Critical Buffer Length) is the short lead length that needs to insert buffering, and than this length, short wire does not need cushion insertions, and the wire insertion that surpasses this length is cushioned and just can acquire the shorter effect of delay.
According to document " P. Saxena; N. Menezes; P. Cocchini; and D. A. Kirkpatrick; " Repeater scaling and its impact on CAD; " IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 23, no. 4, pp. 451 – 463, Apr. 2004 " analysis, it is the buffering of inserting that 35% unit is arranged in the integrated circuit of 65 nanometers; this article thinks, below 70% unit will be arranged in the integrated circuit of several generations is the buffer cell inserted.The performance of these buffer elements to chip, power consumption, crowded property etc. all can produce adverse influence, but and list of references C. N. Sze, etl., Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on (Volume:26, Issue:7), 2007.Therefore, if can adjust the distance between element in the process of placement-and-routing, make conductor length be less than crucial buffer length as far as possible, just can reduce the insertion of buffer element.But a lot of placement-and-routings software has suitable shortcoming in this respect.
The main method that physical Design software is taked at present is first to carry out layout, is then connected up, and cushions insertion after both complete again.Place and route may mutually combine, but the buffering insertion is always carried out after both complete.The main target of placement-and-routing is that the wiring total length is the shortest, yet, when realizing this goal, the problem of usually buffering not being inserted is taken into account.A shortest placement-and-routing's result of total wiring, it might not be minimum needing to insert the line number cushioned.
We can illustrate the problems referred to above by a very simple placement-and-routing result.Suppose to have a fixing input end A and a fixing output terminal B, need to place an element C between the two, the three is on the same straight line.C has respectively line with A and B.Fig. 1 of Figure of description and Fig. 2 are two different layout result, and their line total length is identical, are all the shortest routes.But in Fig. 1, the A-C line is long, and in Fig. 2, two wire lengths of A-C and C-B are identical.Suppose that crucial buffer length is slightly larger than half of A-B wire length, need between the A-C of layout 1 so to insert buffering, and layout 2 does not need to insert buffering, as shown in Figure 3 and Figure 4.In this case, the layout of Fig. 4 just is better than the layout of Fig. 3, because the buffering of inserting in Fig. 4 is few.Conversely, as shown in Figure 5, Figure 6, suppose that crucial buffer length is slightly less than half of A-B, just have to so insert two bufferings in the layout of Fig. 6, now the layout of Fig. 5 is better than the layout of Fig. 6.
As can be seen here, different layout result has obvious difference to required buffering quantity.What existing placement-and-routing method was mainly considered is that the line total length is the shortest, through top analysis, shows, the shortest layout result of total length might not be the layout result of buffering minimum number.Modern buffering insertion algorithm normally just carries out after placement-and-routing completes, when cushioning insertion, layout result is definite, and the position of each element no longer changes, and has so just lost and has adjusted position of components to obtain the chance of buffering insertion number still less.Consider that in modern integrated circuits, the unit of 35%-70% is the buffer cell that placement-and-routing inserts afterwards, therefore, leave placement-and-routing's result of buffering optimization with between optimum placement-and-routing's result, having very large gap, thereby directly caused the overall performance of integrated circuit and the difference of manufacturing cost.
 
Summary of the invention
The present invention is directed to the prior art above shortcomings, a kind of layout method that buffering is inserted number that reduces is provided, by in layout process, the distance between element being carried out to balanced adjustment, contribute to significantly to reduce buffering and insert, reduce crowded property thereby reduce time delay.
The present invention is achieved through the following technical solutions:
A kind of layout method that reduces buffering insertion number comprises step:
S0, determine crucial buffer length and circuit meshwork list is carried out to initial layout;
S1, select a length to be greater than the line L1 of crucial buffer length, select the element be connected with line L1, judge in the line be connected with element whether at least comprise that a length is less than the line L2 of crucial buffer length;
If S2 judgment result is that, moving meter, to shorten the length of line L1, in mobile process, the length of line L2 and other lines of being connected with element likely increases, and when mobile, keeps the length of line L2 to be less than crucial buffer length;
If judgment result is that and not have, successively by the nearly peripheral cell be connected with element to selection far away, peripheral cell comprise the first peripheral cell be connected with element, the second peripheral cell be connected with the first peripheral cell ..., the n+1 peripheral cell be connected with the n peripheral cell, n is more than or equal to 1 integer, and judgement:
Whether at least comprise in the line be connected with the first peripheral cell that a length is less than the line L3 of crucial buffer length, if have, simultaneously moving meter and the first peripheral cell, to shorten line L1, in mobile process, the length of line L3 likely increases, in movement, need to keep line L3 length to be less than crucial buffer length, if do not have, select the second peripheral cell be connected with the first peripheral cell, and repeating the judgement in S2, so circulation, until do not find peripheral cell movably or chosen the peripheral cell at edge;
Whether the length that the line L1 after S2 is carried out in S3, judgement is less than crucial buffer length;
If S4 judgment result is that, be that the adjustment of line L1 finishes;
If the determination result is NO, select other elements that are connected with line L1 to carry out the step that S1 starts, if still can't make the length of line L1 be less than crucial buffer length, in line L1, insert the buffer element of minimum number, make line L1 be cushioned the separated every part of element and all be less than crucial buffer length;
S5, the line of selecting another length to be greater than crucial buffer length are carried out the step that S1 starts, until the length of all lines all is less than crucial buffer length.
Preferably, the element be moved or the quantity of peripheral cell are one or more.
Preferably, in the situation that a plurality of element or peripheral cell meet mobile condition, pay the utmost attention in step S2 existing structure is affected to minimum element or peripheral cell moves.
Preferably, in step S4, if other elements of selected movement or n peripheral cell can make some other wire lengths that are connected with other elements or n peripheral cell surpass crucial buffer length, select other mobile elements or n peripheral cell some other wire lengths to be surpassed to the summation minimum of crucial buffer length.
Preferably, also comprise and be chosen in some other lines that mobile rear length surpasses crucial buffer length, carry out the step that S1 starts, to shorten the length of some other lines.
Existing physical Design flow process is cushioned update after placement-and-routing completes again, and because position of components now can not be done movement again, therefore can't fully reduce the quantity of buffering.Although a large amount of optimization has been done by placement-and-routing itself, after inserting a large amount of buffer elements, the quality of placement-and-routing can be had a strong impact on.Compared with prior art, the present invention can be in the situation that do not increase the use that time delay reduces buffer element as far as possible, and can in layout, realize the optimization of circuit.
 
The accompanying drawing explanation
Shown in Fig. 1 and Fig. 2 is two kinds of different layouts of same circuits structure;
Shown in Fig. 3 and Fig. 4 be existing optimization method in the situation that crucial buffer length be slightly larger than AB length half, the layout after Fig. 1 and Fig. 2 optimize;
Shown in Fig. 5 and Fig. 6 be existing optimization method in the situation that crucial buffer length be slightly less than AB length half, the layout after Fig. 1 and Fig. 2 optimize;
Fig. 7 is that the present invention reduces the process flow diagram that buffering is inserted the layout method of number;
Shown in Fig. 8 to Figure 11 is that the present invention reduces the substep diagrammatic layout figure that buffering is inserted the layout method of number;
Shown in Figure 12 is the layout after the present invention optimizes Fig. 2;
Shown in Figure 13 is the planar circuit layout before optimizing;
Shown in Figure 14 is the circuit arrangement map after the present invention optimizes Figure 13.
 
Embodiment
Below with reference to accompanying drawing of the present invention; technical scheme in the embodiment of the present invention is carried out to clear, complete description and discussion; obviously; as described herein is only a part of example of the present invention; it is not whole examples; embodiment based in the present invention, the every other embodiment that those of ordinary skills obtain under the prerequisite of not making creative work, belong to protection scope of the present invention.
For the ease of the understanding to the embodiment of the present invention, take specific embodiment below in conjunction with accompanying drawing and be further explained as example, and each embodiment does not form the restriction to the embodiment of the present invention.
Please refer to Fig. 7, the present invention realizes by following steps:
1, determine crucial buffer length k.
2, select a layout method to carry out initial layout to the net table.What deserves to be explained is, step 1 and 2 is existing layout methods, immediately thereafter be to build Clock Tree and buffering is inserted, so the present invention is not repeated the content of step 1 and step 2 at this, and the value of k is also associated with actual demand, and the present invention does not do restriction at this.
3, the recurrence adjustment of position of components.Surpass the line L of k for each length, carry out the adjustment of following position:
S1, select a length to be greater than the line L1 of crucial buffer length, select the element be connected with line, judge in the line be connected with element whether comprise that at least one length is less than the line L2 of crucial buffer length;
If S2 judgment result is that, move described element, to shorten the length of described line L1, in mobile process, the length of described line L2 and other lines of being connected with described element likely increases, and when mobile, keeps the length of line L2 to be less than crucial buffer length;
If judgment result is that and not have, successively by the nearly peripheral cell be connected with described element to selection far away, described peripheral cell comprise the first peripheral cell be connected with described element, the second peripheral cell be connected with described the first peripheral cell ..., the n+1 peripheral cell be connected with the n peripheral cell, n is more than or equal to 1 integer, and judgement:
Whether at least comprise in the line be connected with the first peripheral cell that a length is less than the line L3 of crucial buffer length, if have, move described element and described the first peripheral cell simultaneously, to shorten described line L1, in mobile process, the length of described line L3 likely increases, in movement, need to keep line L3 length to be less than crucial buffer length, if do not have, select the second peripheral cell be connected with described the first peripheral cell, and repeat the judgement in S2, so circulation, until do not find peripheral cell movably or chosen the peripheral cell at edge,
The element be moved or the quantity of peripheral cell are one or more, in the situation that a plurality of element or peripheral cell meet mobile condition, pay the utmost attention in step S2 existing structure is affected to minimum element or peripheral cell moves.
Whether the length that the line L1 after S2 is carried out in S3, judgement is less than crucial buffer length;
If S4 judgment result is that, be that the adjustment of line L1 finishes;
If the determination result is NO, select other elements that are connected with line L1 to carry out the step that S1 starts, if still can't make the length of line L1 be less than crucial buffer length, in line L1, insert the buffer element of minimum number, make line L1 be cushioned the separated every part of element and all be less than crucial buffer length;
S5, the line of selecting another length to be greater than crucial buffer length are carried out the step that S1 starts, until the length of all lines all is less than crucial buffer length.
In step S4, other elements of selected movement or n peripheral cell can make some other wire lengths that are connected with other elements or n peripheral cell increase or surpass crucial buffer length, select other mobile elements or n peripheral cell some other wire lengths to be surpassed to the summation minimum of crucial buffer length.And then select these length to surpass some other lines of crucial buffer length, carry out the step that S1 starts.
In aforesaid operations, take adequate measures to guarantee not occur endless loop.
Understand for the ease of the technician, three concrete operational instances below be provided:
Embodiment mono-
As shown in Figure 8, suppose that the length of side of square equals crucial buffer length k, so, when wire length is less than the square length of side, does not need to insert buffering, otherwise need.In the figure, length is the line L between element A and element D over the line of k.
Operated according to method provided by the present invention, for the contraction in length L, in k, at first selected the element A be connected with line L, because the wire length of element A and element B is less than k, so element A can move.Element A is moved towards the direction of element D, but after mobile, can not make the distance between element A and element B surpass k, the results are shown in Figure 9 after mobile.Because the length of line L after mobile still is greater than k, therefore selected again the element D be connected with line L, because the wire length of element D and element C is less than k, so element D can move.Again element D is moved towards the direction of element A, the results are shown in Figure 10.Through moving for above-mentioned twice, the contraction in length of line L, but still be longer than k, therefore carry out again judgement, the first peripheral cell of element A, be to comprise on element B that a length is less than the line of k, therefore, element A and element B can move simultaneously, and what obtain the results are shown in Figure 11, wherein all wire lengths all are less than k, have reached our requirement.Existing layout method need to add two buffer elements between element A and element D, and the present invention has avoided adding buffer element at this.
Embodiment bis-
Please refer to Fig. 2 and Fig. 6, suppose the centre of element C in A-B in Fig. 2, crucial buffer length k equals element A to half of the distance of element B, that is to say, if do not do the position adjustment, prior art need to be in Fig. 2 each needs to insert a buffering between A-C and C-B, shown in Fig. 6.The method according to this invention, at first attempt shortening one section line, such as A-C, but because the length of B-C has reached crucial buffer length k, so element C can't move towards element A.Therefore insert a buffering in the middle of A-C.Then consider line B-C, its length has also surpassed k.But now element C is less than k to the distance of buffer element, therefore can move element C to the direction of element B, make the distance of C-B be less than k, the distance of element C and buffer element is not more than k simultaneously.Obtain thus Figure 12.This figure has only inserted a buffer element, and prior art needs two buffer elements.
It should be noted that, the buffer element inserted on line becomes the part of circuit, and it can be considered the element in circuit, identical with above-mentioned element A, element B etc.
Embodiment tri-
What above two embodiment considered is the simplest situation, and all point-blank, every line only connects two elements to all elements.In actual conditions, component placement is in plane or three-dimensional zone, and a line may connect more than two elements.For these situations, the principle of operation is also identical.Below with the example on a plane, be illustrated.
Please refer to Figure 13, in the figure of this initial layout wiring, four lines are arranged, article one connects (A, B, C, D), and second connects (D, E, F), and the 3rd connects (E, I, J), the 4th line (C, K, L).The length of every line is a plurality of line segment length additions that form this line and obtains.In element: A, B, K, I, J, F is the Inport And Outport Node that is positioned at the layout areas edge, irremovable.
Suppose line (A, B, C, D), the length that the length of (D, F, E) and (E, I, J) all surpasses k is greater than k, and the length of line (C, K, L) is less than k.Suppose that we start from line (D, F, E), we need to reduce to the length of this line below k, and therefore, can consideration be moved these three elements together to reduce wire length to.In the middle of these three elements, F is fixing Inport And Outport Node, can not move; E can not move to D and F direction, because this can increase the length of (E, I, J), and I, J is immovable.Consider that the direction towards E and F moves the position of D: D can move right, and does not increase the length of (A, B, C, D), reduced the length of line (D, E, F) after moving, but its length still is greater than k; If again D is moved down, will increase line (A, B, C, D) length, now this wire length has been greater than k, therefore, first C is moved right, to shorten (A, B, C, D) length, C is moved to the left until (C, K, L) length approach k till, suppose now (A, B, C, D) length also be less than k.Subsequent can moving down D, until till the length of (A, B, C, D) is slightly less than k.Suppose that now the length of (D, E, F) still is greater than k, because this line can not reduce its length by the position of the mobile element that it connects, therefore insert a buffering M at the E place, and adjust the position of E, make new line (D, F, M), (M, E) and (E, I, J) length all be less than k.Adjust result, the length of all lines all has been less than k.Placement-and-routing and buffering have been inserted.Figure after optimizing distribution is shown in Figure 14.
It should be noted that; provided by the present invention a kind of reduce buffering insert number layout method can with this area in arbitrarily existing placement-and-routing method, placement-and-routing's optimization method and Clock Tree generation method carry out combination, within the technical scheme of this combination belongs to protection scope of the present invention.
The above; be only the present invention's embodiment preferably, but protection scope of the present invention do not limit to therewith, anyly be familiar with in technical scope that those skilled in the art disclose in the present invention; the variation that can expect easily or replacement, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claim.

Claims (5)

1. one kind is reduced the layout method that buffering is inserted number, it is characterized in that, comprises step:
S0, determine crucial buffer length and circuit meshwork list is carried out to initial layout;
S1, select a length to be greater than the line L1 of crucial buffer length, select the element be connected with described line L1, judge in the line be connected with described element whether at least comprise that a length is less than the line L2 of crucial buffer length;
If S2 judgment result is that, move described element, to shorten the length of described line L1, in mobile process, the length of described line L2 and other lines of being connected with described element likely increases, and when mobile, keeps the length of line L2 to be less than crucial buffer length;
If judgment result is that and not have, successively by the nearly peripheral cell be connected with described element to selection far away, described peripheral cell comprise the first peripheral cell be connected with described element, the second peripheral cell be connected with described the first peripheral cell ..., the n+1 peripheral cell be connected with the n peripheral cell, n is more than or equal to 1 integer, and judgement:
Whether at least comprise in the line be connected with the first peripheral cell that a length is less than the line L3 of crucial buffer length, if have, move described element and described the first peripheral cell simultaneously, to shorten described line L1, in mobile process, the length of described line L3 likely increases, in movement, need to keep line L3 length to be less than crucial buffer length, if do not have, select the second peripheral cell be connected with described the first peripheral cell, and repeat the judgement in S2, so circulation, until do not find peripheral cell movably or chosen the peripheral cell at edge,
Whether the length that the described line L1 after S2 is carried out in S3, judgement is less than crucial buffer length;
If S4 judgment result is that, be that the adjustment of described line L1 finishes;
If the determination result is NO, select other elements that are connected with described line L1 to carry out the step that S1 starts, if still can't make the length of described line L1 be less than crucial buffer length, in described line L1, insert the buffer element of minimum number, make described line L1 be cushioned the separated every part of element and all be less than crucial buffer length;
S5, the line of selecting another length to be greater than crucial buffer length are carried out the step that S1 starts, until the length of all lines all is less than crucial buffer length.
2. a kind of layout method that buffering is inserted number that reduces according to claim 1, is characterized in that, the element be moved or the quantity of peripheral cell are one or more.
3. a kind of minimizing the according to claim 2 cushioned the layout method that inserts number, it is characterized in that, in the situation that a plurality of elements or peripheral cell meet mobile condition, pay the utmost attention in step S2 existing structure is affected to minimum element or peripheral cell moves.
4. a kind of minimizing the according to claim 1 cushioned the layout method that inserts number, it is characterized in that, in step S4, if other elements of selected movement or n peripheral cell can make some other wire lengths that are connected with described other elements or n peripheral cell surpass crucial buffer length, select mobile described other elements or n peripheral cell described some other wire lengths to be surpassed to the summation minimum of crucial buffer length.
5. a kind of minimizing the according to claim 4 cushioned the layout method that inserts number, it is characterized in that, also comprise and select described some other lines that surpass crucial buffer length in mobile rear length, carry out the step that S1 starts, to shorten the length of described some other lines.
CN201310290833.1A 2013-07-11 2013-07-11 A kind of layout method reducing buffering insertion number Active CN103425820B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201310290833.1A CN103425820B (en) 2013-07-11 2013-07-11 A kind of layout method reducing buffering insertion number

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310290833.1A CN103425820B (en) 2013-07-11 2013-07-11 A kind of layout method reducing buffering insertion number

Publications (2)

Publication Number Publication Date
CN103425820A true CN103425820A (en) 2013-12-04
CN103425820B CN103425820B (en) 2016-02-24

Family

ID=49650552

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310290833.1A Active CN103425820B (en) 2013-07-11 2013-07-11 A kind of layout method reducing buffering insertion number

Country Status (1)

Country Link
CN (1) CN103425820B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105404352A (en) * 2014-09-11 2016-03-16 北京华大九天软件有限公司 Method for inspecting bottleneck in clock tree synthesis result to improve synthesis quality

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1475945A (en) * 2003-07-04 2004-02-18 清华大学 Buffer programming method based on blank region redistribution
US6766499B1 (en) * 2001-04-05 2004-07-20 Lsi Logic Corporation Buffer cell insertion and electronic design automation
CN1547252A (en) * 2003-11-28 2004-11-17 清华大学 Integrated circuit layout plan and buffer plan integrated layout method
CN101241523A (en) * 2008-03-10 2008-08-13 清华大学 Full-chip interconnecting line power consumption optimum layout stage buffer planning method
US20130055188A1 (en) * 2011-08-24 2013-02-28 Renesas Electronics Corporation Semiconductor layout setting device, semiconductor layout setting method, and semiconductor layout setting program

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6766499B1 (en) * 2001-04-05 2004-07-20 Lsi Logic Corporation Buffer cell insertion and electronic design automation
CN1475945A (en) * 2003-07-04 2004-02-18 清华大学 Buffer programming method based on blank region redistribution
CN1547252A (en) * 2003-11-28 2004-11-17 清华大学 Integrated circuit layout plan and buffer plan integrated layout method
CN101241523A (en) * 2008-03-10 2008-08-13 清华大学 Full-chip interconnecting line power consumption optimum layout stage buffer planning method
US20130055188A1 (en) * 2011-08-24 2013-02-28 Renesas Electronics Corporation Semiconductor layout setting device, semiconductor layout setting method, and semiconductor layout setting program

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PRASHANT SAXENA 等: "Repeater Scaling and Its Impact on CAD", 《IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS》 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105404352A (en) * 2014-09-11 2016-03-16 北京华大九天软件有限公司 Method for inspecting bottleneck in clock tree synthesis result to improve synthesis quality
CN105404352B (en) * 2014-09-11 2018-05-11 北京华大九天软件有限公司 It is a kind of to check clock tree synthesis result bottleneck so as to the method for improving comprehensive quality

Also Published As

Publication number Publication date
CN103425820B (en) 2016-02-24

Similar Documents

Publication Publication Date Title
CN100414552C (en) Estimating jitter in a clock tree of a circuit and synthesizing a jitter-aware and skew-aware clock tree
US9817933B2 (en) Systems and methods for switching using hierarchical networks
US9552454B2 (en) Concurrent timing-driven topology construction and buffering for VLSI routing
US9503092B2 (en) Mixed-radix and/or mixed-mode switch matrix architecture and integrated circuit, and method of operating same
CN100440229C (en) Method of generating wiring routes with matching delay in the presence of process variation
CN103259526A (en) Method and device for constructing clock network
US11023377B2 (en) Application mapping on hardened network-on-chip (NoC) of field-programmable gate array (FPGA)
CN103080938A (en) Method and apparatus for simultaneous switching noise optimization
US7612599B2 (en) Semiconductor device
US20040196081A1 (en) Minimization of clock skew and clock phase delay in integrated circuits
JP5987720B2 (en) Binary decision graph processing system and method
CN103425820A (en) Layout method for reducing buffer inserting number
CN112949248A (en) Automatic wiring method and device for top-layer long and narrow channel of chip and storage medium
Wu et al. Timing driven track routing considering coupling capacitance
CN102907053B (en) Wavelength division network planning method and equipment
CN105302947A (en) Fan circle multi-fan-out path-based repeater insertion method
CN113128151B (en) Netlist partitioning method using multi-die structure FPGA layout result
CN104579963A (en) Method and device for optimizing routes of nodes
Marvasti et al. An analysis of hypermesh nocs in fpgas
Kohler et al. A SystemC TLM2 model of communication in wormhole switched Networks-On-Chip
CN117151015B (en) Integrated circuit layout wiring method, device and integrated circuit chip
Li et al. Noise-aware buffer planning for interconnect-driven floorplanning
CN116542209B (en) Layout optimization method and device for SOC (system on chip)
Hu et al. A fully polynomial-time approximation scheme for timing-constrained minimum cost layer assignment
US8769461B1 (en) Replicating a driver of a net in a circuit design

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant