CN104541375A - 具有减少泄露阱衬底结的mos晶体管 - Google Patents

具有减少泄露阱衬底结的mos晶体管 Download PDF

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CN104541375A
CN104541375A CN201380042425.2A CN201380042425A CN104541375A CN 104541375 A CN104541375 A CN 104541375A CN 201380042425 A CN201380042425 A CN 201380042425A CN 104541375 A CN104541375 A CN 104541375A
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T·J·伯德伦
A·查特吉
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Abstract

金属氧化物半导体(MOS)晶体管(340)包括具有顶侧半导体表面(106)的衬底(105)，顶侧半导体表面(106)掺杂有具有基线掺杂水平的第一掺杂物类型。阱(210)在掺杂有第二掺杂类型的半导体表面中形成。阱形成具有阱耗尽区域(215)的阱衬底结。倒掺杂区域(220)在掺杂有第一掺杂物类型的阱衬底结的下方并在峰值第一掺杂物浓度的位置处具有高出基线掺杂水平5-100倍之间的峰值第一掺杂物浓度，其中，在阱衬底结的两端具有零偏压时，倒掺杂区域的总剂量的至少90％在阱耗尽区域的底部的下方。栅极结构(341、342)在阱上。源极区域(344)和漏极区域(345)在栅极结构的相对侧上。

Description

具有减少泄露阱衬底结的MOS晶体管
技术领域
本发明涉及包括具有pn结的集成电路的半导体器件，其包括用于减少pn结泄露的掺杂布置。
背景技术
泄露电流已成为互补金属-氧化物半导体(CMOS)集成电路(IC)的待机功耗的重要贡献者，并且通常通过晶体管参数截止状态电流(Ioff)在晶体管电平处进行测量。当在施加漏极到源极一定的电压(Vdd)的情况下，所施加的栅极电压是零时，Ioff是漏极电流。
Ioff受器件的阈值电压(Vt)、沟道物理尺寸、沟道/表面掺杂分布、漏极/源极结深度、栅极电介质厚度和Vdd的影响。已知长沟道器件中的Ioff受控于来自漏极阱结和阱衬底结的反向偏压泄漏。短沟道晶体管通常需要较低的功率供给电平，以减小它们的内部电场和功率消耗。使用较低的功率供给电平迫使Vt减小，这能够引起Ioff的显著增加。因此，如果能够减少反向偏压阱衬底泄漏，则能够减少IC的待机功率。
发明内容
所公开的实施例包括用于形成金属氧化物半导体(MOS)晶体管的方法和由此形成的IC，包括至少一种用于增强(增加)阱衬底结的耗尽区域(阱耗尽区域)的底部下方的衬底掺杂的高能量注入物，以在此耗尽区域的底部的一个扩散长度内添加倒掺杂区域。增加的衬底掺杂水平通过减少阱耗尽区域下方的少数载流子掺杂水平来显著减少结泄漏。
至于p衬底中的n阱，已经发现在n阱耗尽区域的底部与超过其下方的一个扩散长度之间的一个或更多个高能量硼注入物减少n阱到周围的p型衬底结泄漏。或者，如果衬底材料是n型，并且阱是p阱，那么一个或更多个n型注入物(P、As、或Sb)能够位于p阱的下方，以减少p阱到周围的n型衬底结泄漏。
所公开的倒掺杂区域被定位在适当的深度范围内，使得他们足够深，以不显著地改变阱内的器件的电气特性，电气特征包括阱中的MOS器件的阈值电压(Vt)、阱衬底击穿电压和阱衬底电容。该定位也足够近(一个扩散长度内)，以显著地增加靠近阱衬底结的底部的衬底掺杂的掺杂水平，从而减小其中的少数载流子掺杂水平，减少阱衬底结泄漏。
所公开的阱衬底结下方的倒掺杂区域通常在峰值掺杂浓度的位置(即深度)处具有高出由周围衬底提供的基线掺杂水平5到100倍的峰值掺杂物浓度。例如，p衬底具有1×1015cm-3的硼掺杂水平，阱衬底结下方的倒掺杂区域提供从5×1015cm-3到1×1017cm-3的峰值硼浓度。另外，在阱衬底结的两端具有零偏压的情况下，倒掺杂区域的总(整体)剂量的至少90％在阱耗尽区域的底部的下方。注入时，通常>95％高能量注入物剂量(例如，>99％)在阱耗尽区域的底部的下方，而在完成的IC中，由于注入后(post-implant)的扩散，百分数可降到至少90％。
一个公开的实施例是一种包括具有半导体表面的衬底的MOS晶体管，该半导体表面掺杂有具有基线掺杂水平的第一掺杂物类型。阱在掺杂有第二掺杂类型的半导体表面中形成。阱形成具有阱耗尽区域的阱衬底结。倒掺杂区域在掺杂有第一掺杂物类型的阱衬底结的下方并在峰值第一掺杂物浓度的位置处具有高出基线掺杂水平5到100倍之间的峰值第一掺杂物浓度，其中，在阱衬底结的两端具有零偏压的情况下，倒掺杂区域的总剂量的至少90％在阱耗尽区域的底部的下方。栅极结构在阱上。源极区域和漏极区域在栅极结构的相对侧上。
附图说明
图1是根据一个示例性实施例的示出示例性方法的步骤的流程图，该示例性方法包括用于形成MOS晶体管的至少一种高能量注入物，MOS晶体管包括具有用于减少泄漏的阱耗尽区域下方的倒掺杂区域的阱衬底结。
图2A示出形成倒掺杂区域的两种示例性的高能量注入物条件，倒掺杂区域增加了在所示的n阱下方的衬底中的p型掺杂，而图2B示出了公开的倒掺杂区域的掺杂分布，其通过使用三种不同的高能量注入物条件增加n阱下方的p衬底掺杂而被形成。基线条件被示出为“基线p衬底掺杂”，其中没有添加任何公开的高能量注入物。
图3是根据一个示例性实施例的IC的简化的横截面图，其示出了在衬底的顶侧半导体表面中的CMOS逆变器，其中PMOS晶体管在n阱中，n阱具有在n阱下方的倒掺杂区域，以提供公开的减少泄漏的阱衬底二极管。
图4提供显示在有和没有如上相对于图2A所述的示例性泄露减少高能量注入物的情况下作为温度倒数(1/kT)的函数的n阱反向泄漏电流(I)的对数的数据。相对于不包括任何公开的高能量注入物的基线n阱二极管，示出了减少公开的n阱二极管的结泄露的5到8倍。
具体实施方式
图1是根据一个示例性实施例的示出示例性方法100的步骤的流程图，示例性方法100包括用于增强(增加)阱衬底结的耗尽区域下方的衬底掺杂的至少一种高能量注入物，以将倒掺杂区域添加至结的下方，用于形成具有减少泄露阱衬底结的MOS晶体管。通过增加阱耗尽区域的底部和从阱耗尽区域出来的一个扩散长度之间的衬底表面掺杂，来减少阱衬底结泄漏，从而减少了少数载流子掺杂水平，而不显著地改变阱内器件的电气特性(包括阱内MOS器件的Vt和结电容)。阱衬底结的一个扩散长度的典型值可以是5-20μm。
步骤101包括在半导体表面形成掺杂有第二掺杂类型的阱，半导体表面掺杂有具有基线掺杂水平的第一掺杂物类型，其中阱形成阱衬底结。阱能够是n阱，并且半导体表面为p表面(例如大块(bulk)p衬底、或p+衬底上的p外延层(p-epi layer))。阱能够是p阱并且半导体表面为n表面(例如大块n衬底、或n+衬底上的n外延层)。阱的形成能够包括常规阱的形成，其使用至少一种离子注入物然后进行退火/驱动。衬底能够包括硅、硅-锗、或提供半导体表面的其他衬底材料。
步骤102包括离子注入一定剂量和能量的第一掺杂物类型(与半导体衬底表面一样的类型)，以形成阱衬底结的阱耗尽区域下方的倒掺杂区域，倒掺杂区域具有在峰值第一掺杂物浓度的位置处高出基线掺杂水平5到100倍的峰值第一掺杂物浓度。选择注入物的能量，使得离子注入后，在阱衬底结的两端具有零偏压的情况下，倒掺杂区域的总剂量的至少90％在阱耗尽区域的底部的下方，并且在一个实施例中，注入剂量的至少80％也在离阱耗尽区域的底部两(2)μm内。
如下所述，图2A示出了半导体衬底表面提供的示例性掺杂物分布以及基线掺杂分布。在一个实施例中，注入为覆盖(blanket)离子注入，使得不需要添加掩膜层。在另一个实施例中，一组一个或更多个注入物可被掩蔽，以将产生的泄漏减少施加到所选择的阱，并且掩蔽该高能量注入物，以在其他阱和区域中(例如，在集成电感器下)维持高衬底电阻率。
至于p衬底表面中的n阱，第一掺杂类型通常是硼，并且注入物剂量通常为2×1012cm-2和3×1013cm-2之间，并且能量通常是从400keV到1.8MeV，但是假如剂量保持在阱耗尽区域的底部的一个扩散长度内，则能量能够处于更高的能量。离子注入能够包括具有不同注入物能量的至少两种不同的注入物，例如下文相对于图2B所描述的三个不同的注入物。
步骤103包括在阱上形成栅极结构，其包括栅极电介质上的栅极电极。步骤104包括在栅极结构的相对侧上形成源极区域和漏极区域。尽管相对于方法100没有描述，但公开的方法通常包括常规的CMOS工艺，常规的CMOS工艺包括形成隔离(例如，浅沟槽隔离)、轻度掺杂漏极、间隔件、各种沟道注入物、多级金属化和钝化工艺。
图2A示出了形成倒掺杂区域的两个示例高能量注入物条件的仿真，倒掺杂区域显著增地加了n阱衬底耗尽区域215下方的衬底中的p型掺杂。示例性注入物条件如下所示：在750keV处4×1012cm-2的11B+剂量和在750keV处1×1013cm-2的11B+剂量。
基线条件示为“基线p衬底掺杂”，其中不添加公开的高能量注入物。所示的、作为深度的函数的基线p衬底掺杂分布不是恒定的，这是由于添加了用于改善n阱与n阱之间隔离的任选的覆盖硼注入物。用于硼高能量注入物的每一个的峰值掺杂的位置由注入物能量(和衬底的制动能力)设定，使得注入的分布最小程度地侵蚀到n阱210和n阱衬底耗尽区域215。倒掺杂区域220在n阱衬底耗尽区域215的下方并且具有离器件的表面约1.5μm的峰值掺杂物浓度(对于4×1012cm-2剂量来说，约为1×1017cm-3且对于1×1013cm-2剂量来说，约为3×1017cm-3)，其比在峰值掺杂物浓度(在离该表面约1.5μm处约为4×1015cm-3)的深度处的基线p衬底掺杂水平之上高一个数量级。能够看到基本上所有的倒掺杂区域220位于阱耗尽区域215的底部和离阱耗尽区域215的底部2微米之间。
能够设定注入物剂量来减小约束条件内的泄漏，该约束条件具有如下能力，a)充分地退火消除从高能量注入物至晶体的注入损伤和b)防止由从高能量注入物进入阱耗尽区域的掺杂物的侵蚀引起的耗尽区域电场的增加。多个(附加)高能量注入物可以与不同的剂量和能量组合一起使用，如下文相对于图2B所描述的，以鉴于另一些设计约束条件(例如，阱击穿电压、阱电容、深衬底电阻率)实现增加的泄漏抑制。
公开的倒掺杂区域可与用于CMOS闩锁抑制和阱与阱之间隔离的常规深注入物形成对比。公开的倒掺杂区域涉及不同的设计目标并且随后用于实现减少泄漏的阱设计和掺杂分布，这抑制阱耗尽区域的扩散长度内的少数载流子以减少结泄漏。与适合于阱与阱之间泄漏减少的埋层和掺杂区域相比，用于减少泄漏的注入的分布处于较低的浓度。图2B示出了公开的倒掺杂区域的掺杂分布，其使用三个不同的高能量注入物条件增加n阱下方的p衬底掺杂来形成。如图2A所示，基线条件被示为“基线p衬底掺杂”，其中没有添加任何公开的高能量注入物。
图3是根据一个示例实施例的IC 300的简化的横截面图，其示出了衬底105的顶侧半导体表面106中的CMOS逆变器330，其中PMOS晶体管340在具有倒掺杂区域220的n阱210中，倒掺杂区域220在所示的n阱衬底耗尽区域215的底部和一个扩散长度306之间，以提供公开的减少泄露阱衬底二极管。CMOS逆变器330包括NMOS晶体管320和PMOS晶体管340(未示出NMOS晶体管320和PMOS晶体管340之间的耦合)。衬底105能够是p衬底或p+衬底上的p外延层。电介质隔离被示出为沟槽隔离132。
尽管顶侧半导体表面106在图3中被描述为p型，但是在另一个实施例中，顶侧半导体表面106能够是n型，阱是p阱，并且具有公开的减少泄漏衬底二极管的MOS晶体管能够是n沟道MOS晶体管。此外，尽管未示出，但是IC 300通常包括大量的MOS晶体管和另一些电路元件，例如电容器、电阻器、电容器、二极管等。此外，虽然没有示出，但是IC 300包括功能电路，所述功能电路是实现和执行IC 300所需功能的电路，例如数字IC(例如，数字信号处理器)的功能电路或模拟IC(例如，放大器或功率转换器)的功能电路。IC 300提供的功能电路的性能可以变化，例如从简单的器件变化到复杂的器件。包含在功能电路内的特定功能对公开的实施例来说是不重要的。
尽管只示出了一个n阱210，但所公开的IC通常包括多个n阱210。倒掺杂区域220被示出为覆盖掺杂区域。然而，在另一些实施例中，倒掺杂区域220能够是图案化的区域，使得多个n阱的一部分或IC上的另一些区域不包括倒掺杂区域220，例如用于集成电感器。
PMOS晶体管340包括栅极电极341、栅极电介质342、侧壁间隔件347、轻度掺杂漏极343、源极344和漏极345，并且在源极344、漏极345、以及对于栅极电极341包括多晶硅的情况下的栅极电极341上具有硅化物层319。NMOS晶体管320包括栅极电极321、栅极电介质322、侧壁间隔件347、轻度掺杂漏极323、源极324和漏极325，并且在源极324、漏极325、以及对于栅极电极321包括多晶硅的情况下的栅极电极321上具有硅化物层319。
示例
通过以下具体示例对所公开的实施例作进一步说明，但不应当以任何方式被解释为限定本公开的范围或内容。
执行计算机辅助设计技术(TCAD)仿真，以仿真具有公开的附加高能量注入物的n阱二极管，附加高能量注入物将掺杂物定位在n阱耗尽区域的底部下方的半导体表面中，以相比于不包括任何公开的高能注入物的控制(定义为“基线”)，演示了反向泄露电流的减少。图4提供显示在有和没有上述相对于图2A所述的示例泄露减少高能量注入物的情况下作为温度倒数(1/kT)的函数的n阱反向泄漏电流(I)的对数的数据。使用的偏压条件为n阱+10％的额定Vdd；在这种情况下，则是3.6V(反向偏压)。与不包括任何公开的高能量注入物的基线n阱二极管相比，示出公开的n阱二极管的结泄露减少5-8倍。
公开的实施例的优点包括：不需要附加的掩模和相关的附加成本。覆盖高能量注入物能够被添加到现有工艺流程中而不明显改变另一些器件的性能。如图4所证明的，能够减少待机泄露高达一个数量级，这样能够减少用于公开的IC的IC待机功率。
所公开的实施例能够被集成到各种组件流程中，以形成各种不同的半导体集成电路(IC)器件和相关产品。该组件能够包括单个半导体管芯或多个半导体管芯，例如包括多个堆叠的半导体管芯的PoP结构。可使用各种封装衬底。半导体管芯可包括其中的各种元件和/或其上的各种层，包括阻挡层、电介质层、器件结构、有源元件和无源元件(包括源极区域、漏极区域、位线、基极、射极、集电极、导线、导电通路等)。此外，半导体管芯(包括双极型、CMOS、BiCMOS和MEMS)能够由多种工艺形成。
本公开涉及的本领域技术人员将认识到许多其他实施例和实施例的变体也可能在本要求保护的发明的范围内，并可以对所描述的实施例作进一步的添加、删除、替代和修改，而不脱离本要求保护的发明的范围。

Claims (19)

1.一种金属氧化物半导体晶体管，即MOS晶体管，包括：
衬底，其具有半导体表面，所述半导体表面掺杂有具有基线掺杂水平的第一掺杂物类型；
阱，其在掺杂有第二掺杂类型的所述半导体表面中形成，所述阱形成具有阱耗尽区域的阱衬底结；
倒掺杂区域，其在掺杂有所述第一掺杂物类型的所述阱衬底结的下方并在峰值第一掺杂物浓度的位置处具有高出所述基线掺杂水平5到100倍之间的峰值第一掺杂物浓度，其中，在所述阱衬底结的两端具有零偏压时，所述倒掺杂区域的总剂量的至少90％在所述阱耗尽区域的底部的下方；
栅极结构，其在所述阱上，以及
源极区域和漏极区域，所述源极区域和漏极区域在所述栅极结构的相对侧上。
2.根据权利要求1所述的MOS晶体管，其中，所述阱是n阱，并且所述半导体表面是p表面。
3.根据权利要求1所述的MOS晶体管，其中，所述阱是p阱并且所述半导体表面是n表面。
4.根据权利要求1所述的MOS晶体管，其中，所述倒掺杂区域包括至少两个峰值，所述两个峰值包括所述峰值第一掺杂物浓度和另一个峰值。
5.根据权利要求1所述的MOS晶体管，其中，在所述阱衬底结的两端具有3伏特的反向偏压时，所述倒掺杂区域的总剂量的至少90％在所述阱耗尽区域的底部和所述阱耗尽区域的所述底部的下方的一个扩散长度之间。
6.一种集成电路，即IC，包括：
衬底，其具有半导体表面，所述半导体表面掺杂有具有基线掺杂水平的第一掺杂物类型；
多个阱，所述多个阱在掺杂有第二掺杂类型的所述半导体表面中形成，每个所述阱形成具有阱耗尽区域的阱衬底结；
多个p沟道或n沟道金属氧化物半导体晶体管，即多个p沟道或n沟道MOS晶体管，所述多个p沟道或n沟道金属氧化物半导体晶体管在所述多个阱中形成，并包括：
栅极结构，其在所述多个阱上；
源极区域和漏极区域，所述源极区域和漏极区域在所述栅极结构的相对侧上，以及
倒掺杂区域，其在掺杂有所述第一掺杂物类型的所述阱衬底结的下方并在峰值第一掺杂物浓度的位置处具有高出所述基线掺杂水平5到100倍之间的峰值所述第一掺杂物浓度，其中，在所述阱衬底结的两端具有零偏压时，所述倒掺杂区域的总剂量的至少90％在所述阱耗尽区域的底部的下方。
7.根据权利要求6所述的IC，其中，所述IC为互补MOS IC，即CMOS IC，其包括形成在所述多个阱中的所述多个p沟道MOS晶体管，还包括形成在所述半导体表面中的多个n沟道MOS晶体管。
8.根据权利要求6所述的IC，其中，所述多个阱是n阱，并且其中，所述多个p沟道或n沟道MOS晶体管是p沟道MOS晶体管。
9.根据权利要求6所述的IC，其中，所述多个阱是p阱，并且其中，所述多个p沟道或n沟道MOS晶体管是n沟道MOS晶体管。
10.根据权利要求6所述的IC，其中，所述倒掺杂区域是覆盖掺杂区域。
11.根据权利要求8所述的IC，其中，所述倒掺杂区域是图案化区域，并且其中，所述多个n阱的一部分不包括所述倒掺杂区域。
12.根据权利要求6所述的IC，其中，在所述阱衬底结的两端具有3伏特的反向偏压时，所述倒掺杂区域的总剂量的至少90％在所述阱耗尽区域的所述底部和所述阱耗尽区域的所述底部的下方的一个扩散长度之间。
13.一种形成金属氧化物半导体晶体管即MOS晶体管的方法，包括：
在掺杂有具有基线掺杂水平的第一掺杂物类型的半导体表面中形成掺杂有第二掺杂类型的阱，所述阱形成具有阱耗尽区域的阱衬底结；
离子注入一定剂量和能量的所述第一掺杂物类型以形成所述阱衬底结的下方的倒掺杂区域，所述倒掺杂区域在峰值第一掺杂物浓度的位置处具有高出所述基线掺杂水平5到100倍之间的所述峰值第一掺杂物浓度，其中，在所述阱衬底结的两端具有零偏压时，所述倒掺杂区域的总剂量的至少90％在所述阱耗尽区域的底部的下方；
在所述阱上形成栅极结构，以及
在所述栅极结构的相对侧上形成源极区域和漏极区域。
14.根据权利要求13所述的方法，其中，在所述阱衬底结的两端具有3伏特的反向偏压时，所述倒掺杂区域的总剂量的至少90％在所述阱耗尽区域的所述底部和所述阱耗尽区域的所述底部的下方的一个扩散长度之间。
15.根据权利要求13所述的方法，其中，所述第一掺杂物类型是硼，所述阱是n阱，所述半导体表面是p表面，并且所述剂量是2.0×1012cm-2到3×1013cm-2，并且其中，所述能量是从400keV到1.8MeV。
16.根据权利要求13所述的方法，其中，所述能量包括至少两种不同的能量。
17.根据权利要求13所述的方法，其中，所述阱包括多个n阱，并且所述方法包括形成互补MOS集成电路，即互补CMOS IC的方法，所述互补MOS集成电路包括在所述多个n阱外部的多个p沟道MOS晶体管和在所述多个n阱内形成的多个p沟道MOS晶体管。
18.根据权利要求17所述的方法，其中，所述倒掺杂区域是覆盖掺杂区域。
19.根据权利要求17所述的方法，其中，所述倒掺杂区域是图案化区域，并且其中，所述多个n阱的一部分不包括所述倒掺杂区域。
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Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6513450B2 (ja) * 2015-03-26 2019-05-15 三重富士通セミコンダクター株式会社 半導体装置
US9391111B1 (en) 2015-08-07 2016-07-12 Omnivision Technologies, Inc. Stacked integrated circuit system with thinned intermediate semiconductor die
DE102016115286A1 (de) 2016-08-17 2018-02-22 Infineon Technologies Ag Integrierte Schaltung mit Verstärker-MOSFET
JP2021044315A (ja) 2019-09-09 2021-03-18 キオクシア株式会社 不揮発性半導体記憶装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101447498A (zh) * 2007-11-30 2009-06-03 东部高科股份有限公司 静电放电保护器件及其制造方法
CN101452886A (zh) * 2007-12-07 2009-06-10 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
CN102194869A (zh) * 2010-03-16 2011-09-21 北京大学 一种抗辐照性能增强的超陡倒掺杂mos器件
CN102365749A (zh) * 2009-03-27 2012-02-29 国家半导体公司 使用空阱及满阱来组态及制造的半导体结构

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5622880A (en) * 1994-08-18 1997-04-22 Sun Microsystems, Inc. Method of making a low power, high performance junction transistor
AU6951298A (en) * 1997-04-04 1998-10-30 University Of Florida Method for testing and diagnosing mos transistors
KR19990017331A (ko) * 1997-08-22 1999-03-15 윤종용 바이씨모스 소자의 제조방법
US6310366B1 (en) * 1999-06-16 2001-10-30 Micron Technology, Inc. Retrograde well structure for a CMOS imager
KR100322889B1 (ko) * 1999-12-30 2002-02-09 박종섭 반도체장치의 제조방법
US7189997B2 (en) * 2001-03-27 2007-03-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
KR100811438B1 (ko) * 2001-12-29 2008-03-07 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US6667205B2 (en) 2002-04-19 2003-12-23 International Business Machines Machines Corporation Method of forming retrograde n-well and p-well
KR100486609B1 (ko) * 2002-12-30 2005-05-03 주식회사 하이닉스반도체 이중 도핑구조의 초박형 에피채널 피모스트랜지스터 및그의 제조 방법
US7268049B2 (en) * 2004-09-30 2007-09-11 International Business Machines Corporation Structure and method for manufacturing MOSFET with super-steep retrograded island
US20080099852A1 (en) 2006-10-31 2008-05-01 Juergen Faul Integrated semiconductor device and method of manufacturing an integrated semiconductor device
JP2012114274A (ja) 2010-11-25 2012-06-14 Elpida Memory Inc 半導体装置及びその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101447498A (zh) * 2007-11-30 2009-06-03 东部高科股份有限公司 静电放电保护器件及其制造方法
CN101452886A (zh) * 2007-12-07 2009-06-10 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
CN102365749A (zh) * 2009-03-27 2012-02-29 国家半导体公司 使用空阱及满阱来组态及制造的半导体结构
CN102194869A (zh) * 2010-03-16 2011-09-21 北京大学 一种抗辐照性能增强的超陡倒掺杂mos器件

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