CN104538370A - 一种基于预留槽塑封技术的pop封装结构及其制备方法 - Google Patents

一种基于预留槽塑封技术的pop封装结构及其制备方法 Download PDF

Info

Publication number
CN104538370A
CN104538370A CN201410843485.0A CN201410843485A CN104538370A CN 104538370 A CN104538370 A CN 104538370A CN 201410843485 A CN201410843485 A CN 201410843485A CN 104538370 A CN104538370 A CN 104538370A
Authority
CN
China
Prior art keywords
encapsulating structure
tin cream
plastic
packaging body
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410843485.0A
Other languages
English (en)
Inventor
谌世广
梁天胜
刘卫东
王虎
李涛涛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huatian Technology Xian Co Ltd
Original Assignee
Huatian Technology Xian Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huatian Technology Xian Co Ltd filed Critical Huatian Technology Xian Co Ltd
Priority to CN201410843485.0A priority Critical patent/CN104538370A/zh
Publication of CN104538370A publication Critical patent/CN104538370A/zh
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

本发明公开了一种基于预留槽塑封技术的POP封装结构及其制备方法,所述封装结构主要包括有基板、焊盘、凸点、芯片、塑封锡槽、塑封体、锡膏柱;所述塑封体上有塑封锡槽,塑封锡槽底部裸露有焊盘,塑封锡槽内部有锡膏柱,锡膏柱下端与焊盘连接。所述制备方法:基板上倒装上芯,塑封并制作塑封锡槽,塑封锡槽内印刷锡膏柱。该发明不需要完成封装后进行开孔过程;而且锡膏印刷,工艺简单。

Description

一种基于预留槽塑封技术的POP封装结构及其制备方法
技术领域
本发明涉及半导体封装技术领域,具体是一种基于预留槽塑封技术的POP封装结构及其制备方法。
背景技术
当前半导体封装发展的趋势是越来越多的向高频、多芯片模块(MCM),系统集成(SiP)封装,堆叠封装(PiP,PoP)发展。
三维堆叠封装可以在更小的空间内集成更多的半导体芯片,采用三维堆叠封装的产品拥有更高的性能、更高的可靠性,以及更低的价格。目前,采用三维堆叠封装的产品,例如存储器,能实现更大的存储量,并且已经实现工业化生产。
目前pop制备技术有如下挑战:
(1)上封装体与下封装体互连方式;
(2)高温焊接翘曲控制;
(3)封装厚度控制。
优点:工艺成熟;
缺点:封装后需在封装体进行开孔;工序复杂。
发明内容
对于上述现有技术存在的问题,本发明公开了一种基于预留槽塑封技术的POP封装结构及其制备方法,其不需要完成封装后进行开孔过程;而且锡膏印刷,工艺简单。
一种基于预留槽塑封技术的POP封装结构,主要包括有基板、焊盘、凸点、芯片、塑封锡槽、塑封体、锡膏柱;所述基板通过焊盘、凸点连接芯片,所述塑封体包围芯片、焊盘、凸点、锡膏柱和基板的上表面,塑封体上有塑封锡槽,塑封锡槽底部裸露有焊盘,塑封锡槽内部有锡膏柱,锡膏柱下端与焊盘连接。
所述锡膏柱上端有锡膏球。
所述POP封装结构还连接有上封装体,所述上封装体主要包括有上封装体芯片、上封装体凸点、填充胶和上封装体基板;上封装体基板通过焊盘、上封装体凸点与上封装体芯片连接,填充胶填充四者连接部分;所述POP封装结构的锡膏柱与上封装体基板的下表面连接。
所述POP封装结构的锡膏柱上的锡膏球与上封装体基板的下表面连接。
一种基于预留槽塑封技术的POP封装结构的制备方法,其按照以下具体步骤进行:
步骤一:基板上倒装上芯有芯片;
步骤二:塑封体包围芯片、焊盘、凸点、锡膏柱和基板的上表面,塑封体上制作有塑封锡槽,塑封锡槽底部裸露出焊盘;
步骤三:在塑封锡槽内锡膏印刷和回流,形成锡膏柱,最终形成所述POP封装结构;
步骤四:上封装体与POP封装结构连接,POP封装结构的锡膏柱与上封装体基板的下表面连接,形成堆叠封装结构。
所述步骤三的锡膏柱上端还可以制作锡膏球;
所述步骤四可以替换为:上封装体与POP封装结构连接,所述POP封装结构的锡膏柱上的锡膏球与上封装体基板的下表面连接,形成堆叠封装结构。
附图说明
图1为倒装上芯完成的产品图;
图2为用特殊模具制作的塑封图;
图3为锡膏印刷和回流图;
图4为上层产品贴装和回流图。
图中,1为基板,2为焊盘,3为凸点,4为芯片,5为塑封锡槽,6为塑封体,7为锡膏柱,8为锡膏球,9为上封装体芯片,10为上封装体凸点,11为填充胶,12为上封装体基板。
具体实施方式
下面根据附图对该发明做一详细描述。
如图4所示,一种基于预留槽塑封技术的POP封装结构,主要包括有基板1、焊盘2、凸点3、芯片4、塑封锡槽5、塑封体6、锡膏柱7;所述基板1通过焊盘2、凸点3连接芯片4,所述塑封体6包围芯片4、焊盘2、凸点3、锡膏柱7和基板1的上表面,塑封体6上有塑封锡槽5,塑封锡槽5底部裸露有焊盘2,塑封锡槽5内部有锡膏柱7,锡膏柱7下端与焊盘2连接。
所述锡膏柱7上端有锡膏球8。
所述POP封装结构还连接有上封装体,所述上封装体主要包括有上封装体芯片9、上封装体凸点10、填充胶11和上封装体基板12;上封装体基板12通过焊盘、上封装体凸点10与上封装体芯片9连接,填充胶11填充四者连接部分;所述POP封装结构的锡膏柱7与上封装体基板12的下表面连接。
所述POP封装结构的锡膏柱7上的锡膏球8与上封装体基板12的下表面连接。
一种基于预留槽塑封技术的POP封装结构的制备方法,其按照以下具体步骤进行:
步骤一:基板1上倒装上芯有芯片4,如图1所示;
步骤二:塑封体6包围芯片4、焊盘2、凸点3、锡膏柱7和基板1的上表面,塑封体6上制作有塑封锡槽5,塑封锡槽5底部裸露出焊盘2,如图2所示;
步骤三:在塑封锡槽5内锡膏印刷和回流,形成锡膏柱7,最终形成所述POP封装结构,如图3所示;
步骤四:上封装体与POP封装结构连接,POP封装结构的锡膏柱7与上封装体基板12的下表面连接,形成堆叠封装结构,如图4所示。
所述步骤三的锡膏柱7上端还可以制作锡膏球8;
所述步骤四可以替换为:上封装体与POP封装结构连接,所述POP封装结构的锡膏柱7上的锡膏球8与上封装体基板12的下表面连接,形成堆叠封装结构。

Claims (8)

1.一种基于预留槽塑封技术的POP封装结构,其特征在于,所述封装结构主要包括有基板(1)、焊盘(2)、凸点(3)、芯片(4)、塑封锡槽(5)、塑封体(6)、锡膏柱(7);所述基板(1)通过焊盘(2)、凸点(3)连接芯片(4),所述塑封体(6)包围芯片(4)、焊盘(2)、凸点(3)、锡膏柱(7)和基板(1)的上表面,塑封体(6)上有塑封锡槽(5),塑封锡槽(5)底部裸露有焊盘(2),塑封锡槽(5)内部有锡膏柱(7),锡膏柱(7)下端与焊盘(2)连接。
2.根据权利要求1所述的一种基于预留槽塑封技术的POP封装结构,其特征在于,所述锡膏柱(7)上端有锡膏球(8)。
3.根据权利要求1所述的一种基于预留槽塑封技术的POP封装结构,其特征在于,所述POP封装结构还连接有上封装体,所述上封装体主要包括有上封装体芯片(9)、上封装体凸点(10)、填充胶(11)和上封装体基板(12);上封装体基板(12)通过焊盘、上封装体凸点(10)与上封装体芯片(9)连接,填充胶(11)填充四者连接部分;所述POP封装结构的锡膏柱(7)与上封装体基板(12)的下表面连接。
4.根据权利要求2或者3所述的一种基于预留槽塑封技术的POP封装结构,其特征在于,所述POP封装结构的锡膏柱(7)上的锡膏球(8)与上封装体基板(12)的下表面连接。
5.一种基于预留槽塑封技术的POP封装结构的制备方法,其特征在于,其按照以下具体步骤进行:
步骤一:基板(1)上倒装上芯有芯片(4);
步骤二:塑封体(6)包围芯片(4)、焊盘(2)、凸点(3)、锡膏柱(7)和基板(1)的上表面,塑封体(6)上制作有塑封锡槽(5),塑封锡槽(5)底部裸露出焊盘(2);
步骤三:在塑封锡槽(5)内锡膏印刷和回流,形成锡膏柱(7),最终形成所述POP封装结构。
6.根据权利要求5所述的一种基于预留槽塑封技术的POP封装结构的制备方法,其特征在于,所述步骤三的锡膏柱(7)上端制作锡膏球(8)。
7.根据权利要求5所述的一种基于预留槽塑封技术的POP封装结构的制备方法,其特征在于,所述步骤三形成的POP封装结构与上封装体连接,POP封装结构的锡膏柱(7)与上封装体基板(12)的下表面连接,形成堆叠封装结构。
8.根据权利要求7所述的一种基于预留槽塑封技术的POP封装结构的制备方法,其特征在于,所述POP封装结构的锡膏柱(7)上的锡膏球(8)与上封装体基板(12)的下表面连接,形成堆叠封装结构。
CN201410843485.0A 2014-12-30 2014-12-30 一种基于预留槽塑封技术的pop封装结构及其制备方法 Pending CN104538370A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410843485.0A CN104538370A (zh) 2014-12-30 2014-12-30 一种基于预留槽塑封技术的pop封装结构及其制备方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410843485.0A CN104538370A (zh) 2014-12-30 2014-12-30 一种基于预留槽塑封技术的pop封装结构及其制备方法

Publications (1)

Publication Number Publication Date
CN104538370A true CN104538370A (zh) 2015-04-22

Family

ID=52853873

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410843485.0A Pending CN104538370A (zh) 2014-12-30 2014-12-30 一种基于预留槽塑封技术的pop封装结构及其制备方法

Country Status (1)

Country Link
CN (1) CN104538370A (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1921108A (zh) * 2005-08-23 2007-02-28 新光电气工业株式会社 半导体封装及其制造方法
US20100258932A1 (en) * 2009-04-08 2010-10-14 Elpida Memory, Inc. Supporting substrate before cutting, semiconductor device, and method of forming semiconductor device
CN203118928U (zh) * 2012-12-13 2013-08-07 欣兴电子股份有限公司 封装结构

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1921108A (zh) * 2005-08-23 2007-02-28 新光电气工业株式会社 半导体封装及其制造方法
US20100258932A1 (en) * 2009-04-08 2010-10-14 Elpida Memory, Inc. Supporting substrate before cutting, semiconductor device, and method of forming semiconductor device
CN203118928U (zh) * 2012-12-13 2013-08-07 欣兴电子股份有限公司 封装结构

Similar Documents

Publication Publication Date Title
CN102456677B (zh) 球栅阵列封装结构及其制造方法
KR101190920B1 (ko) 적층 반도체 패키지 및 그 제조 방법
CN101728287A (zh) 使用涂覆有焊料的柱形凸起的晶片级封装
CN103119711A (zh) 形成完全嵌入式非凹凸内建层封装件的方法和由此形成的结构
US9502392B2 (en) Semiconductor device with embedded semiconductor die and substrate-to-substrate interconnects
CN104505382A (zh) 一种圆片级扇出PoP封装结构及其制造方法
US20130009311A1 (en) Semiconductor carrier, package and fabrication method thereof
US20130069223A1 (en) Flash memory card without a substrate and its fabrication method
CN202394859U (zh) 半导体封装构造
CN104078435A (zh) Pop封装结构
US20130256915A1 (en) Packaging substrate, semiconductor package and fabrication method thereof
KR101474189B1 (ko) 집적회로 패키지
US10002852B1 (en) Package on package configuration
KR101685068B1 (ko) 시스템 인 패키지 및 이의 제조방법
CN106997875A (zh) 一种PoP堆叠封装结构及其制造方法
CN109817530B (zh) 封装组件制造方法
CN104538368A (zh) 一种基于二次塑封技术的三维堆叠封装结构及其制备方法
CN105161475A (zh) 带有双圈焊凸点的无引脚csp堆叠封装件及其制造方法
CN103985693A (zh) 无刷直流电机集成驱动电路的封装结构及其封装方法
CN104538370A (zh) 一种基于预留槽塑封技术的pop封装结构及其制备方法
KR20160017412A (ko) 캐버티 기판을 이용한 적층형 반도체 패키지 구조 및 방법
CN104103536A (zh) Pop封装方法
CN106098676A (zh) 多通道堆叠封装结构及封装方法
KR101432486B1 (ko) 집적회로 패키지 제조방법
CN205881899U (zh) 多通道堆叠封装结构

Legal Events

Date Code Title Description
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20150422

WD01 Invention patent application deemed withdrawn after publication