CN104517907A - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN104517907A
CN104517907A CN201410446862.7A CN201410446862A CN104517907A CN 104517907 A CN104517907 A CN 104517907A CN 201410446862 A CN201410446862 A CN 201410446862A CN 104517907 A CN104517907 A CN 104517907A
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China
Prior art keywords
circuit board
semiconductor chip
electrode
type surface
semiconductor device
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Pending
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CN201410446862.7A
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English (en)
Inventor
高桥聪
仮屋崎修一
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Renesas Electronics Corp
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Renesas Electronics Corp
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Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of CN104517907A publication Critical patent/CN104517907A/zh
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Abstract

本发明涉及一种半导体器件。防止电子部件在布线基板上的安装位置上产生错误。第一半导体芯片具有主表面和背表面。背表面是主表面的相反表面。第一半导体芯片的背表面是其主表面上的相反表面。布线基板是矩形的，并具有主表面和背表面。第一半导体芯片安装在布线基板的主表面上。盖覆盖布线基板的主表面和第一半导体芯片。电子部件安装在布线基板的背表面上。布线基板的主表面至少在彼此面对的两个角处具有没有被盖覆盖的未覆盖区域。

Description

半导体器件
相关申请的交叉引用
2013年9月3日提交的日本专利申请No.2013-182363的公开，包括说明书、附图和摘要，其全部通过引用并入本文中。
技术领域
本发明涉及一种半导体器件，例如，可以应用于其中半导体芯片安装在布线基板的主表面上的半导体器件的技术。
背景技术
作为用于在布线基板上安装半导体芯片的方法之一，有倒装芯片结构。在倒装芯片结构中，上面形成电极焊盘的半导体芯片的表面面对布线基板侧，并且半导体芯片利用设置在电极焊盘上的端子安装在布线基板上。在倒装芯片结构中，可以提供盖，用于辐射来自半导体芯片的热量或者保护半导体芯片(例如，参见日本未审查专利申请公开No.2012-54597)的目的。
日本未审查专利申请公开No.平5(1993)-275552公开了上面安装有诸如压电振动器的电子部件的绝缘基底的角被切角(notch)。
发明内容
本发明人已经研究了，为了小型化具有半导体器件的电子装置，在没有安装半导体芯片的布线基板的表面上安装了至今已被安装在母板上的电子部件(例如，电容元件或电阻元件)。为了进行这种安装，在布线基板的第一表面上布置了半导体芯片和诸如盖的覆盖构件之后，必需将布线基板的第一表面侧保持到固定夹具(retention jig)上。在这种情况下，覆盖构件可以抵接固定夹具以间接地确定布线基板相 对于固定夹具的位置。
另一方面，由于使用粘接层将覆盖构件固定到布线基板上，所以覆盖构件可以相对于布线基板的第一表面倾斜。在这种情况下，布线基板相对于固定夹具的位置有变化的可能。当该位置改变时，电子部件在布线基板上的安装位置会产生错误。从本说明书的描述和附图，其它问题和新颖特征将变得显而易见。
根据实施例，第一半导体芯片安装在布线基板的主表面上。盖覆盖布线基板的主表面和第一半导体芯片。电子部件安装在布线基板的背表面上。布线基板的主表面至少在彼此相对的两个角处具有没有覆盖有盖的未覆盖区域。
根据该实施例，在半导体芯片和诸如盖的覆盖构件布置在布线基板的第一表面上之后，在将布线基板的第一表面侧保持到固定夹具时，布线基板的未覆盖区域可以由固定夹具保持。因此，提高了布线基板相对于固定夹具的位置的精度。
附图说明
图1是示出根据实施例的半导体器件的构造的平面图；
图2是沿图1中的线A-A'得到的截面图；
图3是示出布线基板的主表面的构造的图；
图4是示出半导体器件的背表面的第一实例的图；
图5是示出半导体器件的背表面的第二实例的图；
图6是示出连接至电子部件的端子和电极之间的距离的图；
图7是示出第一半导体芯片的构造的截面图；
图8A至8C是示出制造半导体器件的方法的截面图；
图9A和9B是示出制造半导体器件的方法的截面图；
图10是示出固定夹具的构造的平面图；
图11是沿图10的B-B'线得到的截面图；
图12是沿图10中的C-C'线得到的截面图；
图13是示出通过在布线基板上提供未覆盖区域所获得的优点的图；
图14是示出通过在布线基板上提供未覆盖区域所获得的优点的图；
图15是示出根据变形例1的半导体器件的构造的平面图；
图16是示出其中从图15所示的半导体器件移除盖的状态的平面图；
图17是示出布线基板的背表面的第一实例的图；
图18是示出布线基板的背表面的第二实例的图；
图19是示出布线基板的背表面的第三实例的图；
图20是示出固定夹具的平面图；
图21是沿图20的B-B'线得到的截面图；
图22是沿图20的C-C'线得到的截面图；
图23是示出根据变形例2的半导体器件的布线基板的背表面的图；
图24是示出图23的变形例的图；
图25是示出图23的变形例的图；
图26是示出图23的变形例的图；
图27是示出根据变形例3的制造半导体器件的方法的图；
图28A和28B是示出根据变形例3的制造半导体器件的方法的图；
图29A和29B是示出根据变形例3的制造半导体器件的方法的图；
图30A和30B是示出根据变形例3的制造半导体器件的方法的图；
图31是半导体器件的顶视图；
图32是图31所示的半导体器件的后视图；
图33是示出半导体器件的变形例的后视图；
图34是示出半导体器件的变形例的后视图；
图35是示出半导体器件的变形例的后视图；和
图36是示出半导体器件的变形例的截面图。
具体实施方式
在下文中，将参考附图说明实施例。在所有附图中，相同的部件用相同的符号表示，并且将适当省略对它们的描述。
实施例
图1是示出根据实施例的半导体器件SD的构造的平面图。图2是沿图1中的线A-A'得到的截面图。在图2中，为便于附图的可视化，减少了外部连接端子SB的数量和电子部件ELP1的数量。
根据本实施例的半导体器件SD包括：第一半导体芯片SC1、布线基板ISUB、盖LID(覆盖构件)和电子部件ELP1。第一半导体芯片SC1的背表面SFC4是其主表面SFC3的相反表面。布线基板ISUB为矩形，并且包括主表面SFC1(第二主表面)和背表面SFC2(第二背表面)。第一半导体芯片SC1安装在主表面SFC1上。盖LID覆盖布线基板ISUB的主表面SFC1和第一半导体芯片SC1。电子部件ELP1安装在布线基板ISUB的背表面SFC2上。布线基板ISUB的主表面SFC1至少在彼此面对的两个角处具有未被盖LID覆盖的未覆盖区域LDO。换句话说，在主表面SFC1上的至少彼此面对的两个角处，未覆盖有盖LID的部分的宽度比主表面SFC1的边缘的其它部分宽。在下文中，将详细说明该构造。
如图2所示，第一半导体芯片SC1以倒装芯片方式安装在布线基板ISUB上。第一半导体芯片SC1被配置为例如逻辑芯片，但也可以配置为存储器芯片、其中逻辑芯片和存储器电路混合在一起的芯片、或者控制电功率的功率芯片。
多个电极焊盘EL(稍后将参照图7描述)形成在第一半导体芯片SC1的主表面SFC3上。第一半导体芯片SC1以主表面SFC3面对布线基板ISUB的主表面SFC1的方向安装在主表面SFC1上。电极焊盘EL通过端子BMP(例如，焊料凸块、或者诸如Cu柱或Au柱的导体柱) 连接到形成在布线基板ISUB的主表面SFC1上的端子(未示出)。形成在第一半导体芯片SC1的主表面SFC3与布线基板ISUB的主表面SFC1之间的空间是由底部填充树脂UFR1密封的。底部填充树脂UFR1的一部分沿第一半导体芯片SC1的侧面蔓延以形成嵌边(fillet)。
第一半导体芯片SC1的背表面SFC4通过粘接层固定到盖LID。优选的是，粘接层的热导率高。
盖LID是通过拉伸由诸如Cu的金属制成的板形成的。结果，使盖LID成形，使得与第一半导体芯片SC1接触的中心部CNT和边缘EDG通过斜坡部SLP彼此连接。随着倾斜部SLP更离开中心部CNT，倾斜部SLP倾斜以更接近布线基板ISUB。倾斜部SLP相对中心部CNT的倾斜角可以是接近垂直的。盖LID的边缘EDG变为与布线基板ISUB的位于底部填充树脂UFR1外部的区域相接触。盖LID的边缘EDG的至少一部分通过粘接层固定到布线基板ISUB。
如图1所示，盖LID的平面形状在彼此相对的矩形的两个角处被切角。盖LID的四个角与布线基板ISUB的相应的四个角重叠。布线基板ISUB的未涂覆区域LDO位于盖LID的其中角被切角的部分处。未涂覆区域LDO的与布线基板ISUB的对角线重叠的部分的宽度，例如，等于或大于1mm，并且等于或小于6mm。
盖LID的倾斜部SLP沿着其中矩形的四个角被切角的轮廓线形成。换句话说，倾斜部SLP沿着八边形的各个边形成。在八边形中，分别彼此相对的两个边是互相平行的，并且面对布线基板ISUB的四个角的四个边每个都比面对布线基板ISUB的四个边的四个边短。
如图2所示，布线基板ISUB例如由树脂中介层形成，并且在背表面SFC2上具有多个电极LND(第一背电极)。多个电极LND通过布线基板ISUB内的贯通孔(未示出)或布线(未示出)连接到端子 BMP。多个电极LND的一部分可以通过布线基板ISUB内的线连接到电子部件ELP。电极LND提供有外部连接端子SB。例如，外部连接端子SB是由焊料球构成的。
电子部件ELP安装在布线基板ISUB的背表面SFC2上。电子部件ELP被配置为例如诸如电容器、电阻器或电感器的分立部件，但也可以由构成电路的芯片配置。电子部件ELP连接到设置在背表面SFC2上的端子ELA。
而且，如图1所示，布线基板ISUB的主表面SFC1提供有对准标记AMK1。对准标记AMK1是由与形成在主表面SFC1上的线相同的导体(例如，铜)制成的图案，并且当第一半导体芯片SC1和盖LID安装在主表面SFC1上时用作定位图案。对准标记AMK1位于主表面SFC1的任意的未涂覆区域LDO。
图3是示出布线基板ISUB的主表面SFC1的构造的图。多个电极FNG(第二电极)形成在其中第一半导体芯片SC1将被布置在主表面SFC1上的区域中。各电极FNG通过端子BMP连接到第一半导体芯片SC1的电极焊盘EL。
图4是示出半导体器件SD的背表面的第一实例的图。在该图所示的实例中，多个外部连接端子SB和多个电极LND布置在背表面SFC2的除了与第一半导体芯片SC1二维地、换句话说在格点上重叠的部分以外的区域中。多个电子部件ELP1安装在背表面SFC2的其中没有形成电极LND和外部连接端子SB的部分，也就是说，与第一半导体芯片SC1重叠的部分上。电子部件ELP1通过布线基板ISUB的贯通孔和布线连接到第一半导体芯片SC1。采用这种布置，可以减小连接第一半导体芯片SC1和电子部件ELP1的连接路径的电感。电子部件ELP1由例如功率增强电容器配置。
图5是示出半导体器件SD的背表面的第二实例的图。该图中所示的实例除了以下构造之外与图4所示的实例相同。首先，电极LND和外部连接端子SB形成在背表面SFC2的与第一半导体芯片SC1重叠的部分下面。电子部件ELP1布置在第一半导体芯片SC1的边缘附近。采用这种布置，与图4中所示的实例相比，可以增加外部连接端子SB的数量。而且，可以抑制连接第一半导体芯片SC1和电子部件ELP1的连接路径的电感。
在图4和5的每一个中，可以省略电极LND和外部连接端子SB的至少一部分。而且，当电子部件ELP1安装在背表面SFC2上时，背表面SFC2的电极LND的至少一部分用作定位标记。例如，电极LND位于背表面SFC2的角处。
图6是示出连接到电子部件ELP的端子ELA和电极LND之间的距离的图。电子部件ELP每个都有两个端子ELB。对应于这些端子ELB，对于一个电子部件ELP在背表面SFC2上形成两个端子ELA。假定在第一方向(图中的X方向)上排列的一个端子ELA的中心与电极LND的中心之间的距离为LBBC，在第二方向(图中的Y方向)上排列的另一端子ELA的中心与电极LND的中心之间的距离是LABC。而且，假定电极LND的半径为r，端子ELA在第一方向(图中的X方向)上的半宽度是BP，并且端子ELA在第二方向(图中的Y方向)上的半宽度是AP。而且，假定端子ELB在第一方向(图中的X方向)上的半宽度为BC，端子ELB在第二方向(图中的Y方向)上的半宽度是Ac。而且，假定两个端子ELA之间的间隔为G。然后，满足下面描述的式(1)、(2)或(3)。选择表达式(2)和(3)中的在右边大的任一个。
LABC>r+AC+AP···(1)
LBBC>r+BC+BP···(2)
LBBC>r+G+BP···(3)
在图6所示的实例中，电子部件ELP包括两种电子部件ELP1和ELP2。电子部件ELP1和ELP2的平面形状每个都是矩形。电子部件ELP1的端子ELB是沿着矩形的两条长边形成的，电子部件ELP2的端子ELB是沿着矩形的两条短边形成的。
图7是示出第一半导体芯片SC1的构造的截面图。第一半导体芯片SC1具有其中多层布线层MINC堆叠在基板SUB上的构造。例如，基板SUB是由硅基板形成的。多个半导体元件，例如，晶体管形成在基板SUB上。电极焊盘EL形成在多层布线层MINC的最上面的布线层上。电极焊盘EL通过图2中所示的端子BMP连接到图3所示的布线基板ISUB的电极FNG。
图8A到8C和图9A、9B是示出制造半导体器件SD的方法的截面图。在这些图所示的那些工艺之前，制备第一半导体芯片SC1。例如，如下形成第一半导体芯片SC1。
首先，在基板SUB上形成元件隔离膜。元件形成区域被元件隔离膜隔离。元件隔离膜例如通过STI技术形成，但也可以通过LOCOS技术形成。然后，在位于元件形成区域的基板SUB上形成栅极绝缘膜和栅电极。栅极绝缘膜可以由氧化硅膜形成，或者可以由介电常数比氧化硅膜高的高介电常数膜(例如，铪硅膜)形成。当栅极绝缘膜由氧化硅膜形成时，栅电极由多晶硅膜形成。而且，当栅极绝缘膜为高介电常数膜时，栅电极由金属膜(例如，TiN)和多晶硅膜的叠层膜形成。而且，当栅电极由多晶硅制成时，在形成栅电极的工艺中可以在元件隔离膜上形成多晶硅电阻器。
随后，在位于元件形成区域中的基板SUB上形成源极和漏极的延伸区。然后，在栅电极的侧壁上形成侧壁。然后，在位于元件形成区域中的基板SUB上形成杂质区，该杂质区形成源极和漏极。以这种方式，在基板SUB上形成MOS晶体管。
然后，在元件隔离膜和MOS晶体管上形成多层布线层MINC。在最上面的布线层上形成电极焊盘EL。然后，在多层布线层MINC上形成保护绝缘膜(钝化膜)。位于EL上的开口形成在保护绝缘膜上。然后，在电极焊盘EL上形成端子BMP。
然后，如图8A所示，在布线基板ISUB的主表面SFC1上安装第一半导体芯片SC1。然后，如图8B所示，允许底部填充树脂UFR1流入形成在主表面SFC1和第一半导体芯片SC1之间的空间中。底部填充树脂UFR1可以由NCF(非导电膜)形成。在这种情况下，在第一半导体芯片SC1安装在主表面SFC1上之前，NCF形成在主表面SFC1上。
然后，如图8C所示，将盖LID固定到第一半导体芯片SC1的背表面SFC4和布线基板ISUB的主表面SFC1上。
在图8A到8C所示的工艺中，使用对准标记AMK1来确定第一半导体芯片SC1和盖LID相对于布线基板ISUB的定向。基于形成在布线基板ISUB的主表面SFC1上的另一个对准标记进行第一半导体芯片SC1和盖LID相对于布线基板ISUB的定位。
然后，如图9A所示，向上翻转布线基板ISUB的背表面SFC2。然后，将电子部件ELP安装在背表面SFC2上。之后，如图9B所示，在背表面SFC2的电极LND上安装外部连接端子SB。
图10是示出当在背表面SFC2上安装电子部件ELP和外部连接端子SB时使用的固定夹具HLD的构造的平面图。图11是沿着图10中的B-B'线得到的截面图，图12是沿着图10中的C-C'线得到的截面图。
固定夹具HLD由板构件形成，并且在其中心部具有开口OP。开 口OP的平面形状大致为矩形，并且与布线基板ISUB的平面形状的大小大致相同。也就是说，将布线基板ISUB适配到开口OP中。开口OP的四个角中彼此面对的两个角每个都形成有支撑部PRJ。支撑部PRJ中的每一个都被成形为从开口OP的内表面对开口OP的内侧突出。其上适配有布线基板ISUB的支撑部PRJ的表面的高度比固定夹具HLD的主体低。在该图所示的实例中，支撑部PRJ每个都沿着构成开口OP的角的两个侧表面形成。
然后，将粘附了第一半导体芯片SC1和盖LID的布线基板ISUB以主表面SFC1面对固定夹具HLD的方向安装到固定夹具HLD中。在这种情况下，使布线基板ISUB的未覆盖区域LDO配置为面对支撑部PRJ。采用上述构造，支撑部PRJ的上表面抵接布线基板ISUB的未覆盖区域LDO，并且由布线基板ISUB的支撑部PRJ定位。
随后，将利用图13和14描述通过在布线基板ISUB上提供未覆盖区域LDO所获得的优点。
利用粘接层ADA将盖LID固定到布线基板ISUB，但是粘接层ADA的厚度可能会变化。为此，可以使盖LID相对于布线基板ISUB倾斜。
如果没有在布线基板ISUB上提供未覆盖区域LDO，布线基板ISUB的大致整个表面覆盖有盖LID。为此，如图13所示，固定夹具HLD的支撑部PRJ支撑盖LID的边缘EDG。在该实例中，当盖LID相对于基板SUB倾斜时，背表面SFC2也被包括在其中布线基板ISUB由固定夹具HLD保持的状态。 
当背表面SFC2倾斜时，存在邻近于将用作对准标记的电极LND定位的电极LND被错误地认作对准标记的问题。在这种情况下，存在电子部件ELP安装在不正确位置的问题。
而且，当在上面形成外部连接端子SB之前通过丝网印刷技术将焊剂涂覆在布线基板ISUB上时，如果背表面SFC2倾斜，丝网掩膜可能会变形，或焊剂涂覆的量可能变得不均匀。
相反，在本实施例中，如图14所示，因为固定夹具HLD的支撑部PRJ的上表面抵接布线基板ISUB的未覆盖区域LDO，所以由支撑部PRJ定位布线基板ISUB。因此，即使盖LID相对于布线基板ISUB是倾斜的，也以相对固定夹具HLD的给定角度(例如，平行)定位布线基板ISUB的背表面SFC2。因此，难以产生参照图13描述的缺点。 
变形例1
图15是示出根据变形例1的半导体器件SD的构造的平面图。图16是示出其中从图15所示的半导体器件SD移除盖的状态的平面图。除了下面的构造之外，根据本变形例的半导体器件具有与根据实施例的半导体器件SD相同的构造。
首先，如图15所示，盖LID的所有的四个角都被切角。为布线基板ISUB的所有的四个角设置未覆盖区域LDO。
而且，如图16所示，第一半导体芯片SC1以及第二半导体芯片SC2都被安装在布线基板ISUB的主表面SFC1上。第二半导体芯片SC2具有与图8所示的第一半导体芯片SC1相同的构造。而且，用于连接到第二半导体芯片SC2的电极焊盘EL(第三电极)的电极FNG(第四电极)被形成在布线基板ISUB的面对第二半导体芯片SC2的区域中。第二半导体芯片SC2如同第一半导体芯片SC1以倒装芯片的方式安装在主表面SFC1上。上面形成有电极焊盘EL的第二半导体芯片SC2的表面(第五主表面)由底部填充树脂UFR2密封。
在该变形例中，第一半导体芯片SC1和第二半导体芯片SC2每个 都是矩形的，并且在各个长边相互平行的方向上安装在主表面SFC1上。为此，应力容易在沿着第一半导体芯片SC1的长边的方向(图中的Y方向)翘曲的方向上施加在布线基板ISUB上。在该图所示的实例中，第一半导体芯片SC1的短边平行于布线基板ISUB的第三边SID3和第四边SID4，并且第一半导体芯片SC1的长边平行于布线基板ISUB的第一边SID1和第二边SID2。
相反，在本变形例中，如图15所示，作为与第一半导体芯片SC1的短边平行的区域的边缘EDG1和EDG2的宽度比作为与第一半导体芯片SC1的长边平行的区域的边缘EDG3和EDG4的宽度宽。盖LID的边缘EDG1和EDG2被固定到主表面SFC1。然而，边缘EDG3和EDG4仅仅与主表面SFC1接触。换句话说，盖LID沿着布线基板ISUB的第一边SID1和第二边SID2固定。然而，盖LID没有固定到第三边SID3和第四边SID4。采用上述构造，布线基板ISUB的翘曲可以通过盖LID抑制。
图17是示出在该变形例中的布线基板ISUB的背表面SFC2的第一实例的图。在图17所示的实例中，电子部件ELP被设置在背表面SFC2的与第一半导体芯片SC1重叠的区域中，以及背表面SFC2的与第二半导体芯片SC2重叠的区域中。位于与第一半导体芯片SC1重叠的区域中的电子部件ELP被电连接到第一半导体芯片SC1。而且，位于与第二半导体芯片SC2重叠的区域中的电子部件ELP被电连接到第二半导体芯片SC2。
图18是示出在该变形例中的布线基板ISUB的背表面SFC2的第二实例的图。在图18所示的实例中，电子部件ELP至少被设置在背表面SFC2的与第一半导体芯片SC1重叠的区域周围，和背表面SFC2的与第二半导体芯片SC2重叠的区域周围。在图18所示的实例中，第一半导体芯片SC1比第二半导体芯片SC2大。电子部件ELP被设置在背表面SFC2的与第一半导体芯片SC1重叠的区域周围。这些电子部件 ELP电连接到第一半导体芯片SC1。
图19是示出在该变形例中的布线基板ISUB的背表面SFC2的第三实例的图。在图19所示的实例中，第一半导体芯片SC1比第二半导体芯片SC2大。电子部件ELP被设置在背表面SFC2的与第一半导体芯片SC1重叠的区域周围，以及背表面SFC2的与第二半导体芯片SC2重叠的区域中。位于与第一半导体芯片SC1重叠的区域周围的电子部件ELP被电连接到第一半导体芯片SC1。位于与第二半导体芯片SC2重叠的区域中的电子部件ELP被电连接到第二半导体芯片SC2。
除了固定夹具HLD的开口OP的形状之外，制造根据本变形例的半导体器件SD的方法与制造根据实施例的半导体器件SD的方法相同。
图20是示出本变形例中使用的固定夹具HLD的构造的平面图。图21是沿着图20的B-B'线得到的截面图。图22是沿着图20的C-C'线得到的截面图。除了支撑部PRJ形成在开口OP的各自的四个角之外，在这些图中示出的固定夹具HLD与实施例中所示的固定夹具HLD的构造相同。
该变形例也获得了与实施例相同的优点。而且，各个未覆盖区域LDO形成在布线基板ISUB的所有四个角处。而且，对应于该构造，各个支撑部PRJ形成在固定夹具HLD的开口OP的所有四个角处。因此，当布线基板ISUB适配到开口OP中时，可以防止布线基板ISUB相对于固定夹具HLD移动。
变形例2
图23是示出根据变形例2的半导体器件SD中的布线基板ISUB的背表面SFC2的图。除了至少一个第二背电极AMK2(导体图案)被设置在背表面SFC2上之外，根据本变形例的半导体器件与根据实施例 的半导体器件SD的构造相同。
第二背电极AMK2由与电极LND相同层的导体图案(例如，Cu图案)构成，并且在与电极LND相同的工序中形成。然而，第二背电极AMK2与电极LND的尺寸和形状中的至少一项不同。当电子部件ELP安装在背表面SFC2上时，第二背电极AMK2用作定位标记。在图23所示的实例中，第二背电极AMK2布置在背表面SFC2上彼此面对的相应的两个角处。在这种情况下，电极LND不形成在背表面SFC2的与第二背电极AMK2相比更靠近背表面SFC2的边缘的区域中。
外部连接端子SB不形成在第二背电极AMK2上。采用上述构造，可以任意设定第二背电极AMK2的形状和尺寸。外部连接端子SB可以形成在第二背电极AMK2上。
而且，如图24所示，第二背电极AMK2可以布置在背表面SFC2的其中形成了电极LND的区域中。在图24所示的实例中，两个第二背电极AMK2布置在跨背表面SFC2的与第一半导体芯片SC1重叠的区域彼此面对的位置上。换句话说，第二背电极AMK2布置在跨多个电子部件ELP彼此面对的位置上。
如图25和26所示，第二背电极AMK2可以布置在根据变型例1半导体器件SD中。
在图25所示的实例中，设置了四个第二背电极AMK2。这些第二背电极AMK2中的两个布置在跨背表面SFC2的与第一半导体芯片SC1重叠的区域彼此面对的位置处，并且两个剩余的第二背电极AMK2布置在跨背表面SFC2的与第二半导体芯片SC2重叠的区域彼此面对的位置。
在图26所示的实例中，设置了两个第二背电极AMK2。第一个第 二背电极AMK2布置在背表面SFC2的与第一半导体芯片SC1重叠的区域附近，并且第二个第二背电极AMK2布置在背表面SFC2的与第二半导体芯片SC2重叠的区域附近。
本变形例也获得了与实施例相同的优点。而且，除电极LND以外，将第二背电极AMK2设置为定位标记。第二背电极AMK2与电极LND不同之处在于平面形状和尺寸中的至少一项。为此，电极LND被错误地识别为第二背电极AMK2的可能性变低。因此，当电子部件ELP安装在布线基板ISUB的背表面SFC2上时，可以进一步防止电子部件ELP的位置偏移。
变形例3
根据本变形例的半导体器件SD具有密封树脂MDR，代替盖LID。然后，使用接合线WIR在布线基板ISUB上安装第一半导体芯片SC1。
图27至图30是示出制造根据本变形例的半导体器件SD的方法的图。首先，如图27的平面图所示，制备布线基板ISUB。在这些图所示的状态中，多个(例如，1×n个)布线基板ISUB彼此连接。
然后，如图28A的平面图和图28B的截面图所示，第一半导体芯片SC1和电子部件ELP安装在多个布线基板ISUB的主表面SFC1的每一个上。在背表面SFC4面对布线基板ISUB的主表面SFC1的方向上，在主表面SFC1上安装第一半导体芯片SC1。然后，使用接合线WIR将第一半导体芯片SC1的电极焊盘EL连接到布线基板ISUB。
然后，如图29A的截面图所示，在布线基板ISUB的主表面SFC1上布置模具MMD。模具MMD在面对各个布线基板ISUB的区域中具有空腔。然后，使密封树脂MDR流入多个空腔中的每一个。之后，如图29B所示，移除模具MMD。通过这种方式，多个第一半导体芯片SC1分别被密封树脂MDR密封。主表面SFC1上的电子部件ELP也由 密封树脂MDR密封。在该实例中，布线基板ISUB的位于其两端的边缘的至少一部分未覆盖有密封树脂MDR，并且形成有未覆盖区域LDO。
之后，如图30A所示，电子部件ELP和外部连接端子SB，以布线基板ISUB的背表面SFC2向上翻转的这种方式，安装在背表面SFC2上。在这种情形下，像该实施例一样，使用固定夹具HLD。固定夹具HLD的支撑部PRJ抵接布线基板ISUB的位于其两端的边缘的没有覆盖密封树脂MDR的区域(未覆盖区域LDO)。为此，即使密封树脂MDR的上表面是倾斜的，也可以防止布线基板ISUB的背表面SFC2相对于固定夹具HLD倾斜，如同实施例一样。
之后，如图30B所示，分割布线基板ISUB，并切割半导体器件SD。
图31是根据本变形例的半导体器件SD的顶视图。除了没有提供边缘EDG之外，密封树脂MDR的上表面的形状与根据变形例1的盖LID的上表面的形状基本相同。对准标记AMK1的一部分由树脂密封MDR密封。
图32是图31所示的半导体器件SD的后视图。而且，在该变形例中，多个外部连接端子SB设置在布线基板ISUB的背表面SFC2上。多个电子部件ELP安装在背表面SFC2的与第一半导体芯片SC1重叠的区域中。这些电子部件ELP电连接到第一半导体芯片SC1。
如图33所示，变形例2中所示的第二背电极AMK2可以设置在布线基板ISUB的背表面SFC2上。在图33所示的实例中，第二背电极AMK2设置在切割区DSA中。
而且，如图34所示，在半导体器件SD尚未被切割的状态下，n ×m个布线基板ISUB可以彼此连接。在这种情况下，如图35所示，可以设置第二背电极AMK2。
而且，如图36所示，模具MMD可被成形为具有一个空腔。在这种情况下，多个第一半导体芯片SC1和多个电子部件ELP位于同一空腔内，并且第一半导体芯片SC1和电子部件ELP由密封树脂MDR一体地密封。而且，在该实例中，布线基板ISUB的位于其两端的边缘的至少一部分没有被密封树脂MDR密封。因此，固定夹具HLD的支撑部PRJ抵接布线基板ISUB的位于其两端的边缘的没有覆盖密封树脂MDR的区域(未覆盖区域LDO)。为此，可以防止布线基板ISUB的背表面SFC2相对于固定夹具HLD倾斜。
基于上述实施例，上文具体描述了由本发明人做出的发明。然而，本发明并不限于这些实施例，而是可以在不脱离本发明的精神的情况下进行各种改变。

Claims (10)

1.一种半导体器件，包括：
第一半导体芯片，所述第一半导体芯片具有第一主表面和是所述第一主表面的相反表面的第一背表面；
矩形的布线基板，所述布线基板具有第二主表面和是所述第二主表面的相反表面的第二背表面，其中，所述第一半导体芯片安装在所述第二主表面上；
覆盖构件，所述覆盖构件覆盖所述布线基板的所述第二主表面和所述第一半导体芯片；和
电子部件，所述电子部件安装在所述布线基板的所述第二背表面上，
其中，所述布线基板的所述第二主表面至少在彼此面对的两个角处具有没有被所述覆盖构件覆盖的未覆盖区域。
2.根据权利要求1所述的半导体器件，
其中，所述未覆盖区域设置在所述布线基板的四个角处。
3.根据权利要求2所述的半导体器件，
其中，所述覆盖构件的平面形状为矩形，并且在四个角处分别被切角，并且
其中，所述覆盖构件的四个角与所述布线基板的四个角重叠。
4.根据权利要求1所述的半导体器件，
其中，所述未覆盖区域的与所述布线基板的对角线重叠的部分的宽度等于或大于1mm，并且等于或小于6mm。
5.根据权利要求1所述的半导体器件，进一步包括：
多个第一背电极，所述多个第一背电极设置在所述布线基板的所述第二背表面上；
外部连接端子，所述外部连接端子是分别为所述第一背电极设置的；和
至少一个导体图案，所述至少一个导体图案设置在所述布线基板的所述第二背表面上，并且形状和大小中的至少一项与所述多个第一背电极不同。
6.根据权利要求5所述的半导体器件，
其中，所述外部连接端子没有形成在所述导体图案中。
7.根据权利要求1所述的半导体器件，
其中，所述第一半导体芯片在所述第一主表面上具有多个第一电极，
其中，所述布线基板在所述第二主表面上具有多个第二电极，
其中，所述第一半导体芯片以使得所述第一主表面面对所述第二主表面的方向安装在所述布线基板上，并且
其中，所述多个第一电极连接到所述多个第二电极。
8.根据权利要求1所述的半导体器件，
其中，所述覆盖构件被固定到所述布线基板的第一边和面对所述第一边的第二边，并且没有固定到是所述布线基板的其余边的第三边和第四边。
9.根据权利要求8所述的半导体器件，
其中，所述第一半导体芯片的平面形状为矩形，并且
其中，所述第一半导体芯片的长边沿着所述布线基板的所述第三边设置。
10.根据权利要求9所述的半导体器件，进一步包括：第二半导体芯片，所述第二半导体芯片具有第五主表面，并且平面形状是矩形，
其中，所述第二半导体芯片在所述第五主表面上具有多个第三电极，
其中，所述布线基板在所述第二主表面上具有多个第四电极，
其中，所述第二半导体芯片以使得所述第五主表面面对所述第二主表面的方向安装在所述布线基板上，
其中，所述多个第三电极连接到所述多个第四电极，并且
其中，所述第二半导体芯片的长边沿着所述布线基板的所述第三边设置。
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