CN104485287B - 包含溢流槽的新型qfn框架的制备方法 - Google Patents

包含溢流槽的新型qfn框架的制备方法 Download PDF

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CN104485287B
CN104485287B CN201410735577.7A CN201410735577A CN104485287B CN 104485287 B CN104485287 B CN 104485287B CN 201410735577 A CN201410735577 A CN 201410735577A CN 104485287 B CN104485287 B CN 104485287B
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CN104485287A (zh
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倪侠
张俊
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Jiangsu Dongchen Electronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
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Abstract

本发明公开了一种包含溢流槽的新型QFN框架的制备方法，包含的步骤为：首先，制备包含所需刻蚀图形的掩膜版；其次，利用掩膜板按常规光刻工艺对框架基材进行光刻，实现全覆盖保护区、无覆盖区以及网格图形覆盖区；第三，按常规工艺进行喷淋腐蚀，构造出框架结构；第四，去胶；即可获得所设计的框架。在喷淋腐蚀过程中，全覆盖保护区未受腐蚀影响，无覆盖区受到1/2腐蚀，形成隔断的引脚；网格图形覆盖区腐蚀速率由于网格图形的影响而变慢，形成1/3腐蚀，同时形成右下方外露的引脚和溢流槽结构。本发明通过溢流槽吸纳多余的粘片胶，从而提高该型产品封装合格率。

Description

包含溢流槽的新型QFN框架的制备方法
技术领域
本发明属于半导体器件设计及制造领域，具体是一种包含溢流槽的新型QFN框架的制备方法。
背景技术
在集成电路的QFN封装中，通常需要粘片胶溢出至芯片侧面才能保证芯片与框架间无缝隙，提高产品可靠性。而有些器件则需控制粘片胶溢出到芯片侧片，否则会导致芯片短路失效。如图1所示，常规的QFN框架通过湿法腐蚀工艺制备，涂覆光刻胶并曝光相应的图形，经一次湿法腐蚀形成所需电路功能的框架。但这种常规框架无法很好地控制粘片胶的溢出，致使该型产品的QFN封装合格率极低。
发明内容
为解决现有技术的不足，本发明一种包含溢流槽的新型QFN框架的制备方法，其通过对需腐蚀区域的光刻胶进行网格化设计，从而在一次腐蚀过程中通过网格疏密形成多种腐蚀速率，构造更为复杂的框架结构。
本发明采取的技术方案是：一种包含溢流槽的新型QFN框架的制备方法，包含如下步骤：
首先，制备包含所需刻蚀图形的掩膜版；
其次，利用掩膜板按常规光刻工艺对框架基材进行光刻，实现全覆盖保护区、无覆盖区以及网格图形覆盖区；
第三，按常规工艺进行喷淋腐蚀，构造出框架结构；
第四，去胶；即可获得所设计的框架。
本发明中，所述全覆盖保护区、无覆盖区以及网格图形覆盖区经曝光掩膜版上相应的刻蚀图形而形成。在喷淋腐蚀过程中，全覆盖保护区未受腐蚀影响，无覆盖区受到1/2腐蚀，形成隔断的引脚；网格图形覆盖区腐蚀速率由于网格图形的影响而变慢，形成1/3腐蚀，同时形成右下方外露的引脚和溢流槽结构。所述网格图形覆盖区由全覆盖保护区和无覆盖区相间形成。
优选的，所述网格图形覆盖区中相间形成的的网格条纹倾斜排列且条纹宽1μm。所述溢流槽的内围小于芯片尺寸，外围则略大于芯片尺寸。所述溢流槽的槽宽为400-600mm。
本发明的有益效果是通过网格化的设计构造溢流槽结构，通过溢流槽吸纳多余的粘片胶，从而提高该型产品封装合格率。
附图说明
图1为常规双面半导体器件的QFN 封装结构示意图。
图2为本发明的封装结构示意图。
图3为本发明框架基材结构俯视图。
图4为本发明中光刻胶覆盖示意图。
图5为本发明中网格构造示意图。
具体实施方式
下面结合附图对本发明作进一步说明。
如图2至图5所示，一种包含溢流槽的新型QFN框架的制备方法，包含如下步骤：
首先，制备包含所需刻蚀图形的掩膜版；
其次，利用掩膜板按常规光刻工艺对框架基材进行光刻，实现全覆盖保护区、无覆盖区以及网格图形覆盖区；
第三，按常规工艺进行喷淋腐蚀，构造出框架结构；
第四，去胶；即可获得所设计的框架。
本发明中，所述全覆盖保护区、无覆盖区以及网格图形覆盖区经曝光掩膜版上相应的刻蚀图形而形成。在喷淋腐蚀过程中，全覆盖保护区未受腐蚀影响，无覆盖区受到1/2腐蚀，形成隔断的引脚5；网格图形覆盖区腐蚀速率由于网格图形的影响而变慢，形成1/3腐蚀，同时形成右下方外露的引脚6和溢流槽结构。所述网格图形覆盖区由全覆盖保护区和无覆盖区相间形成。
具体实施时，按本方法制作得出的封装结构包括芯片1及与其对接的框架3，所述框架3在其与芯片1侧面边缘对应的位置开有一定宽度的溢流槽2；芯片1和框架3通过导电胶粘合在基岛4上，过量的导电胶流入溢流槽2中。其中无覆盖区受到1/2左右（允许有范围，大于或小于1/2均可）腐蚀，网格图形覆盖区腐蚀速率由于网格图形的影响而变慢，形成1/3左右（允许有范围，大于或小于1/3均可）腐蚀。所述网格图形覆盖区中相间形成的的网格条纹倾斜排列且条纹宽1μm。所述溢流槽的内围小于芯片尺寸，外围则略大于芯片尺寸，槽宽为400-600mm，通常选取400mm。
本发明未涉及部分均与现有技术相同或可采用现有技术加以实现。

Claims (4)

1.一种包含溢流槽的QFN框架的制备方法，其特征在于，包含如下步骤：
首先，制备包含所需刻蚀图形的掩膜版；
其次，利用掩膜板按常规光刻工艺对框架基材进行光刻，实现全覆盖保护区、无覆盖区以及网格图形覆盖区；
第三，按常规工艺进行喷淋腐蚀，构造出框架结构；
第四，去胶；即可获得所设计的框架；
其中所述全覆盖保护区、无覆盖区以及网格图形覆盖区经曝光掩膜版上相应的刻蚀图形而形成，在喷淋腐蚀过程中，全覆盖保护区未受腐蚀影响，无覆盖区受到1/2腐蚀，形成隔断的引脚；网格图形覆盖区腐蚀速率由于网格图形的影响而变慢，形成1/3腐蚀，同时形成右下方外露的引脚和溢流槽结构。
2.根据权利要求1所述的包含溢流槽的QFN框架的制备方法，其特征在于：所述网格图形覆盖区由全覆盖保护区和无覆盖区相间形成。
3.根据权利要求2所述的包含溢流槽的QFN框架的制备方法，其特征在于：所述网格图形覆盖区中相间形成的的网格条纹倾斜排列且条纹宽1μm。
4.根据权利要求1所述的包含溢流槽的QFN框架的制备方法，其特征在于：所述溢流槽的槽宽为400-600mm。
CN201410735577.7A 2014-12-08 2014-12-08 包含溢流槽的新型qfn框架的制备方法 Active CN104485287B (zh)

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CN1577816A (zh) * 2003-06-27 2005-02-09 半导体元件工业有限责任公司 形成包封器件和结构的方法
CN1988077A (zh) * 2005-12-25 2007-06-27 群康科技(深圳)有限公司 电容制造方法
CN104064533A (zh) * 2014-07-03 2014-09-24 江苏东光微电子股份有限公司 一种双面半导体器件的qfn封装结构及方法

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