CN1044761C - 有噪声抵消性能的通信用接插件终端阵列 - Google Patents

有噪声抵消性能的通信用接插件终端阵列 Download PDF

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CN1044761C
CN1044761C CN94108188A CN94108188A CN1044761C CN 1044761 C CN1044761 C CN 1044761C CN 94108188 A CN94108188 A CN 94108188A CN 94108188 A CN94108188 A CN 94108188A CN 1044761 C CN1044761 C CN 1044761C
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conductor
electrical connector
terminal arrays
connector terminal
conductors
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CN1100879A (zh
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D·R·尼尔
C·G·里德
C·F·林肯
J·J·费里
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Whitaker LLC
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R11/00—Individual connecting elements providing two or more spaced connecting locations for conductive members which are, or may be, thereby interconnected, e.g. end pieces for wires or cables supported by the wire or cable and having means for facilitating electrical connection to some other wire, terminal, or conductive member, blocks of binding posts
    • H01R11/03—Individual connecting elements providing two or more spaced connecting locations for conductive members which are, or may be, thereby interconnected, e.g. end pieces for wires or cables supported by the wire or cable and having means for facilitating electrical connection to some other wire, terminal, or conductive member, blocks of binding posts characterised by the relationship between the connecting locations
    • H01R11/05—Individual connecting elements providing two or more spaced connecting locations for conductive members which are, or may be, thereby interconnected, e.g. end pieces for wires or cables supported by the wire or cable and having means for facilitating electrical connection to some other wire, terminal, or conductive member, blocks of binding posts characterised by the relationship between the connecting locations the connecting locations having different types of direct connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/646—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
    • H01R13/6461—Means for preventing cross-talk
    • H01R13/6467—Means for preventing cross-talk by cross-over of signal conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/02—Contact members
    • H01R13/03—Contact members characterised by the material, e.g. plating, or coating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R24/00—Two-part coupling devices, or either of their cooperating parts, characterised by their overall structure
    • H01R24/60—Contacts spaced along planar side wall transverse to longitudinal axis of engagement
    • H01R24/62—Sliding engagements with one side only, e.g. modular jack coupling devices
    • H01R24/64—Sliding engagements with one side only, e.g. modular jack coupling devices for high frequency, e.g. RJ 45
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S439/00—Electrical connectors
    • Y10S439/941—Crosstalk suppression

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Abstract

一种电接插件终端阵列，具有性能超过5类部件要求的干扰抵消特。接插件包括一个电介质壳体(40)，壳体内安置4对电导体(12)。电导体基本并行排列，导体一端的各导体间间一第一均匀间距，另一端各导体相互间比第一间距大的第二间距，其特征在于导体对无接触重叠排列，外部导体对单次相互交迭，而中心对则先互相交迭一次，再与邻导体二次交迭。

Description

有噪声抵消性能的通信用接插件终端阵列
本发明涉及电接插件终端阵列，而这种终端阵列具有抵消干扰的性能。这种接插件专用于无线电通信及电子工业，这些应用要求元部件的性能达到所谓5类工业标准。此类标准主要是为针对由于数据传输速率提高之后而对相应的接插件或硬件性能要求而制订的。
无线电通信工业协会(TIA)与电子工业协会(EIA)合作推出了此5类元部件的标准，其中此类标准的部件的性能已适用于100兆赫芝，其传输速率预期大致可达100兆比特/秒。在1992年8月此标准暂定名为TSB40。本发明涉及到上述要求的硬件，不过这些硬件只是通信系统中的一种重要部件，其它主要的部件则有传输电缆。因此，重要的是保证所采用的接插件或硬件适用于电缆的传输特性。这种电缆通常是高性能无屏蔽的，它满足EIA/TIA公报颁布的标准TSB-36。
高性能硬件的两个重要测试参数，即5类标准，是衰减和近末端串话(NEXT)损耗，所述衰减可定义为是对因连接硬件而引起的信号功率损耗的测量。可通过在连接接插件前后对一段100欧姆的扭绞对的测试引线进行扫频电压测量而求得此衰减。在最坏的情况下，接插件内的任一扭绞对的衰减不应超过下表1所列的值，其中对于5类标准，其值是近似等于2米电缆的衰减。
         表Ⅰ
        UTP硬件衰减
频率(兆赫芝)    类别(分贝)
        1.0    0.1
        4.0    0.1
        8.0    0.1
        10.0   0.1
        16.0   0.2
        20.0   0.2
        25.0   0.2
        31.25  0.2
        62.5   0.3
        100    0.4
一个更有意义的问题是所谓的近端串话损耗，它可定义为在接插件内信号从一个电路耦合到另一个电路的测量，它可通过对端接到接受试验的接插件的一小段100欧姆扭绞对测试电缆进行扫频电压测量求得。将一个被平衡的输入信号加到接插件的干扰对上，同时在测试电缆的近末端测量在被干扰对上引入的信号。换句话，NEXT损耗用来描述引起在一对扭绞对上的信号作为不希望的噪声出现在另一扭绞对上的信号耦合效应。看了表3上的测量数据的描述会对此有更清楚的了解。在任何情况下，对任何干扰与被干扰对的组合的最坏的情形的NEXT损耗，由下式确定：NEXT(F)≥NEXT(16)-20Log(F/16)。式中NEXT(16)是在16兆赫芝时的最小NEXT损耗，F是在1兆赫芝至最高基准频率范围内的频率(兆赫芝)，而NEXT(F)则是在该频率时的性能。
                表Ⅱ
        EIA/TIA文件TSB-40规定的
      UTP连接硬件的NEXT损耗极限值
     频率(兆赫芝) 类别(分贝)
        1.0        ＞65
        4.0        ＞65
        8.0        62
        10.0       60
        16.0       56
        20.0       54
        25         52
        31.25      50
        62.5       44
        100        40
美国专利No.5,186,647中公开的传送高频信号的电接插件代表了最新的发展，其主要目的是为了减少在接插件中的特定导体间的串话干扰。其最佳实施例是一个面板安装组合式插座，它包括一对引线框架，每个框架包括四个扁平细长导体。引体架一层压一层安装，它们的导体则都大体平行且互相紧靠。每个引线框架只有三个导体是互相重叠放置的；此时在一个指定的交迭区城中不会有电接触，因为在此重叠区域里有收纳导体的凹腔。在装配后，在扭绞对1-2,4-5，及7-8内各导体重叠而导体3与6则与任何导体都不重叠。
本发明的一个目的是提高接插件的性能，即减少在电导体的邻道信号通路之间的电感与电容耦合引起的噪声。
本发明的另一个目的是减少耦合到和来自附近电路由通过导体和端接引起的电气干扰。
为了实现上述目的，根据本发明一种电接插件终端阵列，包括多个金属导体(12)，金属导体(12)以基本上互相并行的选定结构排列，以减少在所选的导体对间的感性及容性耦合与电压不平衡，来增强高频传输特性，所述导体的一端以第一均匀间距分开，而另一端则以比第一均匀距离大的第二均匀间距分开；
其特征在于：中心部分(14)的导体各自无接触地重叠，且外部导体对相互各交迭一次，而各中心对导体则先互相交迭一次，然后继续与邻导体交迭二次，最后将整个阵列以模压方式嵌入在介电常数被选定的塑料材料(30,32)中。
同时，为了达到一致的高性能，本发明采用一个涉及所有导线有一个更复杂的安排，并又发现终端阵列显出可减少在电导体的邻道信号通路间的电感与电容耦合引起的噪声。此外，根据本发明的阵列，采用交叉导体的独特结构，也减少了耦合到和来自附近电路由通过导体和终端引起的电气干扰。上述特点在结合附图阅读了下面后详细描述和列举的数据之后将会更清楚。
现参阅附图描述本发明的实例。
图1示出了一对其间包括多个导体的载波带的顶视图和底视图，它们相背排组即构成本发明的最初最佳的导体阵列交叉构型。
图2是一个显示具有图1的导体的两个载波带的顶视图，它以背靠背的关系构成了新颖的4对式构型；
图3是具有图1导体的载波带的立体图；
图4是具有图2的四对重叠构型的载流带的立体图；
图5是一对具有图4的导体的载波带的剖面图，其中载波带已在形成和插入到介电外壳组件前模压嵌入；
图6是图5的模压嵌入组件的侧视图；
图7是形成了模压嵌入组件之后将要插入到用以接纳介电插头的壳体前的截面图；
图8是带有模压嵌入组件的介电插头接纳壳体的剖面图；
图9是按本发明构组的图8的组件的立体图；
图10是一个不同于图1构型的实施例的顶视和底视图；
图11是类似于图2的，用以表示不同于图10的背对背关系的四导体对构型的顶视图。
本发明是针对于一种电接插件的终端阵列，特别适合于生产用于安装印制电路板的接插型接插件。该接插件包括一个介电壳体，在封装到一个模压嵌入件内后，将配有4对电导体的两个终端阵列安装该介电壳体中，其中各导体大致并行排列。导体各对应端，诸如各信号端则分隔开一个第一均匀间距，而其它各对应端，则分隔开一个比上述第一均匀间距大的第二均匀间距。导体的排列还有这样特点：它们以无接触地重叠排列，各外部对的相应导体相互单个重叠，而中心对的各导体则相互交叉且每个导体与相邻导体交叉两次。采用上述这种导体排组，内导体对在100兆赫芝时呈现至少45.00分贝的串话损耗，此值比由5类性能要求的值高出许多。
电接插件终端阵列包括多个金属导体，为了提高高频传输性能，金属导体之间构组得可减少在选择的导体对间的电感和电容耦合及电压的不平衡，金属导体大致并行排列，相应的一些端分隔开一个第一均匀间距，而另一相应的各端则间隔形一个第二均匀间距，其中，中心部分以无接触重叠排置，而各外部对导体则相互单次交迭，且中心对的对应导体起初相交继之再向外穿过邻导体两次，因此整个阵列嵌入到有特定介电常数的塑制模中。
本发明是针对于一种电导体终端阵列，利用它们的独特的导体构型，可以减少因由在拟用于通信工业的电接插件的相邻信号通路之间的感性和容性耦合和电压不平衡形起的电噪声。通常的插头和插孔座型的接插件是由FCC细则控制的，以保证可使其能与各个厂家生产的设备相兼容。然而，遗憾的是，按EIA/TIA 56B标准制订的导体对性能对第5类要求的低近端的串话损耗来说并不是最佳的，而此种串话是用于描述引起在一对导体上的一部分信号作为出现在另一对上的不希望的信号的耦合效应。通常标准RJ45接插件在八对导体组件中关键的内部对，即在4-5→3-6对上的在100兆赫芝时的串话损耗为28分贝。如顶视导体的平面排列，则上述导体自左至右依次编号为1-8。此外，这些导体从“正1”到“负8”呈现交替的极性。
按照上述理解，现在参见上述7个附图。其中图1-4表示了导体的独特的排列或交迭模式的最佳实施例。图1左边示出了一对载波带10,10’，其间延伸着4个分开的导体12，通常该组件是从一条诸如磷青铜这种金属带上冲压制取的，虽然只示出了一种组合，但应该能理解到，载波带10,10’是可延绵的或无限的，其间可以有许多个相同的导体阵列或导体组。图1的右边是阵列的底视图。在两个视图中，导体12每个都有一个交迭部分14，在此处，本来并行的16端折向不同，但在相对端18又并行取向。最后，还给载波带10,10’开有对准孔20。将图1的各阵列背对背关系组排，并使对准孔20重合，则就得到图2的八导体组合阵列。
为避免在交迭区14导体间的接触，在图3和4可见到，导体的路径有了改变。在右手座标系统中，载波带10和图1的导体12阵列的所在平面定义为X-Y平面，而Z方向正交于该平面，导体不仅在X-Y面内弯折，且也在Z方向弯折，采用所示的方式，适当地弯折导线，可避免在交迭中相互抵触，从而增加了相消特性。作为一个最佳实施例，均匀交迭间隔为0.457厘米。
从图2可看得最清楚，8个导体阵列有一并行端16，即信号进入端，导体间有一均匀的预定间隔22，而相对的并行端18，即信号输出端，有一较宽的均匀间隔24。在一个最佳实施例中，间隔22可为0.102厘米。而间隔24为0.127厘米。已发现：出线导体间隔越宽，在导体体端18上对噪声越不敏感。
现再看图2的导体阵列的交迭模式，从图中可看到所有的导体自身都至少和另一导体交迭一次。在各外部对，即对1-2与7-8，在交迭区14内只是一单角度相交迭，然而，内导体3-4-5-6的交迭模式大不一样。导体4与5相互交迭一次，然后又各又与邻导体3或6相交迭两次。如下面的数据和描述可知，内导体3-4-5-6，特别是导体对4-5和3-6是引起最坏的串话问题的危险区域。
在准备将导体阵列包纳入合适的接插件壳体过程中，图2和4的阵列要经受嵌入模压操作，这是人所共知的工艺。在导体12的输出端18，将四导体的导体端18与载波带10分开，并将它弯折到原导体所在平面外，再将自由导体端18’重新在并行于前述平面第二平面内对齐，如图5所示。
在这结构中，采用模压技术中已知的分隔器，可保证精确的间隔，最好在交迭部分14的间隔为046厘米，对8导体阵列进行嵌入模压操作。具体地说，在导体的各交迭区14完全封装到塑料嵌入材料30内，材料30有一特定的介电常数。同时，导体端18,18’用与材料30相分间的第二嵌入物32封装。如图5和6所示，两个模嵌件30,32间只用导体段34相连。
借助于图7上箭头表示的方向来看图7上表示一个最佳实施例，其中嵌入件30,32可以构建成对壳体40是单一的嵌插组件。也就是说，嵌插件30以导体段34为轴转折90°，而突块42位于台肩44上。注意：载波带10,10’已移去，以显露组件两端的八段自由导体端。此外，如常规的构形一样，导体端16或信号进入端，被均匀弯折以形成多个悬臂。
待嵌入组件30,32适当就位后，即可如图8所示将组件推入壳体40并加以密封。最后，如图9所示，三个自由悬臂端16停靠在一个塑料梳46上，这与已知技术的情形一样，同时导体出线端18,18’则在壳体40下伸延，采用如常规的电子设备中，特别在将电接插件安装到印制电路板采用的固化工艺，将其与印制电路板(未示出)相连接众所周知，此时接插件最好是顶端进入式或是正交式接插件。
在描述了本发明的组件和导体构型之后，现在本介绍对本发明的图2的导体阵列构型与以美国专利No.5,186,647，图10中的实施为代表的现有技术导体构型所作的一系列对比性试验。此一系列试验包括监测各指定导体对从其它导体对感应的信号，其结果见下表Ⅲ。
                表Ⅲ
            串话损耗性能
          专利号No.5,186,647
频率    (图10)dB      (图2)dB
MHz     对4-5(被激励)/对3-6(被监测)
 1.00    93.3314        97.3065
 4.00    88.7672        81.9149
 8.00    80.4310        75.3686
 10.00   77.2740        73.1538
 16.00   70.9399        69.2165
 20.00   67.5173        67.0602
 25.00   63.5836        64.5806
 31.25   60.3561        62.3623
 62.50   48.6911        53.8529
100.00  40.7497        47.1532对4-5(被激励)/对1-2(被监测)
 1.00    92.5334    85.7093
 4.00    76.6522    74.9716
 8.00     70.6734    68.9445
 10.00    68.7324    66.9674
 16.00    64.6435    62.8523
 20.00    62.8112    60.8393
 25.00    60.9890    59.0475
 31.25    58.9276    57.1324
 62.50    53.1518    51.0579
100.00    49.3147    47.1061
对4-5(被激励)/对7-8(被监测)
 1.00     83.2705    97.9650
 4.00     77.0405    86.4777
 8.00     70.7822    79.3665
 10.00    68.9286    78.0388
 16.00    64.9881    74.6697
 20.00    62.9083    72.5942
 25.00    60.9954    70.0994
 31.25    59.1458    67.7972
 62.50    53.3385    60.7337
100.00   49.5746    55.2020
对3-6(被激励)/对1-2(被监测)
 1.00    92.5377    83.7281
 4.00    83.2459    72.1978
 8.00    76.4361    66.6110
 10.00    75.1494    64.6226
 16.00    70.4325    60.8918
 20.00    68.2740    58.7496
 25.00    66.3846    56.8689
 31.25    64.1155    54.8807
 62.50    56.1150    49.1693
100.00    49.9030    45.1703
对3-6(被激励)/对7-8(被监测)
 1.00    92.5310    81.6298
 4.00    81.6436    75.2836
 8.00    75.7535    69.4032
 10.00   74.3237    67.6514
 16.00   69.8561    63.5985
 20.00   67.9682    61.6780
 25.00   65.8369    59.8341
 31.25   63.5317    57.8692
 62.50   55.6964    51.9807
100.00  49.5146    47.8650
对1-2(被激励)/对7-8(被监测)
 1.00    96.8048    93.6805
 4.00    89.1507    97.9109
 8.00    85.2356    92.1488
10.00   83.7602    94.9492
 16.00    78.7884    101.859
 20.00    76.2289    103.382
 25.00    75.5069    89.4310
 31.25    72.2444    93.8751
 62.50    66.8171    87.5811
100.00    62.4969    88.8738
串话问题的最危险区域是在内部导体对，即，对4-5和3-6。表Ⅲ开头部分所列的数据针对美国专利No.5,186,647的构型的串话损耗性能与本发明的构型的性能作了比较。在每种情况下，随着频率的增加，串话损耗向着100兆赫芝时的EIA/TIA最小标准40.00分贝明显下降。可见，所试验的先有技术的接插件正好满足最低标准，而本发明在一个相比较的频率上却改进了7.00分贝。
在此最危险对之外的区域，两种接插件的性能一般都比较好。然而，引人注目的是，本发明的串话损耗性能都在45.00分贝以上，比5类最低标准的要求高出5.00分贝。
图10和11表示了本发明的另一种新颖的四对导体交迭构型的实施例。在该构型中，标识为导体54和56的前述导体4与5，起初互相交迭，然后在各自再进入相互间隔而并行取向之前又与邻导体3或6相交迭。扼要地说，本发明的这种独特的导体交迭构型显示了传统上用对1-2和7-8标识的各外导体的单次交迭，而内导体对3-6和4-5则至少有一次双交迭。

Claims (9)

1．一种电接插件终端阵列，包括多个金属导体(12)，金属导体(12)以基本上互相并行的选定结构排列，以减少在所选的导体对间的感性及容性耦合与电压不平衡，来增强高频传输特性，所述导体的一端以第一均匀间距分开，而另一端则以比第一均匀距离大的第二均匀间距分开；
其特征在于：中心部分(14)的导体各自无接触地重叠，且外部导体对相互各交迭一次，而各中心对导体则先互相交迭一次，然后继续与邻导体交迭二次，最后将整个阵列以模压方式嵌入在介电常数被选定的塑料材料(30,32)中。
2．根据权利要求1所述的电接插件端阵列，其中所述的第一均匀间距约为0.102厘米，而第二均匀间距为0.127厘米。
3．如权利要求1所述的电接插件终端阵列，其中导体重叠的间距约为0.046厘米。
4．如权利要求1所述的电接插件终端阵列，在所述嵌插模压件(30)中，导体如下方式重叠排列；在一处以所述第一均匀间距并行延伸，到另一处以所述第二均匀间距并行延伸。
5．如权利要求4所述的电接插件终端阵列，其中所述终端阵列被安置在接插件壳体(40)内，以获得一个印制电路板安装顶端引入线和直角的接插件。
6．如权利要求4所述的电接插件终端阵列，其特征在于，
中心部分(14)的导体各自无接触地重叠，且外部导体对相互交迭一次，而两对内部导体对则如此排组：至少其中两个导体与另外两个所述内部导体交迭，而整个阵列则以模压方式插入具有选定电介质常数的塑料材料(30,32)中。
7．如权利要求6所述的电接插件终端阵列，其中所述第一均匀距离约为0.102厘米，而第二均匀距离约为0.127厘米。
8．如权利要求6所述的电接插件，其中所述的导体重叠间距约为一个0.046厘米的均匀距离。
9．如权利要求6所述的电接插件终端阵列，其中在嵌插模压件(30)中，导体以如下方式重叠排列：在一处以所述第一均匀间距并行延伸，而在另一处以所述第二均匀间距并行延伸。
CN94108188A 1993-07-08 1994-07-06 有噪声抵消性能的通信用接插件终端阵列 Expired - Fee Related CN1044761C (zh)

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US5362257A (en) 1994-11-08
EP0633632A2 (en) 1995-01-11
CA2123260C (en) 2004-09-14
JPH07106010A (ja) 1995-04-21
JP3400123B2 (ja) 2003-04-28
KR100340693B1 (ko) 2002-11-18
EP0633632B1 (en) 2000-04-05
AU6308894A (en) 1995-01-19
CN1100879A (zh) 1995-03-29
DE69423824D1 (de) 2000-05-11
CA2123260A1 (en) 1995-01-09
AU673061B2 (en) 1996-10-24
EP0633632A3 (en) 1996-07-03
BR9402637A (pt) 1995-04-04
KR950004642A (ko) 1995-02-18
TW224547B (en) 1994-06-01

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