CN104471708B - 具有多个插入件的堆叠裸片组件 - Google Patents

具有多个插入件的堆叠裸片组件 Download PDF

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Publication number
CN104471708B
CN104471708B CN201280069303.8A CN201280069303A CN104471708B CN 104471708 B CN104471708 B CN 104471708B CN 201280069303 A CN201280069303 A CN 201280069303A CN 104471708 B CN104471708 B CN 104471708B
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China
Prior art keywords
insert
die
integrated circuit
interposer
circuit die
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Chinese (zh)
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CN104471708A (zh
Inventor
艾弗伦·C·吴
巴哈瑞·巴尼杰马利
拉乌那丹·沙威尔
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Xilinx Inc
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Xilinx Inc
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Priority claimed from US13/369,215 external-priority patent/US8704364B2/en
Priority claimed from US13/399,939 external-priority patent/US8704384B2/en
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Publication of CN104471708A publication Critical patent/CN104471708A/zh
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0652Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147Semiconductor insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385Assembly of a plurality of insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0655Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171Disposition
    • H01L2224/1718Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15151Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/157Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/37Effects of the manufacturing process
    • H01L2924/37001Yield

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
CN201280069303.8A 2012-02-08 2012-12-03 具有多个插入件的堆叠裸片组件 Active CN104471708B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US13/369,215 2012-02-08
US13/369,215 US8704364B2 (en) 2012-02-08 2012-02-08 Reducing stress in multi-die integrated circuit structures
US13/399,939 US8704384B2 (en) 2012-02-17 2012-02-17 Stacked die assembly
US13/399,939 2012-02-17
PCT/US2012/067543 WO2013119309A1 (en) 2012-02-08 2012-12-03 Stacked die assembly with multiple interposers

Publications (2)

Publication Number Publication Date
CN104471708A CN104471708A (zh) 2015-03-25
CN104471708B true CN104471708B (zh) 2017-05-24

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EP (1) EP2812919B1 (enExample)
JP (1) JP5916898B2 (enExample)
KR (1) KR101891862B1 (enExample)
CN (1) CN104471708B (enExample)
WO (1) WO2013119309A1 (enExample)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140138815A1 (en) * 2012-11-20 2014-05-22 Nvidia Corporation Server processing module
US20150221614A1 (en) * 2014-02-06 2015-08-06 Sehat Sutardja High-bandwidth dram using interposer and stacking
US20150279431A1 (en) * 2014-04-01 2015-10-01 Micron Technology, Inc. Stacked semiconductor die assemblies with partitioned logic and associated systems and methods
US9402312B2 (en) 2014-05-12 2016-07-26 Invensas Corporation Circuit assemblies with multiple interposer substrates, and methods of fabrication
US9666559B2 (en) 2014-09-05 2017-05-30 Invensas Corporation Multichip modules and methods of fabrication
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
CN114741344B (zh) * 2016-02-02 2024-08-09 赛灵思公司 有源接有源可编程器件
TWI628742B (zh) * 2016-07-21 2018-07-01 南亞科技股份有限公司 堆疊式封裝結構
CN109564914B (zh) * 2016-08-15 2020-06-30 赛灵思公司 用于堆叠硅互连(ssi)技术集成的独立接口
US10784121B2 (en) 2016-08-15 2020-09-22 Xilinx, Inc. Standalone interface for stacked silicon interconnect (SSI) technology integration
US10141938B2 (en) * 2016-09-21 2018-11-27 Xilinx, Inc. Stacked columnar integrated circuits
US11183458B2 (en) 2016-11-30 2021-11-23 Shenzhen Xiuyuan Electronic Technology Co., Ltd Integrated circuit packaging structure and method
US12341096B2 (en) 2016-12-29 2025-06-24 Intel Corporation Bare-die smart bridge connected with copper pillars for system-in-package apparatus
DE112016007575T5 (de) * 2016-12-29 2019-10-17 Intel IP Corporation Smarte ungehäuster-die-brücke, verbunden mit kupfersäulen für system-in-gehäuse-vorrichtung
US12424531B2 (en) 2017-03-14 2025-09-23 Mediatek Inc. Semiconductor package structure
US11171113B2 (en) 2017-03-14 2021-11-09 Mediatek Inc. Semiconductor package structure having an annular frame with truncated corners
US11264337B2 (en) 2017-03-14 2022-03-01 Mediatek Inc. Semiconductor package structure
US11387176B2 (en) 2017-03-14 2022-07-12 Mediatek Inc. Semiconductor package structure
US10784211B2 (en) 2017-03-14 2020-09-22 Mediatek Inc. Semiconductor package structure
US11362044B2 (en) 2017-03-14 2022-06-14 Mediatek Inc. Semiconductor package structure
US20210018952A1 (en) * 2017-06-02 2021-01-21 Ultramemory Inc. Semiconductor module
US10497689B2 (en) * 2017-08-04 2019-12-03 Mediatek Inc. Semiconductor package assembly and method for forming the same
KR102498883B1 (ko) * 2018-01-31 2023-02-13 삼성전자주식회사 전류를 분산시키는 관통 전극들을 포함하는 반도체 장치
US11652060B2 (en) 2018-12-28 2023-05-16 Intel Corporation Die interconnection scheme for providing a high yielding process for high performance microprocessors
EP3709344B1 (en) * 2019-03-14 2024-05-08 MediaTek Inc. Semiconductor package structure
KR102679095B1 (ko) * 2019-05-30 2024-07-01 삼성전자주식회사 반도체 패키지
US11735533B2 (en) 2019-06-11 2023-08-22 Intel Corporation Heterogeneous nested interposer package for IC chips
US12080643B2 (en) * 2019-09-26 2024-09-03 Intel Corporation Integrated circuit structures having differentiated interconnect lines in a same dielectric layer
DE102021104688A1 (de) 2020-04-30 2021-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Stromverteilungsstruktur und verfahren
US12255148B2 (en) * 2020-04-30 2025-03-18 Taiwan Semiconductor Manufacturing Company, Ltd. Power distribution structure and method
CN111863780A (zh) * 2020-07-17 2020-10-30 北京灵汐科技有限公司 封装结构及电子设备
KR20220022242A (ko) * 2020-08-18 2022-02-25 삼성전자주식회사 회로 기판 모듈 및 이를 포함하는 전자 장치
CN116888735A (zh) * 2021-02-05 2023-10-13 大日本印刷株式会社 半导体封装件、半导体封装件的制造方法以及中介层组
US11862481B2 (en) 2021-03-09 2024-01-02 Apple Inc. Seal ring designs supporting efficient die to die routing
US20220320042A1 (en) * 2021-03-30 2022-10-06 Advanced Micro Devices, Inc. Die stacking for modular parallel processors
CN114242669B (zh) * 2022-02-28 2022-07-08 甬矽电子(宁波)股份有限公司 堆叠封装结构和堆叠结构封装方法
KR20240151232A (ko) * 2022-03-01 2024-10-17 그래프코어 리미티드 데이터 라우팅 로직을 구비한 디램 모듈
US20230352464A1 (en) * 2022-04-29 2023-11-02 Intel Corporation Scalable package architecture using reticle stitching and photonics for zetta-scale integrated circuits
CN114899185B (zh) * 2022-07-12 2022-12-02 之江实验室 一种适用于晶圆级异质异构芯粒的集成结构和集成方法
CN116775555B (zh) * 2023-06-27 2025-03-18 无锡中微亿芯有限公司 一种具有高存储带宽的多裸片存算架构fpga

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1388584A (zh) * 2001-05-25 2003-01-01 日本电气株式会社 半导体器件
CN101295693A (zh) * 2007-04-24 2008-10-29 恩益禧电子股份有限公司 半导体器件
CN101877341A (zh) * 2009-04-29 2010-11-03 国际商业机器公司 可返修的电子器件组件及方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4074342A (en) * 1974-12-20 1978-02-14 International Business Machines Corporation Electrical package for lsi devices and assembly process therefor
US5672546A (en) * 1995-12-04 1997-09-30 General Electric Company Semiconductor interconnect method and structure for high temperature applications
WO2002082540A1 (en) * 2001-03-30 2002-10-17 Fujitsu Limited Semiconductor device, method of manufacture thereof, and semiconductor substrate
JP4380130B2 (ja) * 2002-09-13 2009-12-09 ソニー株式会社 半導体装置
JP4419049B2 (ja) * 2003-04-21 2010-02-24 エルピーダメモリ株式会社 メモリモジュール及びメモリシステム
JP4343044B2 (ja) * 2004-06-30 2009-10-14 新光電気工業株式会社 インターポーザ及びその製造方法並びに半導体装置
JP4581768B2 (ja) * 2005-03-16 2010-11-17 ソニー株式会社 半導体装置の製造方法
JP2009135397A (ja) * 2007-10-31 2009-06-18 Panasonic Corp 半導体装置
US8064224B2 (en) * 2008-03-31 2011-11-22 Intel Corporation Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same
US8008764B2 (en) * 2008-04-28 2011-08-30 International Business Machines Corporation Bridges for interconnecting interposers in multi-chip integrated circuits
US20110180317A1 (en) * 2009-09-11 2011-07-28 Eiji Takahashi Electronic component package, method for producing the same and interposer
JP4649531B1 (ja) * 2009-12-08 2011-03-09 新光電気工業株式会社 電子装置の切断方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1388584A (zh) * 2001-05-25 2003-01-01 日本电气株式会社 半导体器件
CN101295693A (zh) * 2007-04-24 2008-10-29 恩益禧电子股份有限公司 半导体器件
CN101877341A (zh) * 2009-04-29 2010-11-03 国际商业机器公司 可返修的电子器件组件及方法

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KR101891862B1 (ko) 2018-08-24
EP2812919A1 (en) 2014-12-17
JP5916898B2 (ja) 2016-05-11
KR20140111716A (ko) 2014-09-19
WO2013119309A1 (en) 2013-08-15
JP2015507372A (ja) 2015-03-05
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