CN104465543B - 模塑料中具有凹槽的集成扇出封装结构 - Google Patents

模塑料中具有凹槽的集成扇出封装结构 Download PDF

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CN104465543B
CN104465543B CN201410414756.0A CN201410414756A CN104465543B CN 104465543 B CN104465543 B CN 104465543B CN 201410414756 A CN201410414756 A CN 201410414756A CN 104465543 B CN104465543 B CN 104465543B
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top surface
die
metal pad
tube core
moulding compound
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CN104465543A (zh
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蔡柏豪
郑礼辉
洪瑞斌
林俊成
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

模塑料中具有凹槽的集成扇出封装结构。一种封装件包括第一管芯和第二管芯。第一管芯包括第一衬底和第一衬底上方的第一金属焊盘。第二管芯包括第二衬底和第二衬底上方的第二金属焊盘。在模塑料中模制第一管芯和第二管芯。模塑料具有介于第一管芯和第二管芯之间的第一部分、以及可形成围绕第一部分的环的第二部分。第一部分和第二部分位于第一管芯的相对侧。第一部分具有第一顶面。第二部分具有高于第一顶面的第二顶面。

Description

模塑料中具有凹槽的集成扇出封装结构
技术领域
本发明涉及半导体领域,更具体地,涉及模塑料中具有凹槽的集成扇出封装结构。
背景技术
随着半导体技术的演进,半导体芯片/管芯变得越来越小。与此同时,需要将更多的功能集成在半导体管芯中。因此,半导体管芯需要越来越多数量的I/O焊盘封装在较小的区域内,并且I/O焊盘的密度随着时间迅速增加。因此,半导体管芯的封装变得更困难,其对封装的成品率带来负面的影响。
常规的封装技术可被分成两种类别。在第一类别中,先封装晶圆上的管芯再进行切割。这种封装技术具有一些优势特征,如,较高的生产能力和较低的成本。此外,需要较少的底层填料或模塑料。然而,这种封装技术也存在一些缺陷。如上所述,管芯的尺寸变得越来越小,并且各自的封装件只能是扇进型封装件,其中,每个管芯的I/O焊盘被直接限制在各自管芯的表面上方。因管芯的受限区域,由于限制I/O焊盘的间距,导致I/O焊盘的数量也受限制。如果要增大焊盘的间距,可能发生焊料桥接。此外,根据固定球尺寸的要求,焊料球必须具有一定的尺寸,这样进而限制可封装在管芯表面上的焊料球的数量。
在封装的另一个类别中,先从晶圆上切割管芯再进行封装,并且只封装“已知良好管芯”。这种封装技术的优势特征是有可能形成扇出封装件,也就是说,管芯上的I/O焊盘可重分布在比管芯大的区域内,因此,可增加封装在管芯的表面上的I/O焊盘的数量。
发明内容
为解决上述问题,本发明提供了一种封装件,包括:第一管芯,包括第一衬底和第一衬底上方的第一金属焊盘;第二管芯,包括第二衬底;以及模塑料,在其内模制第一管芯和第二管芯,其中,模塑料包括:第一部分,介于第一管芯和第二管芯之间,其中,第一部分包括第一顶面;以及第二部分,其中,第一部分和第二部分位于第一管芯的相对侧,并且其中,第二部分具有高于第一顶面的第二顶面。
其中,模塑料的第二部分包含在模塑料的环部分中,其中,环部分围绕模塑料的第一部分、第一管芯以及第二管芯,并且其中,环部分的整个顶面与第二顶面共平面。
其中,第一顶面和第二顶面之间的高度差介于约2μm至约35μm之间。
其中,第一管芯还包括:钝化层,覆盖第一金属焊盘的边缘部分,并且,第一金属焊盘的中心部分没有被钝化层覆盖,其中,第一顶面与钝化层的顶面大致齐平。
其中,第一管芯还包括:钝化层,覆盖第一金属焊盘的边缘部分,并且,第一金属焊盘的中心部分没有被钝化层覆盖,其中,第一顶面高于钝化层的顶面。
其中,第一管芯还包括:钝化层,覆盖第一金属焊盘的边缘部分,并且第一金属焊盘的中心部分没有被钝化层覆盖,其中,第一顶面低于钝化层的顶面。
该封装件还包括:聚合物层,持续地从与第一管芯重叠的区延伸进与第二管芯重叠的区,其中,第一顶面与聚合物层的底面相接触;第一重布线,穿过聚合物以电连接至第一金属焊盘;第二金属焊盘,位于第二管芯内且位于第二衬底的上方;以及第二重布线,穿过聚合物层以电连接至第二金属焊盘。
此外,还提供了一种封装件,包括:第一管芯,包括:第一衬底;第一金属焊盘,位于第一衬底的上方;以及第一钝化层,覆盖第一金属焊盘的边缘部分,并且第一金属焊盘的中心部分没有被第一钝化层覆盖,其中,第一钝化层包括第一顶面;第二管芯,包括:第二衬底;第二金属焊盘,位于第二衬底的上方;以及第二钝化层,覆盖第二金属焊盘的边缘部分,并且,第二金属焊盘的中心部分没有被第二钝化层覆盖,其中,第二钝化层包括第二顶面;模塑料,在其内模制第一管芯和第二管芯,其中,模塑料包括:第一部分,位于第一管芯和第二管芯之间,其中,第一部分包括第三顶面;以及第二部分,形成围绕模塑料的第一部分、第一管芯和第二管芯的环,其中,第二部分具有高于第三顶面的第四顶面。
其中,模塑料的第一部分的相对端持续地连接至模塑料的第二部分,并且其中,第一部分和第二部分由相同的材料形成。
其中,第三顶面齐平于或低于第一顶面和第二顶面中的一个。
该封装件还包括:聚合物层,持续地从与第一管芯重叠的区延伸进与第二管芯重叠的区,其中,第三顶面与聚合物层的底面相接触;第一重布线,穿过聚合物层以电连接至第一金属焊盘;以及第二重布线,穿过聚合物层以电连接至第二金属焊盘。
其中,第一顶面和第二顶面与聚合物层的底面相接触。
其中,第一管芯和第二管芯具有不同的结构。
其中,第四顶面高于第三顶面,差值介于约2μm至约35μm之间。
此外,还提供了一种方法,包括:在载体上方设置第一管芯,其中,第一管芯包括第一衬底和位于第一衬底上方的第一金属焊盘;在载体上方设置第二管芯,其中,第二管芯包括第二衬底和位于第二衬底上方的第二金属焊盘;在模塑料中模制第一管芯和第二管芯;研磨模塑料;在研磨之后,开槽模塑料的第一部分,其中,第一部分介于第一管芯和第二管芯之间,并且其中,模塑料的第二部分没有被开槽;以及重布线形成于第一金属焊盘和第二金属焊盘的上方且电连接至第一金属焊盘和第二金属焊盘。
其中,通过激光钻孔进行开槽。
其中,开槽之后,模塑料的第一部分的底部没有被去除。
其中,第一保护膜和第二保护膜分别覆盖第一管芯和第二管芯,其中,当露出第一保护膜和第二保护膜时,停止研磨,并且其中,方法还包括:研磨之后,去除第一保护膜和第二保护膜以分别露出第一管芯和第二管芯,其中,去除之后,露出第一金属焊盘和第二金属焊盘。
该方法还包括:形成重布线之后,电连接件形成于重布线的上方且电连接至重布线;以及进行管芯切割以形成包括第一管芯、第二管芯、以及模塑料的第一和第二部分的封装件。
该方法还包括从载体上解接合第一管芯、第二管芯、以及模塑料。
附图说明
为了更全面地理解实施例及其优点,现将结合附图所进行的描述作为参考,其中:
图1至图12A是根据一些示例性实施例的制造集成扇出(InFO)封装件的中间阶段的截面图;以及
图12B示出了根据一些示例性实施例的InFO封装件的俯视图。
具体实施方式
下面,详细讨论本发明各实施例的制造和使用。然而,应该理解,实施例提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式,而不用于限制本发明的范围。
根据各种示例性实施例提供了包括扇出重布线的集成扇出(InFO)封装件及其形成方法。示出了形成InFO封装件的中间阶段。讨论了实施例的变化。贯穿各种视图和示出的实施例,相同的参考符号用于指代相同的元件。
图1至图12A是根据一些示例性实施例的制造封装件结构的中间阶段的截面图。参照图1,提供了载体20,并且聚合物基极层22层压在载体20上。载体20可以是底版玻璃载体、底版陶瓷载体等。聚合物基极层22可由Ajinomoto Buildup Film(ABF)、聚酰亚胺、聚苯并恶唑(PBO)、苯并环丁烯(BCB)、焊料抗蚀(SR)膜、管芯附着膜(DAF)等,但是可使用其他类型的聚合物。聚合物基极层22具有平顶面。
图2示出了设置在聚合物基极层22上方的器件管芯100和200。在一些实施例中,附加粘接层(未示出)设置在器件管芯100和200的每个的下方,以将器件管芯100和200分别粘接至聚合物基极层22。在可选实施例中,没有设置附加粘接层,并且器件管芯100和200与聚合物基极层22相接触。器件管芯100和200可以是其内包括有逻辑晶体管的逻辑器件管芯。在一些示例性实施例中,将器件管芯100和200设计用于移动应用,并且可包括中央计算单元(CPU)管芯、电源管理集成电路(PMIC)管芯等。器件管芯100和200可具有彼此不同的结构,或可具有彼此相通的结构。器件管芯100和200均包括与粘接层相接触的半导体衬底120/220(参照图12A),其中,半导体衬底120/220的背面与粘接层相接触。在一些实施例中,半导体衬底120和220可以是硅衬底。在一些实施例中,每个器件管芯100和一个相邻器件管芯200彼此靠近设置,例如,距离D1小于约150μm。距离D1也可大于约25μm。
图2和图3原理性示出的器件管芯100和200示出了器件管芯100的截面图,其中,示出了更多细节。如图3所示,器件管芯100包括半导体衬底120。半导体衬底120可以是块体硅衬底或绝缘体上硅衬底,但是,也可使用包括族III、族IV和族V元素的其他半导体材料。诸如晶体管(原理性示出的121)的集成电路器件形成在半导体衬底120的表面处。
器件管芯100还可包括位于半导体衬底120上方的层间介电质(ILD)122以及位于ILD122上方的金属层124。金属线126和通孔128形成在介电层125中。在下文中,同一水平上的金属线的组合被称为金属层。因此,多个金属层124通过通孔128相互连接。在一些实施例中,介电层125由低k介电材料形成。例如,低k介电材料的介电常数(k值)可小于约3.0或约2.5。金属线126和通孔128可由铜或铜合金形成,但是也可由其他金属形成。
器件管芯200(图2)可具有与器件管芯100相似的结构,但是,器件管芯100和200的结构也可彼此不同。因此,可以发现,器件管芯200内的部件的材料和结构可参照图3所述的器件管芯100内的相同部件。器件管芯200内的相同部件被标示为以数字“2”开头的参考数字,这些部件对应于器件管芯100内的具有以数字“1”开头的参考数字的部件。图7和图12A原理性示出了器件管芯200内的一些部件
仍参照图3,金属焊盘130形成在金属层124的上方,且可电连接至金属线126和通孔128。金属焊盘130可以是铝焊盘或铝铜焊盘,因此,在下文中,可选地被称为铝焊盘130,但是,可使用其他金属材料。钝化层132形成在金属层124的上方。钝化层132的部分可覆盖铝焊盘130的边缘部分。通过钝化层132内的开口露出铝焊盘130的中心部分。钝化层132可以是单层或复合层,并且可由无孔材料形成。在一些实施例中,钝化层132是包括氧化硅层(未示出)和位于氧化硅层上方的氮化硅层(未示出)的复合层。可选地,钝化层132由非掺杂硅酸盐玻璃(USG)、氮氧化硅等形成。在整篇描述中,钝化层132的顶面132A在下文中被称为器件管芯100的顶面。
保护膜134位于钝化层132和金属焊盘130的上方。在一些实施例中,保护膜134包括背研磨(BG)带、包括聚酰亚胺和粘接剂的层压带、紫外线(UV)带等。保护膜134可以是用于制造器件管芯100的相同膜。例如,在器件管芯100的形成中,形成钝化层132之后,背研磨带粘接至钝化层132,这样使得衬底120的背面被研磨,以薄化管芯100和各自的晶圆。研磨之后,各自的晶圆连同背研磨带被切割,以将管芯100和其他管芯分隔开。剩下的一块背研磨带粘接至钝化层132,且成为保护膜134。
参照图4,模制材料42模制在器件管芯100和200上。模制材料42填充器件管芯100和200之间的间隙,并且可与聚合物基极层22相接触。模制材料42可包括模塑料、模制底层填料、环氧基树脂、或树脂。模制材料42的顶面高于保护膜134和234的顶面,其分别覆盖器件管芯100和200。
接着,进行研磨步骤以去除模制材料42的多余部分,直到露出保护膜134和234。图5示出了最终结构。模制材料42包括器件管芯100和200之间的部分42A以及围绕部分42A和器件管芯100和200的部分42B(参照图12B)。模制材料部分42A具有与保护膜134和234的顶面大致齐平的顶面。因此,模制材料部分42A包括位于器件管芯100的顶面132A和/或器件管芯200的顶面232A上方的顶部分42’。例如,模制材料部分42A的顶部分42’的厚度T1可介于约3μm至约40μm的范围内。研磨之后,模制材料42具有高度H1,其可大于约80μm,并且可介于约80μm至约280μm的范围内。
图6示出了开槽模制材料部分42A。在一些实施例中,通过激光钻孔进行开槽,如原理性所示。围绕部分42B没有被开槽。因此,剩余的模制材料部分42A的顶面42A1低于围绕部分42B的顶面42B1。
图7示出了器件管芯100和200以及模制材料42A的放大图。如图7所示,开槽之后,模制材料部分42A的顶面42A1可与器件管芯100的顶面132A和/或器件管芯200的顶面232A齐平。在可选实施例中,顶面42A1低于顶面132A和/或232A。如图所示,顶面42A1也可低于金属焊盘130和/或230的底面。虚线42示出了各种实施例中顶面42A1的几种可能性位置。或者,剩余的模制材料部分42A具有高度H3,其中,高度H3可大于、等于或小于器件管芯100的高度H2(厚度)和器件管芯200的高度H2’。在一些实施例中,高度差(H1-H3)介于约2μm至约35μm之间。在一些示例性实施例中,高度H3可大于约50μm。
如图8所示,然后去除保护膜134和234。露出钝化层132和232(参照图7)和金属焊盘130和230。应该理解,如果模制材料部分42A没有被开槽,如虚线45所示的模制材料部分42A的突出部分将形成突出于管芯100和200的顶面的隆起部,该隆起部位于模制材料部分42A的相对侧。隆起部可具有等于保护膜134和234的厚度的高度。因此,隆起部的高度可介于约3μm至约40μm的范围内。因此,隆起部形成长且高的壁部,其长度等于器件管芯100和200的长度。因此,如果隆起部没有被去除,那么,隆起部将影响后续的光刻工艺,并且可导致最终封装件内发生破裂。
接着,参照图9,重布线(RDL)44形成在模制材料的上方以连接至金属焊盘130和230。RDL44也可与金属焊盘130和230互连。根据各种实施例,一个或多个介电层46形成在图8所示结构的上方,并且RDL44形成在介电层46中。图9示出了RDL44和介电层46的原理图,但是,在图12A中可发现RDL44和介电层46的细节。在一些示例性形成工艺中,一层RDL44和介电层46的形成包括:形成底版铜晶种层、在底版铜晶种层的上方形成且图案化掩模层、进行电镀以形成RDL44、去除掩模层、以及进行闪蚀刻以去除底版铜晶种层的没有被RDL44覆盖的部分。RDL44可包括金属或金属合金,金属合金包括铝、铜、钨、镍和/或其合金。
图12A示出了RDL44和介电层46的更为详细的视图。在图12中,示出了两层RDL44(包括44A和44B)。在这些实施例中的介电层46(包括46A和46B)可包括聚酰亚胺、苯并环丁烯(BCB)、聚苯并恶唑(PBO)等。可选地,介电层46可包括非有机介电材料,如氧化硅、氮化硅、碳化硅、氮氧化硅等。
图10示出了根据一些示例性实施例的电连接件48的形成。电连接件48的形成可包括:在RDL44上形成凸块下金属化层(UBM)47、在UBM47的露出部分上设置焊料球、以及然后回流焊料球。在可选实施例中,电连接件48的形成包括:进行电镀步骤以在RDL44或UBM47的上方形成焊料区、以及然后回流焊料区。电连接件48也可包括金属柱、或金属柱和焊料盖,其也可通过电镀形成。在电连接件48是焊料球的实施例中,焊料球48的下部可模制在模塑料54中,同时露出焊料球48的上部。在通篇描述中,包括器件管芯100和200的组合结构、模制材料42和上面的RDL44和介电层46被称为封装件50,其可以是复合晶圆。
接着,封装件50从载体20上解接合(de-bonding)。也从封装件50上去除聚合物基极层22和粘接层(如果有)。图11示出了最终结构。在可选实施例中,聚合物基极层22没有被去除,并且留在最终封装件内。解接合之后,露出模制材料42和器件管芯100和200的背面。接着,封装件50进一步粘合至切割带52,其中,电连接件48朝向切割带52且可与切割带52相接触。
接着,封装件50切割成多个封装件60。图12A和12B分别示出了一个封装件60的截面图和俯视图。如图12A所示,可以是聚合物层的一个或多个介电层46(包括46A和46B)位于钝化层132和232的上方,并且持续地从器件管芯100上方的区直接延伸到器件管芯200上方的区。介电层46可以是包括聚酰亚胺、PBO、BCB等的聚合物层。RDL44可包括一个或多个层,如RDL44A和RDL44B,其形成在介电层46中。模制材料部分42A的顶面42A1与介电层46A的底面相接触。模制材料部分42A的顶面42A1低于模制材料42的部分42B的顶面42B1,部分42B形成围绕器件管芯100和200的环。
如图12B所示,示出了模制材料42的部分42A和42B。部分42B形成环绕部分42A和器件管芯100和200的环。此外,模制材料42A的相对端连接至环部分42B以形成持续的模制材料。
在本发明的实施例中,通过开槽同一个封装件内的紧密设置的器件管芯之间的模塑料的部分,去除模制材料的隆起部。消除了隆起部导致的工艺困难(如,对后续光刻工艺)以及隆起部导致的封装件破裂。
根据一些实施例,封装件包括第一管芯和第二管芯。第一管芯包括第一衬底和位于第一衬底上方的第一金属焊盘。第二管芯包括第二衬底和位于第二衬底上方的第二金属焊盘。在模塑料内模制第一管芯和第二管芯。模塑料具有第一管芯和第二管芯之间的第一部分、以及第二部分,第二部分可形成围绕第一部分的环。第一部分和第二部分位于第一管芯的相对侧。第一部分具有第一顶面。第二部分具有高于第一顶面的第二顶面。
根据其他实施例,封装件包括第一管芯和第二管芯。第一管芯包括第一衬底、位于第一衬底上方的第一金属焊盘、以及覆盖第一金属焊盘的边缘部分的第一钝化层,并且,第一金属焊盘的中心部分没有被第一钝化层覆盖。第一钝化层具有第一顶面。第二管芯包括第二衬底、位于第二衬底上方的第二金属焊盘以及覆盖第二金属焊盘的边缘部分的第二钝化层,并且,第二金属焊盘的中心部分没有被第二钝化层覆盖。第二钝化层包括第二顶面。在模塑料中模制第一管芯和第二管芯。模塑料包括第一管芯和第二管芯之间的第一部分、以及形成围绕模塑料的第一部分、第一管芯、和第二管芯的环的第二部分,其中,第一部分包括第三顶面。第二部分具有高于第一顶面的第二顶面。
根据其他实施例,一种方法包括在载体的上方设置第一管芯和第二管芯,其中,第一管芯包括第一衬底和位于第一衬底上方的第一金属焊盘,并且第二管芯包括第二衬底和位于第二衬底上方的第二金属焊盘。方法还包括在模塑料中模制第一管芯和第二管芯以及研磨模塑料。在研磨之后,开槽模塑料的第一部分,其中,第一部分介于第一管芯和第二管芯之间,并且其中,模塑料的第二部分没有被开槽。然后,重布线形成于第一金属焊盘和第二金属焊盘的上方且电连接至第一金属焊盘和第二金属。
尽管已经详细地描述了实施例及其优势,但是应该理解,在不背离由所附权利要求限定的实施例的精神和范围的情况下,可以做出各种改变、替代和变化。此外,本申请的范围不旨在限于说明书中描述的工艺、机器、制造、物质组成、工具、方法和步骤的特定实施例。作为本领域的技术人员容易理解,通过本发明,可以使用现有的或今后开发的用于实施与在此所描述的相应实施例基本相同的功能或者实现基本相同的结构的工艺、机器、制造、物质组成、工具、方法或步骤。因此,所附权利要求应该包括在这些工艺、机器、制造、物质组成、工具、方法或步骤的范围内。此外,每个权利要求构成单独的实施例,并且各个权利要求和实施例的结合在本发明的范围内。

Claims (19)

1.一种封装件,包括:
第一管芯,包括第一衬底和所述第一衬底上方的第一金属焊盘;
第二管芯,包括第二衬底;以及
模塑料,在其内模制所述第一管芯和所述第二管芯,其中,所述模塑料包括:
第一部分,介于所述第一管芯和所述第二管芯之间,其中,所述第一部分包括第一顶面;以及
第二部分,其中,所述第一部分和所述第二部分位于所述第一管芯的相对侧,并且其中,所述第二部分具有高于所述第一顶面的第二顶面,
其中,所述模塑料的第二部分包含在所述模塑料的环部分中,其中,所述环部分围绕所述模塑料的第一部分、所述第一管芯以及所述第二管芯,并且其中,所述环部分的整个顶面与所述第二顶面共平面。
2.根据权利要求1所述的封装件,其中,所述第一顶面和所述第二顶面之间的高度差介于2μm至35μm之间。
3.根据权利要求1所述的封装件,其中,所述第一管芯还包括:
钝化层,覆盖所述第一金属焊盘的边缘部分,并且,所述第一金属焊盘的中心部分没有被所述钝化层覆盖,其中,所述第一顶面与所述钝化层的顶面齐平。
4.根据权利要求1所述的封装件,其中,所述第一管芯还包括:
钝化层,覆盖所述第一金属焊盘的边缘部分,并且,所述第一金属焊盘的中心部分没有被所述钝化层覆盖,其中,所述第一顶面高于所述钝化层的顶面。
5.根据权利要求1所述的封装件,其中,所述第一管芯还包括:
钝化层,覆盖所述第一金属焊盘的边缘部分,并且所述第一金属焊盘的中心部分没有被所述钝化层覆盖,其中,所述第一顶面低于所述钝化层的顶面。
6.根据权利要求1所述的封装件,还包括:
聚合物层,持续地从与所述第一管芯重叠的区延伸进与所述第二管芯重叠的区,其中,所述第一顶面与所述聚合物层的底面相接触;
第一重布线,穿过所述聚合物以电连接至所述第一金属焊盘;
第二金属焊盘,位于所述第二管芯内且位于所述第二衬底的上方;以及
第二重布线,穿过所述聚合物层以电连接至所述第二金属焊盘。
7.一种封装件,包括:
第一管芯,包括:
第一衬底;
第一金属焊盘,位于所述第一衬底的上方;以及
第一钝化层,覆盖所述第一金属焊盘的边缘部分,并且所述第一金属焊盘的中心部分没有被所述第一钝化层覆盖,其中,所述第一钝化层包括第一顶面;
第二管芯,包括:
第二衬底;
第二金属焊盘,位于所述第二衬底的上方;以及
第二钝化层,覆盖所述第二金属焊盘的边缘部分,并且,所述第二金属焊盘的中心部分没有被所述第二钝化层覆盖,其中,所述第二钝化层包括第二顶面;
模塑料,在其内模制所述第一管芯和所述第二管芯,其中,所述模塑料包括:
第一部分,位于所述第一管芯和所述第二管芯之间,其中,所述第一部分包括第三顶面;以及
第二部分,形成围绕所述模塑料的第一部分、所述第一管芯和所述第二管芯的环,其中,所述第二部分具有高于所述第三顶面的第四顶面。
8.根据权利要求7所述的封装件,其中,所述模塑料的第一部分的相对端持续地连接至所述模塑料的第二部分,并且其中,所述第一部分和所述第二部分由相同的材料形成。
9.根据权利要求7所述的封装件,其中,所述第三顶面齐平于或低于所述第一顶面和所述第二顶面中的一个。
10.根据权利要求7所述的封装件,还包括:
聚合物层,持续地从与所述第一管芯重叠的区延伸进与所述第二管芯重叠的区,其中,所述第三顶面与所述聚合物层的底面相接触;
第一重布线,穿过所述聚合物层以电连接至所述第一金属焊盘;以及
第二重布线,穿过所述聚合物层以电连接至所述第二金属焊盘。
11.根据权利要求10所述的封装件,其中,所述第一顶面和所述第二顶面与所述聚合物层的底面相接触。
12.根据权利要求7所述的封装件,其中,所述第一管芯和所述第二管芯具有不同的结构。
13.根据权利要求7所述的封装件,其中,所述第四顶面高于所述第三顶面,差值介于2μm至35μm之间。
14.一种形成封装件的方法,包括:
在载体上方设置第一管芯,其中,所述第一管芯包括第一衬底和位于所述第一衬底上方的第一金属焊盘;
在所述载体上方设置第二管芯,其中,所述第二管芯包括第二衬底和位于所述第二衬底上方的第二金属焊盘;
在模塑料中模制所述第一管芯和所述第二管芯;
研磨所述模塑料;
在所述研磨之后,开槽所述模塑料的第一部分,其中,所述第一部分介于所述第一管芯和所述第二管芯之间,并且其中,所述模塑料的第二部分没有被开槽;以及
重布线形成于所述第一金属焊盘和所述第二金属焊盘的上方且电连接至所述第一金属焊盘和所述第二金属焊盘。
15.根据权利要求14所述的方法,其中,通过激光钻孔进行开槽。
16.根据权利要求14所述的方法,其中,所述开槽之后,所述模塑料的第一部分的底部没有被去除。
17.根据权利要求14所述的方法,其中,第一保护膜和第二保护膜分别覆盖所述第一管芯和所述第二管芯,其中,当露出所述第一保护膜和所述第二保护膜时,停止所述研磨,并且其中,所述方法还包括:
所述研磨之后,去除所述第一保护膜和所述第二保护膜以分别露出所述第一管芯和所述第二管芯,其中,所述去除之后,露出所述第一金属焊盘和所述第二金属焊盘。
18.根据权利要求14所述的方法,还包括:
形成所述重布线之后,电连接件形成于所述重布线的上方且电连接至所述重布线;以及
进行管芯切割以形成包括所述第一管芯、所述第二管芯、以及所述模塑料的第一和第二部分的封装件。
19.根据权利要求14所述的方法,还包括从所述载体上解接合所述第一管芯、所述第二管芯、以及所述模塑料。
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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9142432B2 (en) * 2013-09-13 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package structures with recesses in molding compound
US9818711B2 (en) 2015-06-30 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and methods thereof
US9786614B2 (en) * 2015-11-16 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure and method of forming
US10020239B2 (en) * 2016-01-12 2018-07-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
TW201729308A (zh) * 2016-02-05 2017-08-16 力成科技股份有限公司 晶圓級封裝結構的製造方法
US10535566B2 (en) * 2016-04-28 2020-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US20170373032A1 (en) * 2016-06-24 2017-12-28 Qualcomm Incorporated Redistribution layer (rdl) fan-out wafer level packaging (fowlp) structure
US10515899B2 (en) * 2016-10-03 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with bump
US10297471B2 (en) * 2016-12-15 2019-05-21 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out structure and method of fabricating the same
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US20200006193A1 (en) * 2018-07-02 2020-01-02 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US20200235066A1 (en) 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
CN113632209A (zh) 2019-01-23 2021-11-09 Qorvo美国公司 Rf半导体装置和其制造方法
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
KR20210157787A (ko) * 2020-06-22 2021-12-29 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
US20220157680A1 (en) * 2020-11-19 2022-05-19 Apple Inc. Flexible Package Architecture Concept in Fanout

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6831352B1 (en) * 1998-10-22 2004-12-14 Azimuth Industrial Company, Inc. Semiconductor package for high frequency performance
CN101443979A (zh) * 2006-02-13 2009-05-27 费查尔德半导体有限公司 用于电池功率控制的多芯片模块
CN101689590A (zh) * 2007-04-18 2010-03-31 克里公司 半导体发光器件封装和方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8361842B2 (en) * 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US8753926B2 (en) * 2010-09-14 2014-06-17 Qualcomm Incorporated Electronic packaging with a variable thickness mold cap
US8936966B2 (en) 2012-02-08 2015-01-20 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods for semiconductor devices
US9064879B2 (en) * 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8105875B1 (en) * 2010-10-14 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Approach for bonding dies onto interposers
JP2013062470A (ja) * 2011-09-15 2013-04-04 Powertech Technology Inc 半導体装置
US8610286B2 (en) * 2011-12-08 2013-12-17 Stats Chippac, Ltd. Semiconductor device and method of forming thick encapsulant for stiffness with recesses for stress relief in Fo-WLCSP
US8778733B2 (en) * 2012-03-19 2014-07-15 Infineon Technologies Ag Semiconductor package and methods of formation thereof
US20130260510A1 (en) * 2012-04-02 2013-10-03 Infineon Technologies Ag 3-D Integrated Circuits and Methods of Forming Thereof
US8941244B1 (en) * 2013-07-03 2015-01-27 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US8952544B2 (en) * 2013-07-03 2015-02-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9142432B2 (en) * 2013-09-13 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package structures with recesses in molding compound
US9184128B2 (en) * 2013-12-13 2015-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC package and methods of forming the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6831352B1 (en) * 1998-10-22 2004-12-14 Azimuth Industrial Company, Inc. Semiconductor package for high frequency performance
CN101443979A (zh) * 2006-02-13 2009-05-27 费查尔德半导体有限公司 用于电池功率控制的多芯片模块
CN101689590A (zh) * 2007-04-18 2010-03-31 克里公司 半导体发光器件封装和方法

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