CN104409490B - SOI substrate double grid insulation tunnelling base bipolar transistor and its manufacture method - Google Patents
SOI substrate double grid insulation tunnelling base bipolar transistor and its manufacture method Download PDFInfo
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- CN104409490B CN104409490B CN201410749132.4A CN201410749132A CN104409490B CN 104409490 B CN104409490 B CN 104409490B CN 201410749132 A CN201410749132 A CN 201410749132A CN 104409490 B CN104409490 B CN 104409490B
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- 238000009413 insulation Methods 0.000 title claims abstract description 104
- 239000000758 substrate Substances 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 230000005641 tunneling Effects 0.000 claims abstract description 78
- 230000000694 effects Effects 0.000 claims abstract description 11
- 230000004888 barrier function Effects 0.000 claims description 54
- 238000005530 etching Methods 0.000 claims description 19
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 8
- 239000002019 doping agent Substances 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000010409 thin film Substances 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 3
- 239000012774 insulation material Substances 0.000 claims description 3
- 239000007769 metal material Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 7
- 239000000126 substance Substances 0.000 claims 2
- 230000002708 enhancing effect Effects 0.000 abstract description 5
- 230000009471 action Effects 0.000 abstract description 3
- 230000035945 sensitivity Effects 0.000 abstract 1
- 238000005520 cutting process Methods 0.000 description 27
- 230000005684 electric field Effects 0.000 description 9
- 230000005611 electricity Effects 0.000 description 6
- 230000000630 rising effect Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000037237 body shape Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
The present invention relates to a kind of SOI substrate double grid insulation tunnelling base bipolar transistor, there is insulation tunneling structure simultaneously in base both sides, insulation tunneling effect is made under the control action of gate electrode while occurring in base both sides, therefore improve the generation rate of tunnelling current；Contrast realizes outstanding switching characteristic with size MOSFETs or TFETs device using the correlation of tunneling insulation layer impedance and its fields inside Qianghian extremely sensitivity；Tunneling through signal enhancing by emitter stage realizes outstanding forward conduction characteristic；The invention also provides a kind of specific manufacture method of SOI substrate double grid insulation tunnelling base bipolar transistor in addition.The transistor significantly improves the working characteristics of nanometer-grade IC unit, it is adaptable to popularization and application.
Description
Technical field
Field is manufactured the present invention relates to super large-scale integration, is related to a kind of integrated suitable for high-performance superelevation integrated level
The SOI substrate double grid insulation tunnelling base bipolar transistor and its manufacture method of circuit manufacture.
Background technology
The elementary cell mos field effect transistor of integrated circuit（MOSFETs）Channel length it is continuous
Shortening result in being decreased obviously for devices switch characteristic.Subthreshold swing is embodied in the reduction of channel length to increase
Greatly, quiescent dissipation substantially increases.Although can delay the degeneration of this device performance by way of improving gate electrode structure
Solution, but when device size further reduces, the switching characteristic of device may proceed to deteriorate.
In contrast to MOSFETs devices, the tunneling field-effect transistor proposed in recent years (TFETs), although its average subthreshold
The value amplitude of oscillation has been lifted, but its forward conduction electric current is too small, although prohibited by introducing compound semiconductor, SiGe or germanium etc.
The narrower material of bandwidth can increase tunnelling probability with lifting switch characteristic to generate TFETs tunnelling part, but add work
Skill difficulty.Insulating medium layer between grid and substrate is used as using high dielectric constant insulating material, although grid can be improved
To the control ability of electric field distribution in channel, the tunnelling probability of silicon materials but can not be inherently improved, therefore for TFETs just
Improve very limited on state characteristic.
The content of the invention
Goal of the invention
To be obviously improved nanometer-grade IC basic unit device on the premise of compatibility is existing based on silicon process technology
Switching characteristic, it is ensured that device reduce subthreshold swing while carried with good forward current on state characteristic, the present invention
For it is a kind of suitable for high-performance, high integration IC manufacturing SOI substrate double grid insulation tunnelling base bipolar transistor and
Its manufacture method.
Technical scheme
The present invention is achieved through the following technical solutions：
SOI substrate double grid insulate tunnelling base bipolar transistor, using comprising monocrystalline substrate 1 and wafer insulating barrier 2
SOI wafer as generating device substrate；Launch site 3, base 4 and collecting zone 5 are located at the top of wafer insulating barrier 2；Emitter stage 9
Top positioned at launch site 3；Colelctor electrode 10 is located at the top of collecting zone 5；Existed by conductive layer 6, tunneling insulation layer 7 and gate electrode 8
The center section of the both sides of base 4 forms sandwich；Barrier insulating layer 11 is dielectric.
To reach device function of the present invention, the present invention proposes SOI substrate double grid insulation tunnelling base bipolar crystal
Pipe and its manufacture method, its core texture are characterized as：
Conductive layer 6 is formed at the both sides of base 4, and is respectively formed Ohmic contact in both sides, is metal material, or same base
Area 4 have identical dopant type and doping concentration be more than 1019Semi-conducting material per cubic centimeter.
Tunneling insulation layer 7 is the insulation material layer for producing tunnelling current, with two independent sectors, each section shape
Into the opposite side of the side that is in contact with base 4 in the both sides conductive layer 6 of base 4.
Gate electrode 8 is the electrode for controlling tunneling insulation layer 7 to produce tunneling effect, is the electricity that control device is switched on and off
Pole, is in contact with the opposite side of the side that is in contact with conductive layer 6 of two independent sectors of tunneling insulation layer 7.
Conductive layer 6, tunneling insulation layer 7 and gate electrode 8 pass through barrier insulating layer 11 and launch site 3, emitter stage 9, current collection
Area 5 and colelctor electrode 10 are mutually isolated.
Conductive layer 6, tunneling insulation layer 7 and gate electrode 8 have collectively constituted SOI substrate double grid insulation tunnelling base bipolar crystal
The tunnelling base stage of pipe, when tunnelling occurs under control of the tunneling insulation layer 7 in gate electrode 8, electric current insulate from gate electrode 8 through tunnelling
Layer 7 flow to conductive layer 6, and is powered for base 4.
There is opposite impurity type between launch site 3 and base 4, between collecting zone 5 and base 4 and launch site 3 and transmitting
Formed between pole 9 between Ohmic contact, collecting zone 3 and colelctor electrode 10 and form Ohmic contact.
SOI substrate double grid insulation tunnelling base bipolar transistor, by taking N-type as an example, 5 points of launch site 3, base 4 and collecting zone
Not Wei N areas, P areas and N areas, its specific operation principle is：When the positively biased of colelctor electrode 10, and gate electrode 8 is when being in low potential, grid electricity
Enough electrical potential differences are not formed between pole 8 and conductive layer 6, now tunneling insulation layer 7 is in high-impedance state, without obvious tunnelling
Electric current passes through, hence in so that can not form sufficiently large base electric current between base 4 and launch site 3 to drive SOI substrate double grid
Insulation tunnelling base bipolar transistor, i.e. device are off state；With gradually rising for the voltage of gate electrode 8, gate electrode 8 with
Electrical potential difference between conductive layer 6 gradually increases so that the electric-field strength between gate electrode 8 and conductive layer 6 in tunneling insulation layer 7
Degree also gradually increases therewith, and when the electric-field intensity in tunneling insulation layer 7 is located at below critical value, tunneling insulation layer 7 is still protected
Good high-impedance state is held, the electrical potential difference between gate electrode and emitter stage almost drops in the inwall of tunneling insulation layer 7 and outer completely
Between wall both sides, the electrical potential difference also allowed between base and launch site is minimum, therefore almost no electric current flows through for base, device
Also good off state is therefore kept, and when the electric-field intensity in tunneling insulation layer 7 is located at more than critical value, tunnelling insulation
Layer 7 can produce obvious tunnelling current due to tunneling effect, and tunnelling current then can with the increase of the potential of gate electrode 8 with
The precipitous rising of speed being exceedingly fast, it is fast by high-impedance state in the extremely short potential change of gate electrode is interval that this allows for tunneling insulation layer 7
Speed is converted to low resistance state, and when tunneling insulation layer 7 is in low resistance state, now tunneling insulation layer 7 is between gate electrode 8 and conductive layer 6
The resistance formed will much smaller than the resistance that is formed between conductive layer 6 and emitter stage 3, this allow for base 4 and launch site 3 it
Between form sufficiently large positive bias-voltage, and in the presence of tunneling effect, between the inner and outer wall of tunneling insulation layer 7
A large amount of electric current movements are produced, conductive layer 6, tunneling insulation layer 7 and gate electrode 8 have collectively constituted SOI substrate double grid insulation tunnelling base
The tunnelling base stage of pole bipolar transistor, when tunnelling occurs under control of the tunneling insulation layer 7 in gate electrode 8, electric current is from gate electrode 8
Conductive layer 6 is flow to through tunneling insulation layer 7, and is powered for base 4；By colelctor electrode stream after the emitted enhancing of area 3 of the electric current of base 4
Go out, now device is in opening.
Advantage and effect
The invention has the advantages that and beneficial effect：
1. high tunnelling current generation rate
SOI substrate double grid insulation tunnelling base bipolar transistor, has insulation tunneling structure simultaneously in the both sides of base 4,
Make insulation tunneling effect under the control action of gate electrode 8 while occurring in base both sides, therefore improve the generation of tunnelling current
Rate.
2. outstanding switching characteristic
SOI substrate double grid insulation tunnelling base bipolar transistor and its manufacture method, utilize tunneling insulation layer impedance and tunnel
Correlation extremely sensitive between insulating barrier electric field intensity inside high is worn, by choosing appropriate runnel insulator to tunneling insulation layer 7
Material, and the height and thickness of tunneling insulation layer 7 are suitably adjusted, so that it may so that tunneling insulation layer 7 is in minimum grid electricity
The conversion between high-impedance state and low resistance state is realized in electrode potential constant interval, it is possible to achieve more excellent switching characteristic.
3. high forward conduction electric current
SOI substrate double grid insulation tunnelling base bipolar transistor, gate insulation tunnelling current flows to base by conductive layer 6,
And signal enhancing is carried out by launch site, it is used as device just with a small amount of semiconductor interband tunnelling current with general T FETs
Conducting electric current compare, with more preferable forward current on state characteristic, for these reasons, in contrast to general T FETs devices,
SOI substrate double grid insulation tunnelling base bipolar transistor can realize higher forward conduction electric current.
Brief description of the drawings
Fig. 1 is the two-dimensional structure schematic top plan view of SOI substrate double grid of the present invention insulation tunnelling base bipolar transistor；
Fig. 2 is Fig. 1 diagrammatic cross-sections that tangentially A cuttings are obtained,
Fig. 3 is Fig. 1 diagrammatic cross-sections that tangentially B cuttings are obtained,
Fig. 4 is the schematic top plan view of step one,
Fig. 5 is Fig. 4 diagrammatic cross-sections that tangentially A cuttings are obtained,
Fig. 6 is the schematic top plan view of step 2,
Fig. 7 be Fig. 6 tangentially A cuttings the step of obtain two diagrammatic cross-section,
Fig. 8 is the schematic top plan view of step 3,
Fig. 9 be Fig. 8 tangentially A cuttings the step of obtain three diagrammatic cross-section,
Figure 10 is the schematic top plan view of step 4,
Figure 11 be Figure 10 tangentially A cuttings the step of obtain four diagrammatic cross-section,
Figure 12 is the schematic top plan view of step 5,
Figure 13 be Figure 12 tangentially B cuttings the step of obtain five diagrammatic cross-section,
Figure 14 is the schematic top plan view of step 6,
Figure 15 be Figure 14 tangentially B cuttings the step of obtain six diagrammatic cross-section,
Figure 16 is the schematic top plan view of step 7,
Figure 17 be Figure 16 tangentially B cuttings the step of obtain seven diagrammatic cross-section,
Figure 18 is the schematic top plan view of step 8,
Figure 19 be Figure 18 tangentially B cuttings the step of obtain eight diagrammatic cross-section,
Figure 20 is the schematic top plan view of step 9,
Figure 21 be Figure 20 tangentially B cuttings the step of obtain nine diagrammatic cross-section,
Figure 22 is the schematic top plan view of step 10,
Figure 23 be Figure 22 tangentially B cuttings the step of obtain ten diagrammatic cross-section,
Figure 24 is the schematic top plan view of step 11,
Figure 25 be Figure 24 tangentially B cuttings the step of obtain 11 diagrammatic cross-section,
Figure 26 is the schematic top plan view of step 12,
Figure 27 be Figure 26 tangentially A cuttings the step of obtain 12 diagrammatic cross-section,
Figure 28 be Figure 26 tangentially B cuttings the step of obtain 12 diagrammatic cross-section,
Figure 29 is the schematic top plan view of step 13,
Figure 30 be Figure 29 tangentially B cuttings the step of obtain 13 diagrammatic cross-section,
Figure 31 is the schematic top plan view of step 14,
Figure 32 be Figure 31 tangentially A cuttings the step of obtain 14 diagrammatic cross-section,
Figure 33 be Figure 31 tangentially B cuttings the step of obtain 14 diagrammatic cross-section,
Figure 34 is the schematic top plan view of step 15,
Figure 35 be Figure 34 tangentially B cuttings the step of obtain 15 diagrammatic cross-section,
Figure 36 is the schematic top plan view of step 10 six,
Figure 37 be Figure 36 tangentially A cuttings the step of obtain 16 diagrammatic cross-section,
Figure 38 be Figure 36 tangentially B cuttings the step of obtain 16 diagrammatic cross-section,
Figure 39 is the schematic top plan view of step 10 seven,
Figure 40 be Figure 39 tangentially A cuttings the step of obtain 17 diagrammatic cross-section,
Figure 41 is the schematic top plan view of step 10 eight,
Figure 42 be Figure 41 tangentially A cuttings the step of obtain 18 diagrammatic cross-section,
Figure 43 be Figure 41 tangentially B cuttings the step of obtain 18 diagrammatic cross-section,
Figure 44 is the schematic top plan view of step 10 nine,
Figure 45 be Figure 44 tangentially A cuttings the step of obtain 19 diagrammatic cross-section.
Description of reference numerals：
1st, monocrystalline substrate；2nd, wafer insulating barrier；3rd, launch site；4th, base；5th, collecting zone；6th, conductive layer；7th, tunnelling is exhausted
Edge layer；8th, gate electrode；9th, emitter stage；10th, colelctor electrode；11st, barrier insulating layer.
Embodiment
The present invention is described further below in conjunction with the accompanying drawings：
Such as the two-dimensional structure schematic top plan view that Fig. 1 is SOI substrate double grid of the present invention insulation tunnelling base bipolar transistor；Figure
2 be Fig. 1 diagrammatic cross-sections that tangentially A cuttings are obtained；Fig. 3 is Fig. 1 diagrammatic cross-sections that tangentially B cuttings are obtained；Specific bag
Include monocrystalline substrate 1；Wafer insulating barrier 2；Launch site 3；Base 4；Collecting zone 5；Conductive layer 6；Tunneling insulation layer 7；Gate electrode 8；
Emitter stage 9；Colelctor electrode 10；Barrier insulating layer 11.
SOI substrate double grid insulate tunnelling base bipolar transistor, using comprising monocrystalline substrate 1 and wafer insulating barrier 2
SOI wafer as generating device substrate；Launch site 3, base 4 and collecting zone 5 are located at the top of wafer insulating barrier 2；Emitter stage 9
Top positioned at launch site 3；Colelctor electrode 10 is located at the top of collecting zone 5；Existed by conductive layer 6, tunneling insulation layer 7 and gate electrode 8
The center section of the both sides of base 4 forms sandwich；Barrier insulating layer 11 is dielectric.
To reach device function of the present invention, the present invention proposes SOI substrate double grid insulation tunnelling base bipolar crystal
Pipe and its manufacture method, its core texture are characterized as：
Conductive layer 6 is formed at the both sides of base 4, and is respectively formed Ohmic contact in both sides, is metal material, or same base
Area 4 have identical dopant type and doping concentration be more than 1019 semi-conducting materials per cubic centimeter.
Tunneling insulation layer 7 is the insulation material layer for producing tunnelling current, with two independent sectors, each section shape
Into the opposite side of the side that is in contact with base 4 in the both sides conductive layer 6 of base 4.
Gate electrode 8 is the electrode for controlling tunneling insulation layer 7 to produce tunneling effect, is the electricity that control device is switched on and off
Pole, is in contact with the opposite side of the side that is in contact with conductive layer 6 of two independent sectors of tunneling insulation layer 7.
Conductive layer 6, tunneling insulation layer 7 and gate electrode 8 are mutual by barrier insulating layer 11 and launch site 3 and collecting zone 5
Isolation.
Conductive layer 6, tunneling insulation layer 7 and gate electrode 8 have collectively constituted SOI substrate double grid insulation tunnelling base bipolar crystal
The tunnelling base stage of pipe, when tunnelling occurs under control of the tunneling insulation layer 7 in gate electrode 8, electric current insulate from gate electrode 8 through tunnelling
Layer 7 flow to conductive layer 6, and is powered for base 4.
There is opposite impurity type between launch site 3 and base 4, between collecting zone 5 and base 4 and launch site 3 and transmitting
Formed between pole 9 between Ohmic contact, collecting zone 3 and colelctor electrode 10 and form Ohmic contact.
SOI substrate double grid insulation tunnelling base bipolar transistor, by taking N-type as an example, 5 points of launch site 3, base 4 and collecting zone
Not Wei N areas, P areas and N areas, its specific operation principle is：When the positively biased of colelctor electrode 10, and gate electrode 8 is when being in low potential, grid electricity
Enough electrical potential differences are not formed between pole 8 and conductive layer 6, now tunneling insulation layer 7 is in high-impedance state, without obvious tunnelling
Electric current passes through, hence in so that can not form sufficiently large base electric current between base 4 and launch site 3 to drive SOI substrate double grid
Insulation tunnelling base bipolar transistor, i.e. device are off state；With gradually rising for the voltage of gate electrode 8, gate electrode 8 with
Electrical potential difference between conductive layer 6 gradually increases so that the electric-field strength between gate electrode 8 and conductive layer 6 in tunneling insulation layer 7
Degree also gradually increases therewith, and when the electric-field intensity in tunneling insulation layer 7 is located at below critical value, tunneling insulation layer 7 is still protected
Good high-impedance state is held, the electrical potential difference between gate electrode and emitter stage almost drops in the inwall of tunneling insulation layer 7 and outer completely
Between wall both sides, the electrical potential difference also allowed between base and launch site is minimum, therefore almost no electric current flows through for base, device
Also good off state is therefore kept, and when the electric-field intensity in tunneling insulation layer 7 is located at more than critical value, tunnelling insulation
Layer 7 can produce obvious tunnelling current due to tunneling effect, and tunnelling current then can with the increase of the potential of gate electrode 8 with
The precipitous rising of speed being exceedingly fast, it is fast by high-impedance state in the extremely short potential change of gate electrode is interval that this allows for tunneling insulation layer 7
Speed is converted to low resistance state, and when tunneling insulation layer 7 is in low resistance state, now tunneling insulation layer 7 is between gate electrode 8 and conductive layer 6
The resistance formed will much smaller than the resistance that is formed between conductive layer 6 and emitter stage 3, this allow for base 4 and launch site 3 it
Between form sufficiently large positive bias-voltage, and in the presence of tunneling effect, between the inner and outer wall of tunneling insulation layer 7
A large amount of electric current movements are produced, conductive layer 6, tunneling insulation layer 7 and gate electrode 8 have collectively constituted SOI substrate double grid insulation tunnelling base
The tunnelling base stage of pole bipolar transistor, when tunnelling occurs under control of the tunneling insulation layer 7 in gate electrode 8, electric current is from gate electrode 8
Conductive layer 6 is flow to through tunneling insulation layer 7, and is powered for base 4；By colelctor electrode stream after the emitted enhancing of area 3 of the electric current of base 4
Go out, now device is in opening.
SOI substrate double grid insulation tunnelling base bipolar transistor, has insulation tunneling structure simultaneously in the both sides of base 4,
Make insulation tunneling effect under the control action of gate electrode 8 while occurring in base both sides, therefore improve the generation of tunnelling current
Rate.
SOI substrate double grid insulation tunnelling base bipolar transistor and its manufacture method, utilize tunneling insulation layer impedance and tunnel
Correlation extremely sensitive between insulating barrier electric field intensity inside high is worn, by choosing appropriate runnel insulator to tunneling insulation layer 7
Material, and the height and thickness of tunneling insulation layer 7 are suitably adjusted, so that it may so that tunneling insulation layer 7 is in minimum grid electricity
The conversion between high-impedance state and low resistance state is realized in electrode potential constant interval, it is possible to achieve more excellent switching characteristic.
SOI substrate double grid insulation tunnelling base bipolar transistor, gate insulation tunnelling current flows to base by conductive layer 6,
And signal enhancing is carried out by launch site, it is used as device just with a small amount of semiconductor interband tunnelling current with general T FETs
Conducting electric current compare, with more preferable forward current on state characteristic, for these reasons, in contrast to general T FETs devices,
SOI substrate double grid insulation tunnelling base bipolar transistor can realize higher forward conduction electric current.
The unit and array of SOI substrate double grid insulation tunnelling base bipolar transistor proposed by the invention are in SOI wafer
On specific manufacturing technology steps it is as follows：
Step 1: there is provided a SOI wafer as shown in Fig. 4 to Fig. 5, the lower section of SOI wafer is the monocrystalline silicon of SOI wafer
Substrate 1, the centre of SOI wafer is wafer insulating barrier 2, by ion implanting or diffusion technique, to the monocrystalline silicon above SOI wafer
Film is doped, and preliminarily forms base 4.
Step 2: as shown in Figure 6 to 7, again by ion implanting or diffusion technique, to the monocrystalline above SOI wafer
Silicon thin film is doped, and forming, concentration opposite with the dopant type in step one in wafer upper surface is not less than 1019Every cube
Centimetre heavily doped region.
Step 3: as shown in Fig. 8 to Fig. 9, forming rectangular in the SOI wafer provided by techniques such as photoetching, etchings
Body shape monocrystalline silicon isolated island queue.
Step 4: as shown in Figure 10 to Figure 11, planarization surface is to exposing monocrystalline after deposit dielectric above wafer
Silicon thin film, preliminarily forms barrier insulating layer 11.
Step 5: as shown in Figure 12 to Figure 13, further by techniques such as photoetching, etchings in the SOI wafer provided
Form rectangular-shape monocrystalline silicon isolated island array.
Step 6: as shown in Figure 14 to Figure 15, planarization surface is to exposing transmitting after deposit dielectric above wafer
Area 3, base 4 and collecting zone 5, further form barrier insulating layer 11.
Step 7: as shown in Figure 16 to Figure 17, by etching technics, the stop to crystal column surface base both sides center section
Insulating barrier 11 is performed etching to exposing wafer insulating barrier 2.
Step 8: as shown in Figure 18 to Figure 19, deposited above wafer metal or with the identical dopant type in base 4
The polysilicon of heavy doping, is completely filled the barrier insulating layer 11 being etched away in step 7, then surface planarisation is extremely revealed
Go out launch site 3, base 4, collecting zone 5 and barrier insulating layer 11, form conductive layer 6.
Step 9: as shown in Figure 20 to Figure 21, respectively base both sides conductive layer 6 remote base side to stopping
Insulating barrier 11 is performed etching to exposing wafer insulating barrier 2.
Step 10: as shown in Figure 22 to Figure 23, tunneling insulation layer medium being deposited above wafer, makes to be etched in step 9
The barrier insulating layer 11 fallen is tunneled over insulating dielectric layer and is filled up completely with, then by surface planarisation to expose launch site 3, base 4, collection
Electric area 5, conductive layer 6 and barrier insulating layer 11, form tunneling insulation layer 7.
Step 11: as shown in Figure 24 to Figure 25, respectively base both sides tunneling insulation layer 7 remote base side
Barrier insulating layer 11 is performed etching to exposing wafer insulating barrier 2.
Step 12: as shown in Figure 26 to Figure 28, metal or the polysilicon of heavy doping being deposited above wafer, makes step 10
The barrier insulating layer 11 being etched away in one is completely filled.
Step 13: as shown in Figure 29 to 30, by surface planarisation to exposing launch site 3, it is base 4, collecting zone 5, conductive
Layer 6, tunneling insulation layer 7 and barrier insulating layer 11, preliminarily form gate electrode 8.
Step 14: as shown in Figure 31 to Figure 33, dielectric being deposited above wafer, barrier insulating layer is further formed
11。
Step 15: as shown in Figure 34 to Figure 35, by etching technics by positioned at the barrier insulating layer 11 of the top of gate electrode 8
Etch away.
Step 16: as shown in Figure 36 to Figure 38, metal or the polysilicon of heavy doping being deposited above wafer, makes step 10
The barrier insulating layer 11 being etched away in four is completely filled, by surface planarisation, further forms gate electrode 8.
Step 17: as shown in Figure 39 to Figure 40, being etched away by etching technics is used to form cabling between device cell
Part beyond part, further forms gate electrode 8.
Step 18: as shown in Figure 41 to Figure 43, dielectric is deposited above wafer, by surface planarisation, further
Form barrier insulating layer 11.
Step 19: as shown in Figure 44 to 45, the top positioned at launch site 3 and collecting zone 5 is etched away by etching technics
Barrier insulating layer 11, form the through hole of emitter stage 9 and colelctor electrode 10.
Step 20: as shown in Figure 1 to Figure 3, metal is deposited above wafer, make the emitter stage 9 formed in step 10 eight
It is completely filled with the through hole of colelctor electrode 10, and passes through etching technics formation emitter stage 9 and colelctor electrode 10.
Claims (7)
1.SOI substrates double grid insulation tunnelling base bipolar transistor, it is characterised in that：Using including monocrystalline substrate（1）And crystalline substance
Circle insulating barrier（2）SOI wafer as generating device substrate；Launch site（3）, base（4）And collecting zone（5）It is exhausted positioned at wafer
Edge layer（2）Top, base（4）Positioned at launch site（3）And collecting zone（5）Between；Emitter stage（9）Positioned at launch site（3）It is upper
Side；Colelctor electrode（10）Positioned at collecting zone（5）Top；By conductive layer（6）, tunneling insulation layer（7）And gate electrode（8）Successively in base
Area（4）Both sides center section formed sandwich；Barrier insulating layer（11）For dielectric；Conductive layer（6）, tunnelling insulation
Layer（7）And gate electrode（8）Pass through barrier insulating layer（11）With launch site（3）, emitter stage（9）, collecting zone（5）And colelctor electrode
（10）It is mutually isolated.
The tunnelling base bipolar transistor 2. SOI substrate double grid according to claim 1 insulate, it is characterised in that：Conductive layer
（6）It is formed at base（4）Both sides, and be respectively formed in both sides Ohmic contact, conductive layer（6）It is metal material either same base
（4）With identical dopant type and doping concentration is more than 1019Semi-conducting material per cubic centimeter.
The tunnelling base bipolar transistor 3. SOI substrate double grid according to claim 1 insulate, it is characterised in that：Tunnelling is exhausted
Edge layer（7）For the insulation material layer for producing tunnelling current, with two independent sectors, each section is formed at base（4）
Both sides conductive layer（6）With base（4）Be in contact the opposite side of side.
The tunnelling base bipolar transistor 4. SOI substrate double grid according to claim 1 insulate, it is characterised in that：Gate electrode
（8）It is control tunneling insulation layer（7）The electrode of tunneling effect is produced, is the electrode that control device is switched on and off, it is exhausted with tunnelling
Edge layer（7）Two independent sectors and conductive layer（6）The opposite side of side of being in contact is in contact.
The tunnelling base bipolar transistor 5. SOI substrate double grid according to claim 1 insulate, it is characterised in that：Conductive layer
（6）, tunneling insulation layer（7）And gate electrode（8）The tunnelling of SOI substrate double grid insulation tunnelling base bipolar transistor is collectively constituted
Base stage, works as tunneling insulation layer（7）In gate electrode（8）Control under when occurring tunnelling, electric current is from gate electrode（8）Through tunneling insulation layer
（7）It flow to conductive layer（6）, and be base（4）Power supply.
The tunnelling base bipolar transistor 6. SOI substrate double grid according to claim 1 insulate, it is characterised in that：Launch site
（3）With base（4）Between, collecting zone（5）With base（4）Between there is opposite impurity type, and launch site（3）With emitter stage
（9）Between formed Ohmic contact, collecting zone（3）With colelctor electrode（10）Between form Ohmic contact.
The manufacture method of tunnelling base bipolar transistor, its feature 7. a kind of SOI substrate double grid as claimed in claim 1 insulate
It is：The processing step is as follows：
Step 1: providing a SOI wafer, the lower section of SOI wafer is the monocrystalline substrate of SOI wafer（1）, in SOI wafer
Between be wafer insulating barrier（2）, by ion implanting or diffusion technique, the monocrystalline silicon thin film above SOI wafer is doped, just
Step forms base（4）；
Step 2: again by ion implanting or diffusion technique, being doped to the monocrystalline silicon thin film above SOI wafer, in crystalline substance
Circle upper surface forms, concentration opposite with the dopant type in step one and is not less than 1019Heavily doped region per cubic centimeter；
Step 3: rectangular-shape monocrystalline silicon isolated island queue is formed in the SOI wafer provided by photoetching, etching technics；
Step 4: planarization surface preliminarily forms stop exhausted to monocrystalline silicon thin film is exposed after deposit dielectric above wafer
Edge layer（11）；
Step 5: rectangular-shape monocrystalline silicon isolated island battle array is further formed in the SOI wafer provided by photoetching, etching technics
Row；
Step 6: above the wafer after deposit dielectric planarization surface to exposing launch site（3）, base（4）And collecting zone
（5）, further form barrier insulating layer（11）；
Step 7: by etching technics, to the barrier insulating layer of crystal column surface base both sides center section（11）Perform etching to
Expose wafer insulating barrier（2）；
Step 8: depositing metal above wafer or having and base（4）The polysilicon of the heavy doping of identical dopant type, makes step
The barrier insulating layer being etched away in rapid seven（11）It is completely filled, then by surface planarisation to exposing launch site（3）, base
（4）, collecting zone（5）And barrier insulating layer（11）, form conductive layer（6）；
Step 9: respectively in the conductive layer of base both sides（6）Remote base side to barrier insulating layer（11）Perform etching
To exposing wafer insulating barrier（2）；
Step 10: depositing tunneling insulation layer medium above wafer, make the barrier insulating layer being etched away in step 9（11）Quilt
Tunneling insulation layer medium is filled up completely with, then by surface planarisation to exposing launch site（3）, base（4）, collecting zone（5）, conductive layer
（6）And barrier insulating layer（11）, form tunneling insulation layer（7）；
Step 11: respectively in the tunneling insulation layer of base both sides（7）Remote base side to barrier insulating layer（11）Enter
Row, which is etched to, exposes wafer insulating barrier（2）；
Step 12: depositing metal or the polysilicon of heavy doping above wafer, make the stop being etched away in step 11 exhausted
Edge layer（11）It is completely filled；
Step 13: by surface planarisation to exposing launch site（3）, base（4）, collecting zone（5）, conductive layer（6）, tunnelling insulation
Layer（7）And barrier insulating layer（11）, preliminarily form gate electrode（8）；
Step 14: depositing dielectric above wafer, barrier insulating layer is further formed（11）；
Step 15: gate electrode will be located at by etching technics（8）The barrier insulating layer of top（11）Etch away；
Step 16: depositing metal or the polysilicon of heavy doping above wafer, make the stop being etched away in step 15 exhausted
Edge layer（11）It is completely filled, by surface planarisation, further forms gate electrode（8）；
Step 17: being etched away for forming the part between device cell beyond trace portions, further by etching technics
Form gate electrode（8）；
Step 18: depositing dielectric above wafer, by surface planarisation, barrier insulating layer is further formed（11）；
Step 19: being etched away by etching technics positioned at launch site（3）And collecting zone（5）Top barrier insulating layer
（11）, form emitter stage（9）And colelctor electrode（10）Through hole；
Step 20: depositing metal above wafer, make the emitter stage formed in step 10 eight（9）And colelctor electrode（10）Through hole
It is completely filled, and emitter stage is formed by etching technics（9）And colelctor electrode（10）.
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| CN102208446A (en) * | 2011-04-20 | 2011-10-05 | 北京大学 | Tunneling current amplification transistor |
| CN103474459A (en) * | 2013-09-06 | 2013-12-25 | 北京大学深圳研究生院 | Tunneling field effect transistor |
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| CN102208446A (en) * | 2011-04-20 | 2011-10-05 | 北京大学 | Tunneling current amplification transistor |
| CN103474459A (en) * | 2013-09-06 | 2013-12-25 | 北京大学深圳研究生院 | Tunneling field effect transistor |
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